Revision a455783b
| b/hw/apb_pci.c | ||
|---|---|---|
| 54 | 54 |
PCIHostState host_state; |
| 55 | 55 |
} APBState; |
| 56 | 56 |
|
| 57 |
static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr, |
|
| 58 |
uint32_t val) |
|
| 59 |
{
|
|
| 60 |
APBState *s = opaque; |
|
| 61 |
|
|
| 62 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 63 |
val = bswap32(val); |
|
| 64 |
#endif |
|
| 65 |
APB_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
|
|
| 66 |
val); |
|
| 67 |
s->host_state.config_reg = val; |
|
| 68 |
} |
|
| 69 |
|
|
| 70 |
static uint32_t pci_apb_config_readl (void *opaque, |
|
| 71 |
target_phys_addr_t addr) |
|
| 72 |
{
|
|
| 73 |
APBState *s = opaque; |
|
| 74 |
uint32_t val; |
|
| 75 |
|
|
| 76 |
val = s->host_state.config_reg; |
|
| 77 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 78 |
val = bswap32(val); |
|
| 79 |
#endif |
|
| 80 |
APB_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
|
|
| 81 |
val); |
|
| 82 |
return val; |
|
| 83 |
} |
|
| 84 |
|
|
| 85 |
static CPUWriteMemoryFunc * const pci_apb_config_write[] = {
|
|
| 86 |
&pci_apb_config_writel, |
|
| 87 |
&pci_apb_config_writel, |
|
| 88 |
&pci_apb_config_writel, |
|
| 89 |
}; |
|
| 90 |
|
|
| 91 |
static CPUReadMemoryFunc * const pci_apb_config_read[] = {
|
|
| 92 |
&pci_apb_config_readl, |
|
| 93 |
&pci_apb_config_readl, |
|
| 94 |
&pci_apb_config_readl, |
|
| 95 |
}; |
|
| 96 |
|
|
| 97 | 57 |
static void apb_config_writel (void *opaque, target_phys_addr_t addr, |
| 98 | 58 |
uint32_t val) |
| 99 | 59 |
{
|
| ... | ... | |
| 275 | 235 |
pci_apb_iowrite, s); |
| 276 | 236 |
sysbus_init_mmio(dev, 0x10000ULL, pci_ioport); |
| 277 | 237 |
/* mem_config */ |
| 278 |
pci_mem_config = cpu_register_io_memory(pci_apb_config_read, |
|
| 279 |
pci_apb_config_write, s); |
|
| 238 |
pci_mem_config = pci_host_config_register_io_memory(&s->host_state); |
|
| 280 | 239 |
sysbus_init_mmio(dev, 0x10ULL, pci_mem_config); |
| 281 | 240 |
/* mem_data */ |
| 282 | 241 |
pci_mem_data = pci_host_data_register_io_memory(&s->host_state); |
| b/hw/grackle_pci.c | ||
|---|---|---|
| 43 | 43 |
PCIHostState host_state; |
| 44 | 44 |
} GrackleState; |
| 45 | 45 |
|
| 46 |
static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, |
|
| 47 |
uint32_t val) |
|
| 48 |
{
|
|
| 49 |
GrackleState *s = opaque; |
|
| 50 |
|
|
| 51 |
GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
|
|
| 52 |
val); |
|
| 53 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 54 |
val = bswap32(val); |
|
| 55 |
#endif |
|
| 56 |
s->host_state.config_reg = val; |
|
| 57 |
} |
|
| 58 |
|
|
| 59 |
static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) |
|
| 60 |
{
|
|
| 61 |
GrackleState *s = opaque; |
|
| 62 |
uint32_t val; |
|
| 63 |
|
|
| 64 |
val = s->host_state.config_reg; |
|
| 65 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 66 |
val = bswap32(val); |
|
| 67 |
#endif |
|
| 68 |
GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
|
|
| 69 |
val); |
|
| 70 |
return val; |
|
| 71 |
} |
|
| 72 |
|
|
| 73 |
static CPUWriteMemoryFunc * const pci_grackle_config_write[] = {
|
|
| 74 |
&pci_grackle_config_writel, |
|
| 75 |
&pci_grackle_config_writel, |
|
| 76 |
&pci_grackle_config_writel, |
|
| 77 |
}; |
|
| 78 |
|
|
| 79 |
static CPUReadMemoryFunc * const pci_grackle_config_read[] = {
|
|
| 80 |
&pci_grackle_config_readl, |
|
| 81 |
&pci_grackle_config_readl, |
|
| 82 |
&pci_grackle_config_readl, |
|
| 83 |
}; |
|
| 84 |
|
|
| 85 | 46 |
/* Don't know if this matches real hardware, but it agrees with OHW. */ |
| 86 | 47 |
static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) |
| 87 | 48 |
{
|
| ... | ... | |
| 147 | 108 |
|
| 148 | 109 |
s = FROM_SYSBUS(GrackleState, dev); |
| 149 | 110 |
|
| 150 |
pci_mem_config = cpu_register_io_memory(pci_grackle_config_read, |
|
| 151 |
pci_grackle_config_write, s); |
|
| 111 |
pci_mem_config = pci_host_config_register_io_memory(&s->host_state); |
|
| 152 | 112 |
pci_mem_data = pci_host_data_register_io_memory(&s->host_state); |
| 153 | 113 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
| 154 | 114 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
| ... | ... | |
| 166 | 126 |
|
| 167 | 127 |
s = FROM_SYSBUS(GrackleState, dev); |
| 168 | 128 |
|
| 169 |
pci_mem_config = cpu_register_io_memory(pci_grackle_config_read, |
|
| 170 |
pci_grackle_config_write, s); |
|
| 129 |
pci_mem_config = pci_host_config_register_io_memory(&s->host_state); |
|
| 171 | 130 |
pci_mem_data = pci_host_data_register_io_memory(&s->host_state); |
| 172 | 131 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
| 173 | 132 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
| b/hw/pci_host.c | ||
|---|---|---|
| 32 | 32 |
#define PCI_DPRINTF(fmt, ...) |
| 33 | 33 |
#endif |
| 34 | 34 |
|
| 35 |
static void pci_host_config_writel(void *opaque, target_phys_addr_t addr, |
|
| 36 |
uint32_t val) |
|
| 37 |
{
|
|
| 38 |
PCIHostState *s = opaque; |
|
| 39 |
|
|
| 40 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 41 |
val = bswap32(val); |
|
| 42 |
#endif |
|
| 43 |
PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
|
|
| 44 |
__func__, addr, val); |
|
| 45 |
s->config_reg = val; |
|
| 46 |
} |
|
| 47 |
|
|
| 48 |
static uint32_t pci_host_config_readl(void *opaque, target_phys_addr_t addr) |
|
| 49 |
{
|
|
| 50 |
PCIHostState *s = opaque; |
|
| 51 |
uint32_t val = s->config_reg; |
|
| 52 |
|
|
| 53 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 54 |
val = bswap32(val); |
|
| 55 |
#endif |
|
| 56 |
PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
|
|
| 57 |
__func__, addr, val); |
|
| 58 |
return val; |
|
| 59 |
} |
|
| 60 |
|
|
| 61 |
static CPUWriteMemoryFunc * const pci_host_config_write[] = {
|
|
| 62 |
&pci_host_config_writel, |
|
| 63 |
&pci_host_config_writel, |
|
| 64 |
&pci_host_config_writel, |
|
| 65 |
}; |
|
| 66 |
|
|
| 67 |
static CPUReadMemoryFunc * const pci_host_config_read[] = {
|
|
| 68 |
&pci_host_config_readl, |
|
| 69 |
&pci_host_config_readl, |
|
| 70 |
&pci_host_config_readl, |
|
| 71 |
}; |
|
| 72 |
|
|
| 73 |
int pci_host_config_register_io_memory(PCIHostState *s) |
|
| 74 |
{
|
|
| 75 |
return cpu_register_io_memory(pci_host_config_read, |
|
| 76 |
pci_host_config_write, s); |
|
| 77 |
} |
|
| 78 |
|
|
| 79 |
static void pci_host_config_writel_noswap(void *opaque, |
|
| 80 |
target_phys_addr_t addr, |
|
| 81 |
uint32_t val) |
|
| 82 |
{
|
|
| 83 |
PCIHostState *s = opaque; |
|
| 84 |
|
|
| 85 |
PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
|
|
| 86 |
__func__, addr, val); |
|
| 87 |
s->config_reg = val; |
|
| 88 |
} |
|
| 89 |
|
|
| 90 |
static uint32_t pci_host_config_readl_noswap(void *opaque, |
|
| 91 |
target_phys_addr_t addr) |
|
| 92 |
{
|
|
| 93 |
PCIHostState *s = opaque; |
|
| 94 |
uint32_t val = s->config_reg; |
|
| 95 |
|
|
| 96 |
PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
|
|
| 97 |
__func__, addr, val); |
|
| 98 |
return val; |
|
| 99 |
} |
|
| 100 |
|
|
| 101 |
static CPUWriteMemoryFunc * const pci_host_config_write_noswap[] = {
|
|
| 102 |
&pci_host_config_writel_noswap, |
|
| 103 |
&pci_host_config_writel_noswap, |
|
| 104 |
&pci_host_config_writel_noswap, |
|
| 105 |
}; |
|
| 106 |
|
|
| 107 |
static CPUReadMemoryFunc * const pci_host_config_read_noswap[] = {
|
|
| 108 |
&pci_host_config_readl_noswap, |
|
| 109 |
&pci_host_config_readl_noswap, |
|
| 110 |
&pci_host_config_readl_noswap, |
|
| 111 |
}; |
|
| 112 |
|
|
| 113 |
int pci_host_config_register_io_memory_noswap(PCIHostState *s) |
|
| 114 |
{
|
|
| 115 |
return cpu_register_io_memory(pci_host_config_read_noswap, |
|
| 116 |
pci_host_config_write_noswap, s); |
|
| 117 |
} |
|
| 118 |
|
|
| 119 |
static void pci_host_config_writel_ioport(void *opaque, |
|
| 120 |
uint32_t addr, uint32_t val) |
|
| 121 |
{
|
|
| 122 |
PCIHostState *s = opaque; |
|
| 123 |
|
|
| 124 |
PCI_DPRINTF("%s addr %"PRIx32 " val %"PRIx32"\n", __func__, addr, val);
|
|
| 125 |
s->config_reg = val; |
|
| 126 |
} |
|
| 127 |
|
|
| 128 |
static uint32_t pci_host_config_readl_ioport(void *opaque, uint32_t addr) |
|
| 129 |
{
|
|
| 130 |
PCIHostState *s = opaque; |
|
| 131 |
uint32_t val = s->config_reg; |
|
| 132 |
|
|
| 133 |
PCI_DPRINTF("%s addr %"PRIx32" val %"PRIx32"\n", __func__, addr, val);
|
|
| 134 |
return val; |
|
| 135 |
} |
|
| 136 |
|
|
| 137 |
void pci_host_config_register_ioport(pio_addr_t ioport, PCIHostState *s) |
|
| 138 |
{
|
|
| 139 |
register_ioport_write(ioport, 4, 4, pci_host_config_writel_ioport, s); |
|
| 140 |
register_ioport_read(ioport, 4, 4, pci_host_config_readl_ioport, s); |
|
| 141 |
} |
|
| 142 |
|
|
| 35 | 143 |
#define PCI_ADDR_T target_phys_addr_t |
| 36 | 144 |
#define PCI_HOST_SUFFIX _mmio |
| 37 | 145 |
|
| b/hw/pci_host.h | ||
|---|---|---|
| 37 | 37 |
} PCIHostState; |
| 38 | 38 |
|
| 39 | 39 |
/* for mmio */ |
| 40 |
int pci_host_config_register_io_memory(PCIHostState *s); |
|
| 41 |
int pci_host_config_register_io_memory_noswap(PCIHostState *s); |
|
| 40 | 42 |
int pci_host_data_register_io_memory(PCIHostState *s); |
| 41 | 43 |
|
| 42 | 44 |
/* for ioio */ |
| 45 |
void pci_host_config_register_ioport(pio_addr_t ioport, PCIHostState *s); |
|
| 43 | 46 |
void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s); |
| 44 | 47 |
|
| 45 | 48 |
#endif /* PCI_HOST_H */ |
| b/hw/piix_pci.c | ||
|---|---|---|
| 44 | 44 |
PIIX3State *piix3; |
| 45 | 45 |
}; |
| 46 | 46 |
|
| 47 |
static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
|
| 48 |
{
|
|
| 49 |
I440FXState *s = opaque; |
|
| 50 |
s->config_reg = val; |
|
| 51 |
} |
|
| 52 |
|
|
| 53 |
static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr) |
|
| 54 |
{
|
|
| 55 |
I440FXState *s = opaque; |
|
| 56 |
return s->config_reg; |
|
| 57 |
} |
|
| 58 |
|
|
| 59 | 47 |
static void piix3_set_irq(void *opaque, int irq_num, int level); |
| 60 | 48 |
|
| 61 | 49 |
/* return the global irq number corresponding to a given device irq |
| ... | ... | |
| 192 | 180 |
{
|
| 193 | 181 |
I440FXState *s = FROM_SYSBUS(I440FXState, dev); |
| 194 | 182 |
|
| 195 |
register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s); |
|
| 196 |
register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s); |
|
| 183 |
pci_host_config_register_ioport(0xcf8, s); |
|
| 197 | 184 |
|
| 198 | 185 |
pci_host_data_register_ioport(0xcfc, s); |
| 199 | 186 |
return 0; |
| b/hw/ppce500_pci.c | ||
|---|---|---|
| 84 | 84 |
|
| 85 | 85 |
typedef struct PPCE500PCIState PPCE500PCIState; |
| 86 | 86 |
|
| 87 |
static uint32_t pcie500_cfgaddr_readl(void *opaque, target_phys_addr_t addr) |
|
| 88 |
{
|
|
| 89 |
PPCE500PCIState *pci = opaque; |
|
| 90 |
|
|
| 91 |
pci_debug("%s: (addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, addr,
|
|
| 92 |
pci->pci_state.config_reg); |
|
| 93 |
return pci->pci_state.config_reg; |
|
| 94 |
} |
|
| 95 |
|
|
| 96 |
static CPUReadMemoryFunc * const pcie500_cfgaddr_read[] = {
|
|
| 97 |
&pcie500_cfgaddr_readl, |
|
| 98 |
&pcie500_cfgaddr_readl, |
|
| 99 |
&pcie500_cfgaddr_readl, |
|
| 100 |
}; |
|
| 101 |
|
|
| 102 |
static void pcie500_cfgaddr_writel(void *opaque, target_phys_addr_t addr, |
|
| 103 |
uint32_t value) |
|
| 104 |
{
|
|
| 105 |
PPCE500PCIState *controller = opaque; |
|
| 106 |
|
|
| 107 |
pci_debug("%s: value:%x -> (addr:" TARGET_FMT_plx ")\n", __func__, value,
|
|
| 108 |
addr); |
|
| 109 |
controller->pci_state.config_reg = value & ~0x3; |
|
| 110 |
} |
|
| 111 |
|
|
| 112 |
static CPUWriteMemoryFunc * const pcie500_cfgaddr_write[] = {
|
|
| 113 |
&pcie500_cfgaddr_writel, |
|
| 114 |
&pcie500_cfgaddr_writel, |
|
| 115 |
&pcie500_cfgaddr_writel, |
|
| 116 |
}; |
|
| 117 |
|
|
| 118 | 87 |
static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr) |
| 119 | 88 |
{
|
| 120 | 89 |
PPCE500PCIState *pci = opaque; |
| ... | ... | |
| 324 | 293 |
controller->pci_dev = d; |
| 325 | 294 |
|
| 326 | 295 |
/* CFGADDR */ |
| 327 |
index = cpu_register_io_memory(pcie500_cfgaddr_read, |
|
| 328 |
pcie500_cfgaddr_write, controller); |
|
| 296 |
index = pci_host_config_register_io_memory_noswap(&controller->pci_state); |
|
| 329 | 297 |
if (index < 0) |
| 330 | 298 |
goto free; |
| 331 | 299 |
cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index); |
| b/hw/prep_pci.c | ||
|---|---|---|
| 28 | 28 |
|
| 29 | 29 |
typedef PCIHostState PREPPCIState; |
| 30 | 30 |
|
| 31 |
static void pci_prep_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
|
| 32 |
{
|
|
| 33 |
PREPPCIState *s = opaque; |
|
| 34 |
s->config_reg = val; |
|
| 35 |
} |
|
| 36 |
|
|
| 37 |
static uint32_t pci_prep_addr_readl(void* opaque, uint32_t addr) |
|
| 38 |
{
|
|
| 39 |
PREPPCIState *s = opaque; |
|
| 40 |
return s->config_reg; |
|
| 41 |
} |
|
| 42 |
|
|
| 43 | 31 |
static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr) |
| 44 | 32 |
{
|
| 45 | 33 |
int i; |
| ... | ... | |
| 139 | 127 |
s->bus = pci_register_bus(NULL, "pci", |
| 140 | 128 |
prep_set_irq, prep_map_irq, pic, 0, 4); |
| 141 | 129 |
|
| 142 |
register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s); |
|
| 143 |
register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s); |
|
| 130 |
pci_host_config_register_ioport(0xcf8, s); |
|
| 144 | 131 |
|
| 145 | 132 |
pci_host_data_register_ioport(0xcfc, s); |
| 146 | 133 |
|
| b/hw/unin_pci.c | ||
|---|---|---|
| 41 | 41 |
PCIHostState host_state; |
| 42 | 42 |
} UNINState; |
| 43 | 43 |
|
| 44 |
static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, |
|
| 45 |
uint32_t val) |
|
| 46 |
{
|
|
| 47 |
UNINState *s = opaque; |
|
| 48 |
|
|
| 49 |
UNIN_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, val);
|
|
| 50 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 51 |
val = bswap32(val); |
|
| 52 |
#endif |
|
| 53 |
|
|
| 54 |
s->host_state.config_reg = val; |
|
| 55 |
} |
|
| 56 |
|
|
| 57 |
static uint32_t pci_unin_main_config_readl (void *opaque, |
|
| 58 |
target_phys_addr_t addr) |
|
| 59 |
{
|
|
| 60 |
UNINState *s = opaque; |
|
| 61 |
uint32_t val; |
|
| 62 |
|
|
| 63 |
val = s->host_state.config_reg; |
|
| 64 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 65 |
val = bswap32(val); |
|
| 66 |
#endif |
|
| 67 |
UNIN_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, val);
|
|
| 68 |
|
|
| 69 |
return val; |
|
| 70 |
} |
|
| 71 |
|
|
| 72 |
static CPUWriteMemoryFunc * const pci_unin_main_config_write[] = {
|
|
| 73 |
&pci_unin_main_config_writel, |
|
| 74 |
&pci_unin_main_config_writel, |
|
| 75 |
&pci_unin_main_config_writel, |
|
| 76 |
}; |
|
| 77 |
|
|
| 78 |
static CPUReadMemoryFunc * const pci_unin_main_config_read[] = {
|
|
| 79 |
&pci_unin_main_config_readl, |
|
| 80 |
&pci_unin_main_config_readl, |
|
| 81 |
&pci_unin_main_config_readl, |
|
| 82 |
}; |
|
| 83 |
|
|
| 84 |
static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr, |
|
| 85 |
uint32_t val) |
|
| 86 |
{
|
|
| 87 |
UNINState *s = opaque; |
|
| 88 |
|
|
| 89 |
s->host_state.config_reg = val; |
|
| 90 |
} |
|
| 91 |
|
|
| 92 |
static uint32_t pci_unin_config_readl (void *opaque, |
|
| 93 |
target_phys_addr_t addr) |
|
| 94 |
{
|
|
| 95 |
UNINState *s = opaque; |
|
| 96 |
|
|
| 97 |
return s->host_state.config_reg; |
|
| 98 |
} |
|
| 99 |
|
|
| 100 |
static CPUWriteMemoryFunc * const pci_unin_config_write[] = {
|
|
| 101 |
&pci_unin_config_writel, |
|
| 102 |
&pci_unin_config_writel, |
|
| 103 |
&pci_unin_config_writel, |
|
| 104 |
}; |
|
| 105 |
|
|
| 106 |
static CPUReadMemoryFunc * const pci_unin_config_read[] = {
|
|
| 107 |
&pci_unin_config_readl, |
|
| 108 |
&pci_unin_config_readl, |
|
| 109 |
&pci_unin_config_readl, |
|
| 110 |
}; |
|
| 111 |
|
|
| 112 | 44 |
/* Don't know if this matches real hardware, but it agrees with OHW. */ |
| 113 | 45 |
static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) |
| 114 | 46 |
{
|
| ... | ... | |
| 152 | 84 |
/* Uninorth main bus */ |
| 153 | 85 |
s = FROM_SYSBUS(UNINState, dev); |
| 154 | 86 |
|
| 155 |
pci_mem_config = cpu_register_io_memory(pci_unin_main_config_read, |
|
| 156 |
pci_unin_main_config_write, s); |
|
| 87 |
pci_mem_config = pci_host_config_register_io_memory(&s->host_state); |
|
| 157 | 88 |
pci_mem_data = pci_host_data_register_io_memory(&s->host_state); |
| 158 |
|
|
| 159 | 89 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
| 160 | 90 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
| 161 | 91 |
|
| ... | ... | |
| 173 | 103 |
s = FROM_SYSBUS(UNINState, dev); |
| 174 | 104 |
|
| 175 | 105 |
// XXX: s = &pci_bridge[2]; |
| 176 |
pci_mem_config = cpu_register_io_memory(pci_unin_config_read, |
|
| 177 |
pci_unin_config_write, s); |
|
| 106 |
pci_mem_config = pci_host_config_register_io_memory_noswap(&s->host_state); |
|
| 178 | 107 |
pci_mem_data = pci_host_data_register_io_memory(&s->host_state); |
| 179 | 108 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
| 180 | 109 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
| ... | ... | |
| 189 | 118 |
/* Uninorth AGP bus */ |
| 190 | 119 |
s = FROM_SYSBUS(UNINState, dev); |
| 191 | 120 |
|
| 192 |
pci_mem_config = cpu_register_io_memory(pci_unin_config_read, |
|
| 193 |
pci_unin_config_write, s); |
|
| 121 |
pci_mem_config = pci_host_config_register_io_memory_noswap(&s->host_state); |
|
| 194 | 122 |
pci_mem_data = pci_host_data_register_io_memory(&s->host_state); |
| 195 | 123 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
| 196 | 124 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
| ... | ... | |
| 205 | 133 |
/* Uninorth internal bus */ |
| 206 | 134 |
s = FROM_SYSBUS(UNINState, dev); |
| 207 | 135 |
|
| 208 |
pci_mem_config = cpu_register_io_memory(pci_unin_config_read, |
|
| 209 |
pci_unin_config_write, s); |
|
| 136 |
pci_mem_config = pci_host_config_register_io_memory_noswap(&s->host_state); |
|
| 210 | 137 |
pci_mem_data = pci_host_data_register_io_memory(&s->host_state); |
| 211 | 138 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
| 212 | 139 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
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