Revision a455783b hw/grackle_pci.c

b/hw/grackle_pci.c
43 43
    PCIHostState host_state;
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} GrackleState;
45 45

  
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static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
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                                       uint32_t val)
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{
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    GrackleState *s = opaque;
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    GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
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                    val);
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#ifdef TARGET_WORDS_BIGENDIAN
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    val = bswap32(val);
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#endif
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    s->host_state.config_reg = val;
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}
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static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
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{
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    GrackleState *s = opaque;
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    uint32_t val;
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    val = s->host_state.config_reg;
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#ifdef TARGET_WORDS_BIGENDIAN
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    val = bswap32(val);
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#endif
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    GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
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                    val);
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    return val;
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}
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static CPUWriteMemoryFunc * const pci_grackle_config_write[] = {
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    &pci_grackle_config_writel,
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    &pci_grackle_config_writel,
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    &pci_grackle_config_writel,
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};
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static CPUReadMemoryFunc * const pci_grackle_config_read[] = {
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    &pci_grackle_config_readl,
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    &pci_grackle_config_readl,
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    &pci_grackle_config_readl,
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};
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85 46
/* Don't know if this matches real hardware, but it agrees with OHW.  */
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static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
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{
......
147 108

  
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    s = FROM_SYSBUS(GrackleState, dev);
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    pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
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                                            pci_grackle_config_write, s);
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    pci_mem_config = pci_host_config_register_io_memory(&s->host_state);
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    pci_mem_data = pci_host_data_register_io_memory(&s->host_state);
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    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
......
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    s = FROM_SYSBUS(GrackleState, dev);
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    pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
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                                            pci_grackle_config_write, s);
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    pci_mem_config = pci_host_config_register_io_memory(&s->host_state);
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    pci_mem_data = pci_host_data_register_io_memory(&s->host_state);
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    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

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