Revision a4625612 target-sh4/translate.c
b/target-sh4/translate.c | ||
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283 | 283 |
gen_jump(ctx); |
284 | 284 |
} |
285 | 285 |
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286 |
static inline void gen_set_t(void) |
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287 |
{ |
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288 |
tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); |
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289 |
} |
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290 |
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291 |
static inline void gen_clr_t(void) |
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292 |
{ |
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293 |
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
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294 |
} |
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295 |
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296 |
static inline void gen_cmp(int cond, TCGv t0, TCGv t1) |
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297 |
{ |
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298 |
int label1 = gen_new_label(); |
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299 |
int label2 = gen_new_label(); |
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300 |
tcg_gen_brcond_i32(cond, t1, t0, label1); |
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301 |
gen_clr_t(); |
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302 |
tcg_gen_br(label2); |
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303 |
gen_set_label(label1); |
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304 |
gen_set_t(); |
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305 |
gen_set_label(label2); |
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306 |
} |
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307 |
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308 |
static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm) |
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309 |
{ |
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310 |
int label1 = gen_new_label(); |
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311 |
int label2 = gen_new_label(); |
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312 |
tcg_gen_brcondi_i32(cond, t0, imm, label1); |
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313 |
gen_clr_t(); |
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314 |
tcg_gen_br(label2); |
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315 |
gen_set_label(label1); |
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316 |
gen_set_t(); |
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317 |
gen_set_label(label2); |
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318 |
} |
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319 |
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286 | 320 |
#define B3_0 (ctx->opcode & 0xf) |
287 | 321 |
#define B6_4 ((ctx->opcode >> 4) & 0x7) |
288 | 322 |
#define B7_4 ((ctx->opcode >> 4) & 0xf) |
... | ... | |
331 | 365 |
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S); |
332 | 366 |
return; |
333 | 367 |
case 0x0008: /* clrt */ |
334 |
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
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368 |
gen_clr_t();
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335 | 369 |
return; |
336 | 370 |
case 0x0038: /* ldtlb */ |
337 | 371 |
#if defined(CONFIG_USER_ONLY) |
... | ... | |
349 | 383 |
tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S); |
350 | 384 |
return; |
351 | 385 |
case 0x0018: /* sett */ |
352 |
tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
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386 |
gen_set_t();
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353 | 387 |
return; |
354 | 388 |
case 0xfbfd: /* frchg */ |
355 | 389 |
gen_op_frchg(); |
... | ... | |
582 | 616 |
case 0x3000: /* cmp/eq Rm,Rn */ |
583 | 617 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
584 | 618 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
585 |
gen_op_cmp_eq_T0_T1();
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619 |
gen_cmp(TCG_COND_EQ, cpu_T[0], cpu_T[1]);
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586 | 620 |
return; |
587 | 621 |
case 0x3003: /* cmp/ge Rm,Rn */ |
588 | 622 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
589 | 623 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
590 |
gen_op_cmp_ge_T0_T1();
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624 |
gen_cmp(TCG_COND_GE, cpu_T[0], cpu_T[1]);
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591 | 625 |
return; |
592 | 626 |
case 0x3007: /* cmp/gt Rm,Rn */ |
593 | 627 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
594 | 628 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
595 |
gen_op_cmp_gt_T0_T1();
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629 |
gen_cmp(TCG_COND_GT, cpu_T[0], cpu_T[1]);
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596 | 630 |
return; |
597 | 631 |
case 0x3006: /* cmp/hi Rm,Rn */ |
598 | 632 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
599 | 633 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
600 |
gen_op_cmp_hi_T0_T1();
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634 |
gen_cmp(TCG_COND_GTU, cpu_T[0], cpu_T[1]);
|
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601 | 635 |
return; |
602 | 636 |
case 0x3002: /* cmp/hs Rm,Rn */ |
603 | 637 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
604 | 638 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
605 |
gen_op_cmp_hs_T0_T1();
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639 |
gen_cmp(TCG_COND_GEU, cpu_T[0], cpu_T[1]);
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606 | 640 |
return; |
607 | 641 |
case 0x200c: /* cmp/str Rm,Rn */ |
608 | 642 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
... | ... | |
737 | 771 |
case 0x2008: /* tst Rm,Rn */ |
738 | 772 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
739 | 773 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
740 |
gen_op_tst_T0_T1(); |
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774 |
tcg_gen_and_i32(cpu_T[0], cpu_T[0], cpu_T[1]); |
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775 |
gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0); |
|
741 | 776 |
return; |
742 | 777 |
case 0x200a: /* xor Rm,Rn */ |
743 | 778 |
tcg_gen_xor_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
... | ... | |
911 | 946 |
return; |
912 | 947 |
case 0x8800: /* cmp/eq #imm,R0 */ |
913 | 948 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
914 |
gen_op_cmp_eq_imm_T0(B7_0s);
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949 |
gen_cmp_imm(TCG_COND_EQ, cpu_T[0], B7_0s);
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|
915 | 950 |
return; |
916 | 951 |
case 0xc400: /* mov.b @(disp,GBR),R0 */ |
917 | 952 |
gen_op_stc_gbr_T0(); |
... | ... | |
997 | 1032 |
ctx->bstate = BS_BRANCH; |
998 | 1033 |
return; |
999 | 1034 |
case 0xc800: /* tst #imm,R0 */ |
1000 |
gen_op_tst_imm_rN(B7_0, REG(0)); |
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1035 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(0)], B7_0); |
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1036 |
gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0); |
|
1001 | 1037 |
return; |
1002 | 1038 |
case 0xcc00: /* tst.b #imm,@(R0,GBR) */ |
1003 | 1039 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
1004 | 1040 |
tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr); |
1005 | 1041 |
gen_op_ldub_T0_T0(ctx); |
1006 |
gen_op_tst_imm_T0(B7_0); |
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1042 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], B7_0); |
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1043 |
gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0); |
|
1007 | 1044 |
return; |
1008 | 1045 |
case 0xca00: /* xor #imm,R0 */ |
1009 | 1046 |
tcg_gen_xori_i32(cpu_gregs[REG(0)], cpu_gregs[REG(0)], B7_0); |
... | ... | |
1058 | 1095 |
return; |
1059 | 1096 |
case 0x4015: /* cmp/pl Rn */ |
1060 | 1097 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
1061 |
gen_op_cmp_pl_T0();
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1098 |
gen_cmp_imm(TCG_COND_GT, cpu_T[0], 0);
|
|
1062 | 1099 |
return; |
1063 | 1100 |
case 0x4011: /* cmp/pz Rn */ |
1064 | 1101 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
1065 |
gen_op_cmp_pz_T0();
|
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1102 |
gen_cmp_imm(TCG_COND_GE, cpu_T[0], 0);
|
|
1066 | 1103 |
return; |
1067 | 1104 |
case 0x4010: /* dt Rn */ |
1068 |
gen_op_dt_rN(REG(B11_8)); |
|
1105 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
|
1106 |
gen_cmp_imm(TCG_COND_EQ, cpu_gregs[REG(B11_8)], 0); |
|
1069 | 1107 |
return; |
1070 | 1108 |
case 0x402b: /* jmp @Rn */ |
1071 | 1109 |
CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
... | ... | |
1187 | 1225 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); |
1188 | 1226 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
1189 | 1227 |
gen_op_ldub_T0_T0(ctx); |
1190 |
gen_op_cmp_eq_imm_T0(0);
|
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1228 |
gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0);
|
|
1191 | 1229 |
tcg_gen_ori_i32(cpu_T[0], cpu_T[0], 0x80); |
1192 | 1230 |
gen_op_stb_T0_T1(ctx); |
1193 | 1231 |
return; |
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