Revision a4a771c0 hw/ide.c
b/hw/ide.c | ||
---|---|---|
3414 | 3414 |
} |
3415 | 3415 |
|
3416 | 3416 |
/***********************************************************/ |
3417 |
/* MMIO based ide port |
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3418 |
* This emulates IDE device connected directly to the CPU bus without |
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3419 |
* dedicated ide controller, which is often seen on embedded boards. |
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*/ |
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|
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typedef struct { |
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void *dev; |
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int shift; |
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} MMIOState; |
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|
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static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr) |
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{ |
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MMIOState *s = (MMIOState*)opaque; |
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IDEState *ide = (IDEState*)s->dev; |
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addr >>= s->shift; |
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if (addr & 7) |
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return ide_ioport_read(ide, addr); |
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else |
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return ide_data_readw(ide, 0); |
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} |
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3437 |
|
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static void mmio_ide_write (void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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MMIOState *s = (MMIOState*)opaque; |
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IDEState *ide = (IDEState*)s->dev; |
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addr >>= s->shift; |
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if (addr & 7) |
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ide_ioport_write(ide, addr, val); |
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else |
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3447 |
ide_data_writew(ide, 0, val); |
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} |
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|
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static CPUReadMemoryFunc *mmio_ide_reads[] = { |
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mmio_ide_read, |
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mmio_ide_read, |
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mmio_ide_read, |
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}; |
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|
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static CPUWriteMemoryFunc *mmio_ide_writes[] = { |
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mmio_ide_write, |
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mmio_ide_write, |
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mmio_ide_write, |
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}; |
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3461 |
|
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static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr) |
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3463 |
{ |
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MMIOState *s= (MMIOState*)opaque; |
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3465 |
IDEState *ide = (IDEState*)s->dev; |
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return ide_status_read(ide, 0); |
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} |
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|
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static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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3472 |
MMIOState *s = (MMIOState*)opaque; |
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IDEState *ide = (IDEState*)s->dev; |
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ide_cmd_write(ide, 0, val); |
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} |
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|
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static CPUReadMemoryFunc *mmio_ide_status[] = { |
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3478 |
mmio_ide_status_read, |
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mmio_ide_status_read, |
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mmio_ide_status_read, |
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}; |
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|
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static CPUWriteMemoryFunc *mmio_ide_cmd[] = { |
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mmio_ide_cmd_write, |
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mmio_ide_cmd_write, |
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mmio_ide_cmd_write, |
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}; |
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|
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void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, |
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3490 |
qemu_irq irq, int shift, |
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3491 |
BlockDriverState *hd0, BlockDriverState *hd1) |
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{ |
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MMIOState *s = qemu_mallocz(sizeof(MMIOState)); |
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IDEState *ide = qemu_mallocz(sizeof(IDEState) * 2); |
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int mem1, mem2; |
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|
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ide_init2(ide, hd0, hd1, irq); |
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|
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s->dev = ide; |
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s->shift = shift; |
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|
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mem1 = cpu_register_io_memory(0, mmio_ide_reads, mmio_ide_writes, s); |
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mem2 = cpu_register_io_memory(0, mmio_ide_status, mmio_ide_cmd, s); |
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3504 |
cpu_register_physical_memory(membase, 16 << shift, mem1); |
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3505 |
cpu_register_physical_memory(membase2, 2 << shift, mem2); |
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3506 |
} |
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3507 |
|
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3508 |
/***********************************************************/ |
|
3417 | 3509 |
/* CF-ATA Microdrive */ |
3418 | 3510 |
|
3419 | 3511 |
#define METADATA_SIZE 0x20 |
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