Revision a4bc3afc hw/mips_malta.c
| b/hw/mips_malta.c | ||
|---|---|---|
| 55 | 55 |
uint32_t i2csel; |
| 56 | 56 |
CharDriverState *display; |
| 57 | 57 |
char display_text[9]; |
| 58 |
SerialState *uart; |
|
| 58 | 59 |
} MaltaFPGAState; |
| 59 | 60 |
|
| 60 | 61 |
static PITState *pit; |
| ... | ... | |
| 241 | 242 |
val = s->brk; |
| 242 | 243 |
break; |
| 243 | 244 |
|
| 245 |
/* UART Registers */ |
|
| 246 |
case 0x00900: |
|
| 247 |
case 0x00904: |
|
| 248 |
case 0x00908: |
|
| 249 |
case 0x0090c: |
|
| 250 |
case 0x00910: |
|
| 251 |
case 0x00914: |
|
| 252 |
case 0x00918: |
|
| 253 |
case 0x0091c: |
|
| 254 |
val = serial_mm_readl(s->uart, addr); |
|
| 255 |
break; |
|
| 256 |
|
|
| 244 | 257 |
/* GPOUT Register */ |
| 245 | 258 |
case 0x00a00: |
| 246 | 259 |
val = s->gpout; |
| ... | ... | |
| 341 | 354 |
s->brk = val & 0xff; |
| 342 | 355 |
break; |
| 343 | 356 |
|
| 357 |
/* UART Registers */ |
|
| 358 |
case 0x00900: |
|
| 359 |
case 0x00904: |
|
| 360 |
case 0x00908: |
|
| 361 |
case 0x0090c: |
|
| 362 |
case 0x00910: |
|
| 363 |
case 0x00914: |
|
| 364 |
case 0x00918: |
|
| 365 |
case 0x0091c: |
|
| 366 |
serial_mm_writel(s->uart, addr, val); |
|
| 367 |
break; |
|
| 368 |
|
|
| 344 | 369 |
/* GPOUT Register */ |
| 345 | 370 |
case 0x00a00: |
| 346 | 371 |
s->gpout = val & 0xff; |
| ... | ... | |
| 400 | 425 |
malta_fpga_update_display(s); |
| 401 | 426 |
} |
| 402 | 427 |
|
| 403 |
MaltaFPGAState *malta_fpga_init(target_phys_addr_t base) |
|
| 428 |
MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
|
|
| 404 | 429 |
{
|
| 405 | 430 |
MaltaFPGAState *s; |
| 431 |
CharDriverState *uart_chr; |
|
| 406 | 432 |
int malta; |
| 407 | 433 |
|
| 408 | 434 |
s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState)); |
| 409 | 435 |
|
| 410 | 436 |
malta = cpu_register_io_memory(0, malta_fpga_read, |
| 411 | 437 |
malta_fpga_write, s); |
| 438 |
|
|
| 412 | 439 |
cpu_register_physical_memory(base, 0x100000, malta); |
| 413 | 440 |
|
| 414 | 441 |
s->display = qemu_chr_open("vc");
|
| ... | ... | |
| 422 | 449 |
qemu_chr_printf(s->display, "+ +\r\n"); |
| 423 | 450 |
qemu_chr_printf(s->display, "+--------+\r\n"); |
| 424 | 451 |
|
| 452 |
uart_chr = qemu_chr_open("vc");
|
|
| 453 |
qemu_chr_printf(uart_chr, "CBUS UART\r\n"); |
|
| 454 |
s->uart = serial_mm_init(&cpu_mips_irq_request, env, base, 3, 2, |
|
| 455 |
uart_chr, 0); |
|
| 456 |
|
|
| 425 | 457 |
malta_fpga_reset(s); |
| 426 | 458 |
qemu_register_reset(malta_fpga_reset, s); |
| 427 | 459 |
|
| ... | ... | |
| 683 | 715 |
cpu_mips_irqctrl_init(); |
| 684 | 716 |
|
| 685 | 717 |
/* FPGA */ |
| 686 |
malta_fpga = malta_fpga_init(0x1f000000LL); |
|
| 718 |
malta_fpga = malta_fpga_init(0x1f000000LL, env);
|
|
| 687 | 719 |
|
| 688 | 720 |
/* Interrupt controller */ |
| 689 | 721 |
isa_pic = pic_init(pic_irq_request, env); |
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