Revision a4bc3afc hw/serial.c
| b/hw/serial.c | ||
|---|---|---|
| 371 | 371 |
} |
| 372 | 372 |
|
| 373 | 373 |
/* Memory mapped interface */ |
| 374 |
static uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
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uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr) |
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| 375 | 375 |
{
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| 376 | 376 |
SerialState *s = opaque; |
| 377 | 377 |
|
| 378 | 378 |
return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF; |
| 379 | 379 |
} |
| 380 | 380 |
|
| 381 |
static void serial_mm_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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void serial_mm_writeb (void *opaque, |
|
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target_phys_addr_t addr, uint32_t value) |
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| 383 | 383 |
{
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| 384 | 384 |
SerialState *s = opaque; |
| 385 | 385 |
|
| 386 | 386 |
serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF); |
| 387 | 387 |
} |
| 388 | 388 |
|
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static uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
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uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr) |
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| 390 | 390 |
{
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| 391 | 391 |
SerialState *s = opaque; |
| 392 | 392 |
|
| 393 | 393 |
return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF; |
| 394 | 394 |
} |
| 395 | 395 |
|
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static void serial_mm_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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void serial_mm_writew (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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| 398 | 398 |
{
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| 399 | 399 |
SerialState *s = opaque; |
| 400 | 400 |
|
| 401 | 401 |
serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF); |
| 402 | 402 |
} |
| 403 | 403 |
|
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static uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
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uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr) |
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| 405 | 405 |
{
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| 406 | 406 |
SerialState *s = opaque; |
| 407 | 407 |
|
| 408 | 408 |
return serial_ioport_read(s, (addr - s->base) >> s->it_shift); |
| 409 | 409 |
} |
| 410 | 410 |
|
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static void serial_mm_writel (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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void serial_mm_writel (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{
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| 414 | 414 |
SerialState *s = opaque; |
| 415 | 415 |
|
| ... | ... | |
| 430 | 430 |
|
| 431 | 431 |
SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque, |
| 432 | 432 |
target_ulong base, int it_shift, |
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int irq, CharDriverState *chr) |
|
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int irq, CharDriverState *chr, |
|
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int ioregister) |
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| 434 | 435 |
{
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| 435 | 436 |
SerialState *s; |
| 436 | 437 |
int s_io_memory; |
| ... | ... | |
| 449 | 450 |
|
| 450 | 451 |
register_savevm("serial", base, 2, serial_save, serial_load, s);
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| 451 | 452 |
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s_io_memory = cpu_register_io_memory(0, serial_mm_read, |
|
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serial_mm_write, s); |
|
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cpu_register_physical_memory(base, 8 << it_shift, s_io_memory); |
|
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if (ioregister) {
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s_io_memory = cpu_register_io_memory(0, serial_mm_read, |
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serial_mm_write, s); |
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cpu_register_physical_memory(base, 8 << it_shift, s_io_memory); |
|
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} |
|
| 455 | 458 |
s->chr = chr; |
| 456 | 459 |
qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1, |
| 457 | 460 |
serial_event, s); |
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