Archipelago » qemu

#include "config.h"

#include <inttypes.h>

#if defined (TARGET_PPC64)

/* PowerPC 64 definitions */

typedef uint64_t ppc_gpr_t;

/* Machine state register bits definition                                    */

#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */

#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */

#define MSR_CM   31 /* Computation mode for BookE                     hflags */

#define MSR_ICM  30 /* Interrupt computation mode for BookE                  */

#define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */

#define MSR_VR   25 /* altivec available                            x hflags */

#define MSR_SPE  25 /* SPE enable for BookE                         x hflags */

#define msr_sf   ((env->msr >> MSR_SF)   & 1)

#define msr_isf  ((env->msr >> MSR_ISF)  & 1)

#define msr_cm   ((env->msr >> MSR_CM)   & 1)

#define msr_icm  ((env->msr >> MSR_ICM)  & 1)

#define msr_ucle ((env->msr >> MSR_UCLE) & 1)

#define msr_vr   ((env->msr >> MSR_VR)   & 1)

#define msr_spe  ((env->msr >> MSR_SE)   & 1)

#define msr_pmm  ((env->msr >> MSR_PMM)  & 1)

#define msr_ri   ((env->msr >> MSR_RI)   & 1)

#define msr_le   ((env->msr >> MSR_LE)   & 1)

enum {

    POWERPC_FLAG_NONE = 0x00000000,

    /* Flag for MSR bit 9 signification (BE/DE)                              */

    POWERPC_FLAG_BE   = 0x00000080,

    POWERPC_FLAG_DE   = 0x00000100,

    POWERPC_FLAG_PX   = 0x00000200,

    POWERPC_FLAG_PMM  = 0x00000400,

};

/* GDBstub can read and write MSR... */

void ppc_store_msr (CPUPPCState *env, target_ulong value)

{

}

/*****************************************************************************/

{

    target_ulong msr, new_msr, vector;

    int srr0, srr1, asrr0, asrr1;

    if (0) {

        /* XXX: find a suitable condition to enable the hypervisor mode */

        }

        new_msr &= ~((target_ulong)1 << MSR_RI);

        new_msr &= ~((target_ulong)1 << MSR_ME);

        if (0) {

            /* XXX: find a suitable condition to enable the hypervisor mode */

        }

        /* XXX: should also have something loaded in DAR / DSISR */

        switch (excp_model) {

        case POWERPC_EXCP_40x:

        }

#endif

        new_msr &= ~((target_ulong)1 << MSR_RI);

        if (lpes1 == 0)

        goto store_next;

    case POWERPC_EXCP_ISI:       /* Instruction storage exception            */

#if defined (DEBUG_EXCEPTIONS)

        }

#endif

        new_msr &= ~((target_ulong)1 << MSR_RI);

        if (lpes1 == 0)

        msr |= env->error_code;

        goto store_next;

    case POWERPC_EXCP_EXTERNAL:  /* External input                           */

        new_msr &= ~((target_ulong)1 << MSR_RI);

        if (lpes0 == 1)

        goto store_next;

    case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */

        new_msr &= ~((target_ulong)1 << MSR_RI);

        if (lpes1 == 0)

        /* XXX: this is false */

        /* Get rS/rD and rA from faulting opcode */

        env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;

                return;

            }

            new_msr &= ~((target_ulong)1 << MSR_RI);

            if (lpes1 == 0)

            msr |= 0x00100000;

            if (msr_fe0 == msr_fe1)

                goto store_next;

            }

#endif

            new_msr &= ~((target_ulong)1 << MSR_RI);

            if (lpes1 == 0)

            msr |= 0x00080000;

            break;

        case POWERPC_EXCP_PRIV:

            new_msr &= ~((target_ulong)1 << MSR_RI);

            if (lpes1 == 0)

            msr |= 0x00040000;

            break;

        case POWERPC_EXCP_TRAP:

            new_msr &= ~((target_ulong)1 << MSR_RI);

            if (lpes1 == 0)

            msr |= 0x00020000;

            break;

        default:

        goto store_current;

    case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */

        new_msr &= ~((target_ulong)1 << MSR_RI);

        if (lpes1 == 0)

        goto store_current;

    case POWERPC_EXCP_SYSCALL:   /* System call exception                    */

        /* NOTE: this is a temporary hack to support graphics OSI

            dump_syscall(env);

        }

        new_msr &= ~((target_ulong)1 << MSR_RI);

        lev = env->error_code;

        if (lev == 1 || (lpes0 == 0 && lpes1 == 0))

        goto store_next;

    case POWERPC_EXCP_APU:       /* Auxiliary processor unavailable          */

        new_msr &= ~((target_ulong)1 << MSR_RI);

        goto store_current;

    case POWERPC_EXCP_DECR:      /* Decrementer exception                    */

        new_msr &= ~((target_ulong)1 << MSR_RI);

        if (lpes1 == 0)

        goto store_next;

    case POWERPC_EXCP_FIT:       /* Fixed-interval timer interrupt           */

        /* FIT on 4xx */

        goto store_next;

    case POWERPC_EXCP_RESET:     /* System reset exception                   */

        new_msr &= ~((target_ulong)1 << MSR_RI);

        goto store_next;

    case POWERPC_EXCP_DSEG:      /* Data segment exception                   */

        new_msr &= ~((target_ulong)1 << MSR_RI);

        if (lpes1 == 0)

        goto store_next;

    case POWERPC_EXCP_ISEG:      /* Instruction segment exception            */

        new_msr &= ~((target_ulong)1 << MSR_RI);

        if (lpes1 == 0)

        goto store_next;

    case POWERPC_EXCP_HDECR:     /* Hypervisor decrementer exception         */

        srr0 = SPR_HSRR0;

        srr1 = SPR_HSRR1;

        goto store_next;

    case POWERPC_EXCP_TRACE:     /* Trace exception                          */

        new_msr &= ~((target_ulong)1 << MSR_RI);

        if (lpes1 == 0)

        goto store_next;

    case POWERPC_EXCP_HDSI:      /* Hypervisor data storage exception        */

        srr0 = SPR_HSRR0;

        srr1 = SPR_HSRR1;

        goto store_next;

    case POWERPC_EXCP_HISI:      /* Hypervisor instruction storage exception */

        srr0 = SPR_HSRR0;

        srr1 = SPR_HSRR1;

        goto store_next;

    case POWERPC_EXCP_HDSEG:     /* Hypervisor data segment exception        */

        srr0 = SPR_HSRR0;

        srr1 = SPR_HSRR1;

        goto store_next;

    case POWERPC_EXCP_HISEG:     /* Hypervisor instruction segment exception */

        srr0 = SPR_HSRR0;

        srr1 = SPR_HSRR1;

        goto store_next;

    case POWERPC_EXCP_VPU:       /* Vector unavailable exception             */

        new_msr &= ~((target_ulong)1 << MSR_RI);

        if (lpes1 == 0)

        goto store_current;

    case POWERPC_EXCP_PIT:       /* Programmable interval timer interrupt    */

#if defined (DEBUG_EXCEPTIONS)

        goto store_next;

    case POWERPC_EXCP_IFTLB:     /* Instruction fetch TLB error              */

        new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */

        switch (excp_model) {

        case POWERPC_EXCP_602:

        case POWERPC_EXCP_603:

        break;

    case POWERPC_EXCP_DLTLB:     /* Data load TLB miss                       */

        new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */

        switch (excp_model) {

        case POWERPC_EXCP_602:

        case POWERPC_EXCP_603:

        break;

    case POWERPC_EXCP_DSTLB:     /* Data store TLB miss                      */

        new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */

        switch (excp_model) {

        case POWERPC_EXCP_602:

        case POWERPC_EXCP_603:

        goto store_next;

    case POWERPC_EXCP_PERFM:     /* Embedded performance monitor interrupt   */

        new_msr &= ~((target_ulong)1 << MSR_RI);

        if (lpes1 == 0)

        /* XXX: TODO */

        cpu_abort(env,

                  "Performance counter exception is not implemented yet !\n");

    /* XXX: we don't use hreg_store_msr here as already have treated

     *      any special case that could occur. Just store MSR and update hflags

     */

    hreg_compute_hflags(env);

    env->nip = vector;

    /* Reset exception state */

void ppc_hw_interrupt (CPUPPCState *env)

{

    int hdice;

#if 0

    if (loglevel & CPU_LOG_INT) {

        return;

    }

#endif

    if (0) {

        /* XXX: find a suitable condition to enable the hypervisor mode */

        hdice = env->spr[SPR_LPCR] & 1;

            return;

        }

    }

    if (msr_ce != 0) {

        /* External critical interrupt */

        if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {

    env = opaque;

    msr = (target_ulong)0;

    msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */

    msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */

    msr |= (target_ulong)1 << MSR_EP;

static always_inline void hreg_compute_mem_idx (CPUPPCState *env)

{

    /* Precompute MMU index */

        env->mmu_idx = 2;

        env->mmu_idx = 1 - msr_pr;

}

static always_inline void hreg_compute_hflags (CPUPPCState *env)

    hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |

        (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |

        (1 << MSR_LE);

    hreg_compute_mem_idx(env);

    env->hflags = env->msr & hflags_mask;

    /* Merge with hflags coming from other registers */

    env->hflags |= env->hflags_nmsr;

}

{

    int excp;

    excp = 0;

    value &= env->msr_mask;

#if !defined (CONFIG_USER_ONLY)

    if (((value >> MSR_IR) & 1) != msr_ir ||

        ((value >> MSR_DR) & 1) != msr_dr) {

        /* Flush all tlb when changing translation mode */

void do_store_msr (void)

{

    if (T0 != 0) {

        env->interrupt_request |= CPU_INTERRUPT_EXITTB;

        do_raise_exception(T0);

#endif

    /* XXX: beware: this is false if VLE is supported */

    env->nip = nip & ~((target_ulong)0x00000003);

#if defined (DEBUG_OP)

    cpu_dump_rfi(env->nip, env->msr);

#endif