Revision a541f297 monitor.c
b/monitor.c | ||
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530 | 530 |
int (*get_value)(struct MonitorDef *md); |
531 | 531 |
} MonitorDef; |
532 | 532 |
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#if defined(TARGET_PPC) |
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static int monitor_get_ccr (struct MonitorDef *md) |
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{ |
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unsigned int u; |
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int i; |
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u = 0; |
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for (i = 0; i < 8; i++) |
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u |= cpu_single_env->crf[i] << (32 - (4 * i)); |
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return u; |
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} |
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static int monitor_get_msr (struct MonitorDef *md) |
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{ |
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return (cpu_single_env->msr[MSR_POW] << MSR_POW) | |
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(cpu_single_env->msr[MSR_ILE] << MSR_ILE) | |
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(cpu_single_env->msr[MSR_EE] << MSR_EE) | |
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(cpu_single_env->msr[MSR_PR] << MSR_PR) | |
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(cpu_single_env->msr[MSR_FP] << MSR_FP) | |
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(cpu_single_env->msr[MSR_ME] << MSR_ME) | |
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(cpu_single_env->msr[MSR_FE0] << MSR_FE0) | |
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(cpu_single_env->msr[MSR_SE] << MSR_SE) | |
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(cpu_single_env->msr[MSR_BE] << MSR_BE) | |
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(cpu_single_env->msr[MSR_FE1] << MSR_FE1) | |
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(cpu_single_env->msr[MSR_IP] << MSR_IP) | |
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(cpu_single_env->msr[MSR_IR] << MSR_IR) | |
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(cpu_single_env->msr[MSR_DR] << MSR_DR) | |
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(cpu_single_env->msr[MSR_RI] << MSR_RI) | |
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(cpu_single_env->msr[MSR_LE] << MSR_LE); |
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} |
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|
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static int monitor_get_xer (struct MonitorDef *md) |
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{ |
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return (cpu_single_env->xer[XER_SO] << XER_SO) | |
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(cpu_single_env->xer[XER_OV] << XER_OV) | |
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(cpu_single_env->xer[XER_CA] << XER_CA) | |
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(cpu_single_env->xer[XER_BC] << XER_BC); |
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} |
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#endif |
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|
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533 | 574 |
static MonitorDef monitor_defs[] = { |
534 | 575 |
#ifdef TARGET_I386 |
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{ "eax", offsetof(CPUState, regs[0]) }, |
... | ... | |
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{ "esi", offsetof(CPUState, regs[7]) }, |
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{ "eflags", offsetof(CPUState, eflags) }, |
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{ "eip|pc", offsetof(CPUState, eip) }, |
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#elif defined(TARGET_PPC) |
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{ "r0", offsetof(CPUState, gpr[0]) }, |
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{ "r1", offsetof(CPUState, gpr[1]) }, |
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{ "r2", offsetof(CPUState, gpr[2]) }, |
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{ "r3", offsetof(CPUState, gpr[3]) }, |
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{ "r4", offsetof(CPUState, gpr[4]) }, |
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{ "r5", offsetof(CPUState, gpr[5]) }, |
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{ "r6", offsetof(CPUState, gpr[6]) }, |
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{ "r7", offsetof(CPUState, gpr[7]) }, |
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{ "r8", offsetof(CPUState, gpr[8]) }, |
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{ "r9", offsetof(CPUState, gpr[9]) }, |
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{ "r10", offsetof(CPUState, gpr[10]) }, |
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{ "r11", offsetof(CPUState, gpr[11]) }, |
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{ "r12", offsetof(CPUState, gpr[12]) }, |
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{ "r13", offsetof(CPUState, gpr[13]) }, |
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{ "r14", offsetof(CPUState, gpr[14]) }, |
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{ "r15", offsetof(CPUState, gpr[15]) }, |
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{ "r16", offsetof(CPUState, gpr[16]) }, |
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{ "r17", offsetof(CPUState, gpr[17]) }, |
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{ "r18", offsetof(CPUState, gpr[18]) }, |
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{ "r19", offsetof(CPUState, gpr[19]) }, |
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{ "r20", offsetof(CPUState, gpr[20]) }, |
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{ "r21", offsetof(CPUState, gpr[21]) }, |
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{ "r22", offsetof(CPUState, gpr[22]) }, |
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{ "r23", offsetof(CPUState, gpr[23]) }, |
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{ "r24", offsetof(CPUState, gpr[24]) }, |
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{ "r25", offsetof(CPUState, gpr[25]) }, |
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{ "r26", offsetof(CPUState, gpr[26]) }, |
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{ "r27", offsetof(CPUState, gpr[27]) }, |
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{ "r28", offsetof(CPUState, gpr[28]) }, |
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{ "r29", offsetof(CPUState, gpr[29]) }, |
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{ "r30", offsetof(CPUState, gpr[30]) }, |
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{ "r31", offsetof(CPUState, gpr[31]) }, |
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{ "lr", offsetof(CPUState, lr) }, |
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{ "ctr", offsetof(CPUState, ctr) }, |
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{ "decr", offsetof(CPUState, decr) }, |
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{ "ccr", 0, &monitor_get_ccr, }, |
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{ "msr", 0, &monitor_get_msr, }, |
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{ "xer", 0, &monitor_get_xer, }, |
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{ "tbu", offsetof(CPUState, tb[0]) }, |
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{ "tbl", offsetof(CPUState, tb[1]) }, |
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{ "sdr1", offsetof(CPUState, sdr1) }, |
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{ "sr0", offsetof(CPUState, sr[0]) }, |
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{ "sr1", offsetof(CPUState, sr[1]) }, |
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{ "sr2", offsetof(CPUState, sr[2]) }, |
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{ "sr3", offsetof(CPUState, sr[3]) }, |
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{ "sr4", offsetof(CPUState, sr[4]) }, |
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{ "sr5", offsetof(CPUState, sr[5]) }, |
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{ "sr6", offsetof(CPUState, sr[6]) }, |
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{ "sr7", offsetof(CPUState, sr[7]) }, |
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{ "sr8", offsetof(CPUState, sr[8]) }, |
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{ "sr9", offsetof(CPUState, sr[9]) }, |
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{ "sr10", offsetof(CPUState, sr[10]) }, |
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{ "sr11", offsetof(CPUState, sr[11]) }, |
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{ "sr12", offsetof(CPUState, sr[12]) }, |
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{ "sr13", offsetof(CPUState, sr[13]) }, |
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{ "sr14", offsetof(CPUState, sr[14]) }, |
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{ "sr15", offsetof(CPUState, sr[15]) }, |
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/* Too lazy to put BATs and SPRs ... */ |
|
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#endif |
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{ NULL }, |
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}; |
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