Revision a5a52cf2 target-sparc/op_helper.c
| b/target-sparc/op_helper.c | ||
|---|---|---|
| 1649 | 1649 |
} |
| 1650 | 1650 |
case 0x51: // I-MMU 8k TSB pointer |
| 1651 | 1651 |
case 0x52: // I-MMU 64k TSB pointer |
| 1652 |
case 0x55: // I-MMU data access |
|
| 1653 | 1652 |
// XXX |
| 1654 | 1653 |
break; |
| 1654 |
case 0x55: // I-MMU data access |
|
| 1655 |
{
|
|
| 1656 |
int reg = (addr >> 3) & 0x3f; |
|
| 1657 |
|
|
| 1658 |
ret = env->itlb_tte[reg]; |
|
| 1659 |
break; |
|
| 1660 |
} |
|
| 1655 | 1661 |
case 0x56: // I-MMU tag read |
| 1656 | 1662 |
{
|
| 1657 | 1663 |
unsigned int i; |
| 1658 | 1664 |
|
| 1659 | 1665 |
for (i = 0; i < 64; i++) {
|
| 1660 | 1666 |
// Valid, ctx match, vaddr match |
| 1661 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 && |
|
| 1662 |
env->itlb_tag[i] == addr) {
|
|
| 1663 |
ret = env->itlb_tag[i]; |
|
| 1664 |
break; |
|
| 1667 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
|
|
| 1668 |
uint64_t mask; |
|
| 1669 |
|
|
| 1670 |
switch ((env->itlb_tte[i] >> 61) & 3) {
|
|
| 1671 |
default: |
|
| 1672 |
case 0x0: |
|
| 1673 |
mask = 0xffffffffffffffff; |
|
| 1674 |
break; |
|
| 1675 |
case 0x1: |
|
| 1676 |
mask = 0xffffffffffff0fff; |
|
| 1677 |
break; |
|
| 1678 |
case 0x2: |
|
| 1679 |
mask = 0xfffffffffff80fff; |
|
| 1680 |
break; |
|
| 1681 |
case 0x3: |
|
| 1682 |
mask = 0xffffffffffc00fff; |
|
| 1683 |
break; |
|
| 1684 |
} |
|
| 1685 |
if ((env->itlb_tag[i] & mask) == (addr & mask)) {
|
|
| 1686 |
ret = env->itlb_tte[i]; |
|
| 1687 |
break; |
|
| 1688 |
} |
|
| 1665 | 1689 |
} |
| 1666 | 1690 |
} |
| 1667 | 1691 |
break; |
| ... | ... | |
| 1673 | 1697 |
ret = env->dmmuregs[reg]; |
| 1674 | 1698 |
break; |
| 1675 | 1699 |
} |
| 1700 |
case 0x5d: // D-MMU data access |
|
| 1701 |
{
|
|
| 1702 |
int reg = (addr >> 3) & 0x3f; |
|
| 1703 |
|
|
| 1704 |
ret = env->dtlb_tte[reg]; |
|
| 1705 |
break; |
|
| 1706 |
} |
|
| 1676 | 1707 |
case 0x5e: // D-MMU tag read |
| 1677 | 1708 |
{
|
| 1678 | 1709 |
unsigned int i; |
| 1679 | 1710 |
|
| 1680 | 1711 |
for (i = 0; i < 64; i++) {
|
| 1681 | 1712 |
// Valid, ctx match, vaddr match |
| 1682 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 && |
|
| 1683 |
env->dtlb_tag[i] == addr) {
|
|
| 1684 |
ret = env->dtlb_tag[i]; |
|
| 1685 |
break; |
|
| 1713 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
|
|
| 1714 |
uint64_t mask; |
|
| 1715 |
|
|
| 1716 |
switch ((env->dtlb_tte[i] >> 61) & 3) {
|
|
| 1717 |
default: |
|
| 1718 |
case 0x0: |
|
| 1719 |
mask = 0xffffffffffffffff; |
|
| 1720 |
break; |
|
| 1721 |
case 0x1: |
|
| 1722 |
mask = 0xffffffffffff0fff; |
|
| 1723 |
break; |
|
| 1724 |
case 0x2: |
|
| 1725 |
mask = 0xfffffffffff80fff; |
|
| 1726 |
break; |
|
| 1727 |
case 0x3: |
|
| 1728 |
mask = 0xffffffffffc00fff; |
|
| 1729 |
break; |
|
| 1730 |
} |
|
| 1731 |
if ((env->dtlb_tag[i] & mask) == (addr & mask)) {
|
|
| 1732 |
ret = env->dtlb_tte[i]; |
|
| 1733 |
break; |
|
| 1734 |
} |
|
| 1686 | 1735 |
} |
| 1687 | 1736 |
} |
| 1688 | 1737 |
break; |
| 1689 | 1738 |
} |
| 1690 | 1739 |
case 0x46: // D-cache data |
| 1691 | 1740 |
case 0x47: // D-cache tag access |
| 1741 |
case 0x4b: // E-cache error enable |
|
| 1742 |
case 0x4c: // E-cache asynchronous fault status |
|
| 1743 |
case 0x4d: // E-cache asynchronous fault address |
|
| 1692 | 1744 |
case 0x4e: // E-cache tag data |
| 1693 | 1745 |
case 0x66: // I-cache instruction access |
| 1694 | 1746 |
case 0x67: // I-cache tag access |
| ... | ... | |
| 1700 | 1752 |
case 0x59: // D-MMU 8k TSB pointer |
| 1701 | 1753 |
case 0x5a: // D-MMU 64k TSB pointer |
| 1702 | 1754 |
case 0x5b: // D-MMU data pointer |
| 1703 |
case 0x5d: // D-MMU data access |
|
| 1704 | 1755 |
case 0x48: // Interrupt dispatch, RO |
| 1705 | 1756 |
case 0x49: // Interrupt data receive |
| 1706 | 1757 |
case 0x7f: // Incoming interrupt vector, RO |
| ... | ... | |
| 2052 | 2103 |
return; |
| 2053 | 2104 |
case 0x46: // D-cache data |
| 2054 | 2105 |
case 0x47: // D-cache tag access |
| 2106 |
case 0x4b: // E-cache error enable |
|
| 2107 |
case 0x4c: // E-cache asynchronous fault status |
|
| 2108 |
case 0x4d: // E-cache asynchronous fault address |
|
| 2055 | 2109 |
case 0x4e: // E-cache tag data |
| 2056 | 2110 |
case 0x66: // I-cache instruction access |
| 2057 | 2111 |
case 0x67: // I-cache tag access |
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