Revision a5e26afa target-ppc/translate.c
| b/target-ppc/translate.c | ||
|---|---|---|
| 50 | 50 |
#if !defined(TARGET_PPC64) |
| 51 | 51 |
+ 10*4 + 22*5 /* SPE GPRh */ |
| 52 | 52 |
#endif |
| 53 |
+ 10*4 + 22*5 /* FPR */ |
|
| 53 | 54 |
+ 2*(10*6 + 22*7) /* AVRh, AVRl */]; |
| 54 | 55 |
static TCGv cpu_gpr[32]; |
| 55 | 56 |
#if !defined(TARGET_PPC64) |
| 56 | 57 |
static TCGv cpu_gprh[32]; |
| 57 | 58 |
#endif |
| 59 |
static TCGv cpu_fpr[32]; |
|
| 58 | 60 |
static TCGv cpu_avrh[32], cpu_avrl[32]; |
| 59 | 61 |
|
| 60 | 62 |
/* dyngen register indexes */ |
| ... | ... | |
| 64 | 66 |
#else |
| 65 | 67 |
static TCGv cpu_T64[3]; |
| 66 | 68 |
#endif |
| 69 |
static TCGv cpu_FT[3]; |
|
| 67 | 70 |
static TCGv cpu_AVRh[3], cpu_AVRl[3]; |
| 68 | 71 |
|
| 69 | 72 |
#include "gen-icount.h" |
| ... | ... | |
| 101 | 104 |
TCG_AREG0, offsetof(CPUState, t2_64), |
| 102 | 105 |
"T2_64"); |
| 103 | 106 |
#endif |
| 107 |
|
|
| 108 |
cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
|
| 109 |
offsetof(CPUState, ft0), "FT0"); |
|
| 110 |
cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
|
| 111 |
offsetof(CPUState, ft1), "FT1"); |
|
| 112 |
cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
|
| 113 |
offsetof(CPUState, ft2), "FT2"); |
|
| 114 |
|
|
| 104 | 115 |
cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 105 | 116 |
offsetof(CPUState, avr0.u64[0]), "AVR0H"); |
| 106 | 117 |
cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| ... | ... | |
| 127 | 138 |
p += (i < 10) ? 4 : 5; |
| 128 | 139 |
#endif |
| 129 | 140 |
|
| 141 |
sprintf(p, "fp%d", i); |
|
| 142 |
cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
|
| 143 |
offsetof(CPUState, fpr[i]), p); |
|
| 144 |
|
|
| 130 | 145 |
sprintf(p, "avr%dH", i); |
| 131 | 146 |
cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
| 132 | 147 |
offsetof(CPUState, avr[i].u64[0]), p); |
| ... | ... | |
| 196 | 211 |
GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf); |
| 197 | 212 |
#endif |
| 198 | 213 |
|
| 199 |
/* floating point registers moves */ |
|
| 200 |
GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr); |
|
| 201 |
GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr); |
|
| 202 |
GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr); |
|
| 203 |
GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr); |
|
| 204 |
GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr); |
|
| 205 |
#if 0 // unused |
|
| 206 |
GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr); |
|
| 207 |
#endif |
|
| 208 |
|
|
| 209 | 214 |
/* internal defines */ |
| 210 | 215 |
typedef struct DisasContext {
|
| 211 | 216 |
struct TranslationBlock *tb; |
| ... | ... | |
| 1780 | 1785 |
GEN_EXCP_NO_FP(ctx); \ |
| 1781 | 1786 |
return; \ |
| 1782 | 1787 |
} \ |
| 1783 |
gen_op_load_fpr_FT0(rA(ctx->opcode)); \
|
|
| 1784 |
gen_op_load_fpr_FT1(rC(ctx->opcode)); \
|
|
| 1785 |
gen_op_load_fpr_FT2(rB(ctx->opcode)); \
|
|
| 1788 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
|
|
| 1789 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
|
|
| 1790 |
tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
|
|
| 1786 | 1791 |
gen_reset_fpstatus(); \ |
| 1787 | 1792 |
gen_op_f##op(); \ |
| 1788 | 1793 |
if (isfloat) { \
|
| 1789 | 1794 |
gen_op_frsp(); \ |
| 1790 | 1795 |
} \ |
| 1791 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
|
|
| 1796 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
| 1792 | 1797 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ |
| 1793 | 1798 |
} |
| 1794 | 1799 |
|
| ... | ... | |
| 1803 | 1808 |
GEN_EXCP_NO_FP(ctx); \ |
| 1804 | 1809 |
return; \ |
| 1805 | 1810 |
} \ |
| 1806 |
gen_op_load_fpr_FT0(rA(ctx->opcode)); \
|
|
| 1807 |
gen_op_load_fpr_FT1(rB(ctx->opcode)); \
|
|
| 1811 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
|
|
| 1812 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
|
|
| 1808 | 1813 |
gen_reset_fpstatus(); \ |
| 1809 | 1814 |
gen_op_f##op(); \ |
| 1810 | 1815 |
if (isfloat) { \
|
| 1811 | 1816 |
gen_op_frsp(); \ |
| 1812 | 1817 |
} \ |
| 1813 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
|
|
| 1818 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
| 1814 | 1819 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ |
| 1815 | 1820 |
} |
| 1816 | 1821 |
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
| ... | ... | |
| 1824 | 1829 |
GEN_EXCP_NO_FP(ctx); \ |
| 1825 | 1830 |
return; \ |
| 1826 | 1831 |
} \ |
| 1827 |
gen_op_load_fpr_FT0(rA(ctx->opcode)); \
|
|
| 1828 |
gen_op_load_fpr_FT1(rC(ctx->opcode)); \
|
|
| 1832 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
|
|
| 1833 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
|
|
| 1829 | 1834 |
gen_reset_fpstatus(); \ |
| 1830 | 1835 |
gen_op_f##op(); \ |
| 1831 | 1836 |
if (isfloat) { \
|
| 1832 | 1837 |
gen_op_frsp(); \ |
| 1833 | 1838 |
} \ |
| 1834 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
|
|
| 1839 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
| 1835 | 1840 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ |
| 1836 | 1841 |
} |
| 1837 | 1842 |
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
| ... | ... | |
| 1845 | 1850 |
GEN_EXCP_NO_FP(ctx); \ |
| 1846 | 1851 |
return; \ |
| 1847 | 1852 |
} \ |
| 1848 |
gen_op_load_fpr_FT0(rB(ctx->opcode)); \
|
|
| 1853 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
|
|
| 1849 | 1854 |
gen_reset_fpstatus(); \ |
| 1850 | 1855 |
gen_op_f##name(); \ |
| 1851 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
|
|
| 1856 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
| 1852 | 1857 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ |
| 1853 | 1858 |
} |
| 1854 | 1859 |
|
| ... | ... | |
| 1859 | 1864 |
GEN_EXCP_NO_FP(ctx); \ |
| 1860 | 1865 |
return; \ |
| 1861 | 1866 |
} \ |
| 1862 |
gen_op_load_fpr_FT0(rB(ctx->opcode)); \
|
|
| 1867 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
|
|
| 1863 | 1868 |
gen_reset_fpstatus(); \ |
| 1864 | 1869 |
gen_op_f##name(); \ |
| 1865 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
|
|
| 1870 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
| 1866 | 1871 |
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ |
| 1867 | 1872 |
} |
| 1868 | 1873 |
|
| ... | ... | |
| 1902 | 1907 |
GEN_EXCP_NO_FP(ctx); |
| 1903 | 1908 |
return; |
| 1904 | 1909 |
} |
| 1905 |
gen_op_load_fpr_FT0(rB(ctx->opcode));
|
|
| 1910 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
|
|
| 1906 | 1911 |
gen_reset_fpstatus(); |
| 1907 | 1912 |
gen_op_fsqrt(); |
| 1908 |
gen_op_store_FT0_fpr(rD(ctx->opcode));
|
|
| 1913 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
|
| 1909 | 1914 |
gen_compute_fprf(1, Rc(ctx->opcode) != 0); |
| 1910 | 1915 |
} |
| 1911 | 1916 |
|
| ... | ... | |
| 1915 | 1920 |
GEN_EXCP_NO_FP(ctx); |
| 1916 | 1921 |
return; |
| 1917 | 1922 |
} |
| 1918 |
gen_op_load_fpr_FT0(rB(ctx->opcode));
|
|
| 1923 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
|
|
| 1919 | 1924 |
gen_reset_fpstatus(); |
| 1920 | 1925 |
gen_op_fsqrt(); |
| 1921 | 1926 |
gen_op_frsp(); |
| 1922 |
gen_op_store_FT0_fpr(rD(ctx->opcode));
|
|
| 1927 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
|
| 1923 | 1928 |
gen_compute_fprf(1, Rc(ctx->opcode) != 0); |
| 1924 | 1929 |
} |
| 1925 | 1930 |
|
| ... | ... | |
| 1966 | 1971 |
GEN_EXCP_NO_FP(ctx); |
| 1967 | 1972 |
return; |
| 1968 | 1973 |
} |
| 1969 |
gen_op_load_fpr_FT0(rA(ctx->opcode));
|
|
| 1970 |
gen_op_load_fpr_FT1(rB(ctx->opcode));
|
|
| 1974 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
|
|
| 1975 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
|
|
| 1971 | 1976 |
gen_reset_fpstatus(); |
| 1972 | 1977 |
gen_op_fcmpo(); |
| 1973 | 1978 |
gen_op_store_T0_crf(crfD(ctx->opcode)); |
| ... | ... | |
| 1981 | 1986 |
GEN_EXCP_NO_FP(ctx); |
| 1982 | 1987 |
return; |
| 1983 | 1988 |
} |
| 1984 |
gen_op_load_fpr_FT0(rA(ctx->opcode));
|
|
| 1985 |
gen_op_load_fpr_FT1(rB(ctx->opcode));
|
|
| 1989 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
|
|
| 1990 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
|
|
| 1986 | 1991 |
gen_reset_fpstatus(); |
| 1987 | 1992 |
gen_op_fcmpu(); |
| 1988 | 1993 |
gen_op_store_T0_crf(crfD(ctx->opcode)); |
| ... | ... | |
| 2002 | 2007 |
GEN_EXCP_NO_FP(ctx); |
| 2003 | 2008 |
return; |
| 2004 | 2009 |
} |
| 2005 |
gen_op_load_fpr_FT0(rB(ctx->opcode));
|
|
| 2006 |
gen_op_store_FT0_fpr(rD(ctx->opcode));
|
|
| 2010 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
|
|
| 2011 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
|
| 2007 | 2012 |
gen_compute_fprf(0, Rc(ctx->opcode) != 0); |
| 2008 | 2013 |
} |
| 2009 | 2014 |
|
| ... | ... | |
| 2041 | 2046 |
gen_optimize_fprf(); |
| 2042 | 2047 |
gen_reset_fpstatus(); |
| 2043 | 2048 |
gen_op_load_fpscr_FT0(); |
| 2044 |
gen_op_store_FT0_fpr(rD(ctx->opcode));
|
|
| 2049 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
|
| 2045 | 2050 |
gen_compute_fprf(0, Rc(ctx->opcode) != 0); |
| 2046 | 2051 |
} |
| 2047 | 2052 |
|
| ... | ... | |
| 2096 | 2101 |
return; |
| 2097 | 2102 |
} |
| 2098 | 2103 |
gen_optimize_fprf(); |
| 2099 |
gen_op_load_fpr_FT0(rB(ctx->opcode));
|
|
| 2104 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
|
|
| 2100 | 2105 |
gen_reset_fpstatus(); |
| 2101 | 2106 |
gen_op_store_fpscr(FM(ctx->opcode)); |
| 2102 | 2107 |
if (unlikely(Rc(ctx->opcode) != 0)) {
|
| ... | ... | |
| 2716 | 2721 |
} \ |
| 2717 | 2722 |
gen_addr_imm_index(ctx, 0); \ |
| 2718 | 2723 |
op_ldst(l##width); \ |
| 2719 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
|
|
| 2724 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
| 2720 | 2725 |
} |
| 2721 | 2726 |
|
| 2722 | 2727 |
#define GEN_LDUF(width, opc, type) \ |
| ... | ... | |
| 2732 | 2737 |
} \ |
| 2733 | 2738 |
gen_addr_imm_index(ctx, 0); \ |
| 2734 | 2739 |
op_ldst(l##width); \ |
| 2735 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
|
|
| 2740 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
| 2736 | 2741 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ |
| 2737 | 2742 |
} |
| 2738 | 2743 |
|
| ... | ... | |
| 2749 | 2754 |
} \ |
| 2750 | 2755 |
gen_addr_reg_index(ctx); \ |
| 2751 | 2756 |
op_ldst(l##width); \ |
| 2752 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
|
|
| 2757 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
| 2753 | 2758 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ |
| 2754 | 2759 |
} |
| 2755 | 2760 |
|
| ... | ... | |
| 2762 | 2767 |
} \ |
| 2763 | 2768 |
gen_addr_reg_index(ctx); \ |
| 2764 | 2769 |
op_ldst(l##width); \ |
| 2765 |
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
|
|
| 2770 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
|
| 2766 | 2771 |
} |
| 2767 | 2772 |
|
| 2768 | 2773 |
#define GEN_LDFS(width, op, type) \ |
| ... | ... | |
| 2786 | 2791 |
return; \ |
| 2787 | 2792 |
} \ |
| 2788 | 2793 |
gen_addr_imm_index(ctx, 0); \ |
| 2789 |
gen_op_load_fpr_FT0(rS(ctx->opcode)); \
|
|
| 2794 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
|
|
| 2790 | 2795 |
op_ldst(st##width); \ |
| 2791 | 2796 |
} |
| 2792 | 2797 |
|
| ... | ... | |
| 2802 | 2807 |
return; \ |
| 2803 | 2808 |
} \ |
| 2804 | 2809 |
gen_addr_imm_index(ctx, 0); \ |
| 2805 |
gen_op_load_fpr_FT0(rS(ctx->opcode)); \
|
|
| 2810 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
|
|
| 2806 | 2811 |
op_ldst(st##width); \ |
| 2807 | 2812 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ |
| 2808 | 2813 |
} |
| ... | ... | |
| 2819 | 2824 |
return; \ |
| 2820 | 2825 |
} \ |
| 2821 | 2826 |
gen_addr_reg_index(ctx); \ |
| 2822 |
gen_op_load_fpr_FT0(rS(ctx->opcode)); \
|
|
| 2827 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
|
|
| 2823 | 2828 |
op_ldst(st##width); \ |
| 2824 | 2829 |
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ |
| 2825 | 2830 |
} |
| ... | ... | |
| 2832 | 2837 |
return; \ |
| 2833 | 2838 |
} \ |
| 2834 | 2839 |
gen_addr_reg_index(ctx); \ |
| 2835 |
gen_op_load_fpr_FT0(rS(ctx->opcode)); \
|
|
| 2840 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
|
|
| 2836 | 2841 |
op_ldst(st##width); \ |
| 2837 | 2842 |
} |
| 2838 | 2843 |
|
| ... | ... | |
| 4522 | 4527 |
gen_update_nip(ctx, ctx->nip - 4); |
| 4523 | 4528 |
gen_addr_imm_index(ctx, 0); |
| 4524 | 4529 |
op_POWER2_lfq(); |
| 4525 |
gen_op_store_FT0_fpr(rD(ctx->opcode));
|
|
| 4526 |
gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
|
|
| 4530 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
|
| 4531 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
|
|
| 4527 | 4532 |
} |
| 4528 | 4533 |
|
| 4529 | 4534 |
/* lfqu */ |
| ... | ... | |
| 4535 | 4540 |
gen_update_nip(ctx, ctx->nip - 4); |
| 4536 | 4541 |
gen_addr_imm_index(ctx, 0); |
| 4537 | 4542 |
op_POWER2_lfq(); |
| 4538 |
gen_op_store_FT0_fpr(rD(ctx->opcode));
|
|
| 4539 |
gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
|
|
| 4543 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
|
| 4544 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
|
|
| 4540 | 4545 |
if (ra != 0) |
| 4541 | 4546 |
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); |
| 4542 | 4547 |
} |
| ... | ... | |
| 4550 | 4555 |
gen_update_nip(ctx, ctx->nip - 4); |
| 4551 | 4556 |
gen_addr_reg_index(ctx); |
| 4552 | 4557 |
op_POWER2_lfq(); |
| 4553 |
gen_op_store_FT0_fpr(rD(ctx->opcode));
|
|
| 4554 |
gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
|
|
| 4558 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
|
| 4559 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
|
|
| 4555 | 4560 |
if (ra != 0) |
| 4556 | 4561 |
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); |
| 4557 | 4562 |
} |
| ... | ... | |
| 4563 | 4568 |
gen_update_nip(ctx, ctx->nip - 4); |
| 4564 | 4569 |
gen_addr_reg_index(ctx); |
| 4565 | 4570 |
op_POWER2_lfq(); |
| 4566 |
gen_op_store_FT0_fpr(rD(ctx->opcode));
|
|
| 4567 |
gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
|
|
| 4571 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
|
| 4572 |
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
|
|
| 4568 | 4573 |
} |
| 4569 | 4574 |
|
| 4570 | 4575 |
/* stfq */ |
| ... | ... | |
| 4573 | 4578 |
/* NIP cannot be restored if the memory exception comes from an helper */ |
| 4574 | 4579 |
gen_update_nip(ctx, ctx->nip - 4); |
| 4575 | 4580 |
gen_addr_imm_index(ctx, 0); |
| 4576 |
gen_op_load_fpr_FT0(rS(ctx->opcode));
|
|
| 4577 |
gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
|
|
| 4581 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
|
|
| 4582 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
|
|
| 4578 | 4583 |
op_POWER2_stfq(); |
| 4579 | 4584 |
} |
| 4580 | 4585 |
|
| ... | ... | |
| 4586 | 4591 |
/* NIP cannot be restored if the memory exception comes from an helper */ |
| 4587 | 4592 |
gen_update_nip(ctx, ctx->nip - 4); |
| 4588 | 4593 |
gen_addr_imm_index(ctx, 0); |
| 4589 |
gen_op_load_fpr_FT0(rS(ctx->opcode));
|
|
| 4590 |
gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
|
|
| 4594 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
|
|
| 4595 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
|
|
| 4591 | 4596 |
op_POWER2_stfq(); |
| 4592 | 4597 |
if (ra != 0) |
| 4593 | 4598 |
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); |
| ... | ... | |
| 4601 | 4606 |
/* NIP cannot be restored if the memory exception comes from an helper */ |
| 4602 | 4607 |
gen_update_nip(ctx, ctx->nip - 4); |
| 4603 | 4608 |
gen_addr_reg_index(ctx); |
| 4604 |
gen_op_load_fpr_FT0(rS(ctx->opcode));
|
|
| 4605 |
gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
|
|
| 4609 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
|
|
| 4610 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
|
|
| 4606 | 4611 |
op_POWER2_stfq(); |
| 4607 | 4612 |
if (ra != 0) |
| 4608 | 4613 |
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); |
| ... | ... | |
| 4614 | 4619 |
/* NIP cannot be restored if the memory exception comes from an helper */ |
| 4615 | 4620 |
gen_update_nip(ctx, ctx->nip - 4); |
| 4616 | 4621 |
gen_addr_reg_index(ctx); |
| 4617 |
gen_op_load_fpr_FT0(rS(ctx->opcode));
|
|
| 4618 |
gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
|
|
| 4622 |
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
|
|
| 4623 |
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
|
|
| 4619 | 4624 |
op_POWER2_stfq(); |
| 4620 | 4625 |
} |
| 4621 | 4626 |
|
Also available in: Unified diff