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Revision a5fce077

IDa5fce077b134a486794b77b49f4eae1d3c9b960c

Added by Isaku Yamahata over 13 years ago

pci bridge: implement secondary bus reset

Trigger secondary bus reset when secondary bus reset bit
value changes from 0 to 1.

Signed-off-by: Isaku Yamahata <>
Signed-off-by: Anthony Liguori <>
Signed-off-by: Michael S. Tsirkin <>

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