Revision a63b5829
| b/dyngen-exec.h | ||
|---|---|---|
| 50 | 50 |
|
| 51 | 51 |
#if defined(__i386__) |
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#define AREG0 "ebp" |
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#define AREG1 "ebx" |
|
| 54 |
#define AREG2 "esi" |
|
| 55 | 53 |
#elif defined(__x86_64__) |
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#define AREG0 "r14" |
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#define AREG1 "r15" |
|
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#define AREG2 "r12" |
|
| 59 | 55 |
#elif defined(_ARCH_PPC) |
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#define AREG0 "r27" |
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#define AREG1 "r24" |
|
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#define AREG2 "r25" |
|
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#elif defined(__arm__) |
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#define AREG0 "r7" |
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#define AREG1 "r4" |
|
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#define AREG2 "r5" |
|
| 67 | 59 |
#elif defined(__hppa__) |
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#define AREG0 "r17" |
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#define AREG1 "r14" |
|
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#define AREG2 "r15" |
|
| 71 | 61 |
#elif defined(__mips__) |
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#define AREG0 "fp" |
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#define AREG1 "s0" |
|
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#define AREG2 "s1" |
|
| 75 | 63 |
#elif defined(__sparc__) |
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#ifdef CONFIG_SOLARIS |
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#define AREG0 "g2" |
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#define AREG1 "g3" |
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#define AREG2 "g4" |
|
| 80 | 66 |
#else |
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#ifdef __sparc_v9__ |
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#define AREG0 "g5" |
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#define AREG1 "g6" |
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#define AREG2 "g7" |
|
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#else |
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#define AREG0 "g6" |
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#define AREG1 "g1" |
|
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#define AREG2 "g2" |
|
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#endif |
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#endif |
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#elif defined(__s390__) |
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#define AREG0 "r10" |
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#define AREG1 "r7" |
|
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#define AREG2 "r8" |
|
| 95 | 75 |
#elif defined(__alpha__) |
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/* Note $15 is the frame pointer, so anything in op-i386.c that would |
| 97 | 77 |
require a frame pointer, like alloca, would probably loose. */ |
| 98 | 78 |
#define AREG0 "$15" |
| 99 |
#define AREG1 "$9" |
|
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#define AREG2 "$10" |
|
| 101 | 79 |
#elif defined(__mc68000) |
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#define AREG0 "%a5" |
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#define AREG1 "%a4" |
|
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#define AREG2 "%d7" |
|
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#elif defined(__ia64__) |
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#define AREG0 "r7" |
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#define AREG1 "r4" |
|
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#define AREG2 "r5" |
|
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#else |
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#error unsupported CPU |
| 111 | 85 |
#endif |
| b/tcg/arm/tcg-target.h | ||
|---|---|---|
| 73 | 73 |
enum {
|
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/* Note: must be synced with dyngen-exec.h */ |
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TCG_AREG0 = TCG_REG_R7, |
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TCG_AREG1 = TCG_REG_R4, |
|
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TCG_AREG2 = TCG_REG_R5, |
|
| 78 | 76 |
}; |
| 79 | 77 |
|
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
| b/tcg/hppa/tcg-target.h | ||
|---|---|---|
| 83 | 83 |
|
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/* Note: must be synced with dyngen-exec.h */ |
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#define TCG_AREG0 TCG_REG_R17 |
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#define TCG_AREG1 TCG_REG_R14 |
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#define TCG_AREG2 TCG_REG_R15 |
|
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|
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{
|
| b/tcg/i386/tcg-target.h | ||
|---|---|---|
| 62 | 62 |
|
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/* Note: must be synced with dyngen-exec.h */ |
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#define TCG_AREG0 TCG_REG_EBP |
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#define TCG_AREG1 TCG_REG_EBX |
|
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#define TCG_AREG2 TCG_REG_ESI |
|
| 67 | 65 |
|
| 68 | 66 |
static inline void flush_icache_range(unsigned long start, unsigned long stop) |
| 69 | 67 |
{
|
| b/tcg/mips/tcg-target.h | ||
|---|---|---|
| 95 | 95 |
|
| 96 | 96 |
/* Note: must be synced with dyngen-exec.h */ |
| 97 | 97 |
#define TCG_AREG0 TCG_REG_FP |
| 98 |
#define TCG_AREG1 TCG_REG_S0 |
|
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#define TCG_AREG2 TCG_REG_S1 |
|
| 100 | 98 |
|
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#include <sys/cachectl.h> |
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|
| b/tcg/ppc/tcg-target.h | ||
|---|---|---|
| 91 | 91 |
#define TCG_TARGET_HAS_orc_i32 |
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|
| 93 | 93 |
#define TCG_AREG0 TCG_REG_R27 |
| 94 |
#define TCG_AREG1 TCG_REG_R24 |
|
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#define TCG_AREG2 TCG_REG_R25 |
|
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|
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#define TCG_TARGET_HAS_GUEST_BASE |
| b/tcg/ppc64/tcg-target.h | ||
|---|---|---|
| 98 | 98 |
/* #define TCG_TARGET_HAS_orc_i64 */ |
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|
| 100 | 100 |
#define TCG_AREG0 TCG_REG_R27 |
| 101 |
#define TCG_AREG1 TCG_REG_R24 |
|
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#define TCG_AREG2 TCG_REG_R25 |
|
| 103 | 101 |
|
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#define TCG_TARGET_HAS_GUEST_BASE |
| b/tcg/s390/tcg-target.h | ||
|---|---|---|
| 84 | 84 |
enum {
|
| 85 | 85 |
/* Note: must be synced with dyngen-exec.h */ |
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TCG_AREG0 = TCG_REG_R10, |
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TCG_AREG1 = TCG_REG_R7, |
|
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TCG_AREG2 = TCG_REG_R8, |
|
| 89 |
TCG_AREG3 = TCG_REG_R9, |
|
| 90 | 87 |
}; |
| 91 | 88 |
|
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
| b/tcg/sparc/tcg-target.h | ||
|---|---|---|
| 119 | 119 |
#define TCG_TARGET_HAS_orc_i64 |
| 120 | 120 |
#endif |
| 121 | 121 |
|
| 122 |
/* Note: must be synced with dyngen-exec.h and Makefile.target */
|
|
| 122 |
/* Note: must be synced with dyngen-exec.h */ |
|
| 123 | 123 |
#ifdef CONFIG_SOLARIS |
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#define TCG_AREG0 TCG_REG_G2 |
| 125 |
#define TCG_AREG1 TCG_REG_G3 |
|
| 126 |
#define TCG_AREG2 TCG_REG_G4 |
|
| 127 | 125 |
#elif defined(__sparc_v9__) |
| 128 | 126 |
#define TCG_AREG0 TCG_REG_G5 |
| 129 |
#define TCG_AREG1 TCG_REG_G6 |
|
| 130 |
#define TCG_AREG2 TCG_REG_G7 |
|
| 131 | 127 |
#else |
| 132 | 128 |
#define TCG_AREG0 TCG_REG_G6 |
| 133 |
#define TCG_AREG1 TCG_REG_G1 |
|
| 134 |
#define TCG_AREG2 TCG_REG_G2 |
|
| 135 | 129 |
#endif |
| 136 | 130 |
|
| 137 | 131 |
static inline void flush_icache_range(unsigned long start, unsigned long stop) |
| b/tcg/x86_64/tcg-target.h | ||
|---|---|---|
| 89 | 89 |
|
| 90 | 90 |
/* Note: must be synced with dyngen-exec.h */ |
| 91 | 91 |
#define TCG_AREG0 TCG_REG_R14 |
| 92 |
#define TCG_AREG1 TCG_REG_R15 |
|
| 93 |
#define TCG_AREG2 TCG_REG_R12 |
|
| 94 | 92 |
|
| 95 | 93 |
static inline void flush_icache_range(unsigned long start, unsigned long stop) |
| 96 | 94 |
{
|
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