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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#define TCG_TARGET_SPARC 1
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#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
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#define TCG_TARGET_REG_BITS 64
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#else
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#define TCG_TARGET_REG_BITS 32
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#endif
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#define TCG_TARGET_WORDS_BIGENDIAN
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#define TCG_TARGET_NB_REGS 32
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enum {
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    TCG_REG_G0 = 0,
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    TCG_REG_G1,
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    TCG_REG_G2,
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    TCG_REG_G3,
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    TCG_REG_G4,
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    TCG_REG_G5,
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    TCG_REG_G6,
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    TCG_REG_G7,
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    TCG_REG_O0,
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    TCG_REG_O1,
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    TCG_REG_O2,
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    TCG_REG_O3,
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    TCG_REG_O4,
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    TCG_REG_O5,
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    TCG_REG_O6,
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    TCG_REG_O7,
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    TCG_REG_L0,
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    TCG_REG_L1,
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    TCG_REG_L2,
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    TCG_REG_L3,
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    TCG_REG_L4,
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    TCG_REG_L5,
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    TCG_REG_L6,
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    TCG_REG_L7,
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    TCG_REG_I0,
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    TCG_REG_I1,
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    TCG_REG_I2,
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    TCG_REG_I3,
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    TCG_REG_I4,
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    TCG_REG_I5,
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    TCG_REG_I6,
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    TCG_REG_I7,
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};
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#define TCG_CT_CONST_S11 0x100
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#define TCG_CT_CONST_S13 0x200
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_I6
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#ifdef __arch64__
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// Reserve space for AREG0
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#define TCG_TARGET_STACK_MINFRAME (176 + 4 * (int)sizeof(long) + \
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                                   TCG_STATIC_CALL_ARGS_SIZE)
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#define TCG_TARGET_CALL_STACK_OFFSET (2047 - 16)
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#define TCG_TARGET_STACK_ALIGN 16
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#else
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// AREG0 + one word for alignment
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#define TCG_TARGET_STACK_MINFRAME (92 + (2 + 1) * (int)sizeof(long) + \
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                                   TCG_STATIC_CALL_ARGS_SIZE)
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#define TCG_TARGET_CALL_STACK_OFFSET TCG_TARGET_STACK_MINFRAME
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#define TCG_TARGET_STACK_ALIGN 8
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#endif
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/* optional instructions */
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#define TCG_TARGET_HAS_div_i32
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// #define TCG_TARGET_HAS_rot_i32
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// #define TCG_TARGET_HAS_ext8s_i32
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// #define TCG_TARGET_HAS_ext16s_i32
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// #define TCG_TARGET_HAS_ext8u_i32
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// #define TCG_TARGET_HAS_ext16u_i32
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// #define TCG_TARGET_HAS_bswap16_i32
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// #define TCG_TARGET_HAS_bswap32_i32
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#define TCG_TARGET_HAS_neg_i32
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#define TCG_TARGET_HAS_not_i32
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#define TCG_TARGET_HAS_andc_i32
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#define TCG_TARGET_HAS_orc_i32
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_div_i64
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// #define TCG_TARGET_HAS_rot_i64
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// #define TCG_TARGET_HAS_ext8s_i64
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// #define TCG_TARGET_HAS_ext16s_i64
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#define TCG_TARGET_HAS_ext32s_i64
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// #define TCG_TARGET_HAS_ext8u_i64
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// #define TCG_TARGET_HAS_ext16u_i64
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#define TCG_TARGET_HAS_ext32u_i64
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// #define TCG_TARGET_HAS_bswap16_i64
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// #define TCG_TARGET_HAS_bswap32_i64
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// #define TCG_TARGET_HAS_bswap64_i64
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#define TCG_TARGET_HAS_neg_i64
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#define TCG_TARGET_HAS_not_i64
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#define TCG_TARGET_HAS_andc_i64
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#define TCG_TARGET_HAS_orc_i64
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#endif
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/* Note: must be synced with dyngen-exec.h */
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#ifdef CONFIG_SOLARIS
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#define TCG_AREG0 TCG_REG_G2
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#elif defined(__sparc_v9__)
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#define TCG_AREG0 TCG_REG_G5
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#else
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#define TCG_AREG0 TCG_REG_G6
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#endif
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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    unsigned long p;
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    p = start & ~(8UL - 1UL);
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    stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
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    for (; p < stop; p += 8)
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        __asm__ __volatile__("flush\t%0" : : "r" (p));
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}