Revision a73d39ba target-sh4/translate.c

b/target-sh4/translate.c
584 584 
    case 0x000f:		/* mac.l @Rm+,@Rn+ */
585 585 
	gen_op_movl_rN_T0(REG(B11_8));
586 586 
	gen_op_ldl_T0_T0(ctx);
587 
	gen_op_movl_T0_T1();
587 
	tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
588 588 
	gen_op_movl_rN_T0(REG(B7_4));
589 589 
	gen_op_ldl_T0_T0(ctx);
590 590 
	gen_op_macl_T0_T1();
......
594 594 
    case 0x400f:		/* mac.w @Rm+,@Rn+ */
595 595 
	gen_op_movl_rN_T0(REG(B11_8));
596 596 
	gen_op_ldl_T0_T0(ctx);
597 
	gen_op_movl_T0_T1();
597 
	tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
598 598 
	gen_op_movl_rN_T0(REG(B7_4));
599 599 
	gen_op_ldl_T0_T0(ctx);
600 600 
	gen_op_macw_T0_T1();
......
813 813 
    case 0xcd00:		/* and.b #imm,@(R0,GBR) */
814 814 
	gen_op_movl_rN_T0(REG(0));
815 815 
	gen_op_addl_GBR_T0();
816 
	gen_op_movl_T0_T1();
816 
	tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
817 817 
	gen_op_ldub_T0_T0(ctx);
818 818 
	gen_op_and_imm_T0(B7_0);
819 819 
	gen_op_stb_T0_T1(ctx);
......
865 865 
    case 0xc000:		/* mov.b R0,@(disp,GBR) */
866 866 
	gen_op_stc_gbr_T0();
867 867 
	gen_op_addl_imm_T0(B7_0);
868 
	gen_op_movl_T0_T1();
868 
	tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
869 869 
	gen_op_movl_rN_T0(REG(0));
870 870 
	gen_op_stb_T0_T1(ctx);
871 871 
	return;
872 872 
    case 0xc100:		/* mov.w R0,@(disp,GBR) */
873 873 
	gen_op_stc_gbr_T0();
874 874 
	gen_op_addl_imm_T0(B7_0 * 2);
875 
	gen_op_movl_T0_T1();
875 
	tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
876 876 
	gen_op_movl_rN_T0(REG(0));
877 877 
	gen_op_stw_T0_T1(ctx);
878 878 
	return;
879 879 
    case 0xc200:		/* mov.l R0,@(disp,GBR) */
880 880 
	gen_op_stc_gbr_T0();
881 881 
	gen_op_addl_imm_T0(B7_0 * 4);
882 
	gen_op_movl_T0_T1();
882 
	tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
883 883 
	gen_op_movl_rN_T0(REG(0));
884 884 
	gen_op_stl_T0_T1(ctx);
885 885 
	return;
......
917 917 
    case 0xcf00:		/* or.b #imm,@(R0,GBR) */
918 918 
	gen_op_movl_rN_T0(REG(0));
919 919 
	gen_op_addl_GBR_T0();
920 
	gen_op_movl_T0_T1();
920 
	tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
921 921 
	gen_op_ldub_T0_T0(ctx);
922 922 
	gen_op_or_imm_T0(B7_0);
923 923 
	gen_op_stb_T0_T1(ctx);
......
942 942 
    case 0xce00:		/* xor.b #imm,@(R0,GBR) */
943 943 
	gen_op_movl_rN_T0(REG(0));
944 944 
	gen_op_addl_GBR_T0();
945 
	gen_op_movl_T0_T1();
945 
	tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
946 946 
	gen_op_ldub_T0_T0(ctx);
947 947 
	gen_op_xor_imm_T0(B7_0);
948 948 
	gen_op_stb_T0_T1(ctx);
......
1110 1110 
	return;
1111 1111 
    case 0x401b:		/* tas.b @Rn */
1112 1112 
	gen_op_movl_rN_T0(REG(B11_8));
1113 
	gen_op_movl_T0_T1();
1113 
	tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
1114 1114 
	gen_op_ldub_T0_T0(ctx);
1115 1115 
	gen_op_cmp_eq_imm_T0(0);
1116 1116 
	gen_op_or_imm_T0(0x80);

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