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# Date Author Comment
091959de 05/14/2011 05:54 pm Aurelien Jarno

Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf

  • 'ppc-next' of git://repo.or.cz/qemu/agraf:
    PPC: Qdev'ify e500 pci
    PPC MPC7544DS: Use new TLB helper function
    PPC: Implement e500 (FSL) MMU
    PPC: Add another 64 bits to instruction feature mask...
71afeb61 05/12/2011 01:24 am Alexander Graf

PPC: Add GS MSR definition

The BookE specification defines MSR bit 28 as Guest State. Add it
to the list of MSR macros.

Signed-off-by: Alexander Graf <>

a5858d7a 05/12/2011 01:24 am Alexander Graf

PPC: Add another 64 bits to instruction feature mask

To enable quick runtime detection of instruction groups to the currently
selected CPU emulation, we have a feature mask of what exactly the respective
instruction supports.

This feature mask is 64 bits long and we just successfully exceeded those 64...

01662f3e 05/12/2011 01:24 am Alexander Graf

PPC: Implement e500 (FSL) MMU

Most of the code to support e500 style MMUs is already in place, but
we're missing on some of the special TLB0-TLB1 handling code and slightly
different TLB modification.

This patch adds support for the FSL style MMU.

Signed-off-by: Alexander Graf <>

64e07be5 05/09/2011 11:31 pm Alexander Graf

kvm: ppc: detect old headers

When compiling Qemu with older kernel headers, the PVR setting
mechanism isn't available yet. Unfortunately, back then I didn't add
a capability we could check against, so all we can do is add a configure
test to see if we support PVR setting. For BookE, we don't care yet....

5666ca4a 05/09/2011 11:31 pm Scott Wood

kvm: ppc: fixes for KVM_SET_SREGS on init

Classic/server ppc has had SREGS for a while now (though I think not
always?), but it's still missing for booke. Check the capability before
calling KVM_SET_SREGS.

Without this, booke kvm fails to boot as of commit...

90dc8812 05/09/2011 11:31 pm Scott Wood

monitor: add PPC BookE SPRs

Read them via KVM_GET_SREGS in kvm_arch_get_registers(),
and display them in "info registers".

Also get CR and PID from the existing KVM_GET_REGS.

Signed-off-by: Scott Wood <>
Signed-off-by: Alexander Graf <>

60b14d95 05/08/2011 12:02 pm Stefan Weil

Fix typos in comments (instanciation -> instantiation)

Signed-off-by: Stefan Weil <>
Signed-off-by: Stefan Hajnoczi <>

5b46d07d 05/08/2011 12:02 pm Stefan Weil

Fix typo in comment (embeded -> embedded)

Signed-off-by: Stefan Weil <>
Signed-off-by: Stefan Hajnoczi <>

618ba8e6 04/20/2011 11:37 am Stefan Weil

Remove unused function parameter from cpu_restore_state

The previous patch removed the need for parameter puc.
Is is now unused, so remove it.

Cc: Aurelien Jarno <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Stefan Weil <>

e87b7cb0 04/20/2011 11:33 am Stefan Weil

Remove unused function parameters from gen_pc_load and rename the function

Function gen_pc_load was introduced in commit
d2856f1ad4c259e5766847c49acbb4e390731bd4.
The only reason for parameter searched_pc was
a debug statement in target-i386/translate.c....

019702c8 04/17/2011 09:32 pm Aurelien Jarno

target-ppc: fix SPE comparison functions

efstst*() functions are fast SPE funtions which do not take into account
special values (infinites, NaN, etc.), while efscmp*() functions are
IEEE754 compliant.

Given that float32_*() functions are IEEE754 compliant, the efscmp*()...

211315fb 04/17/2011 09:32 pm Aurelien Jarno

softfloat: rename float*_eq() into float*_eq_quiet()

float*_eq functions have a different semantics than other comparison
functions. Fix that by first renaming float*_quiet() into float*_eq_quiet().

Note that it is purely mechanical, and the behaviour should be unchanged....

7dae117a 04/12/2011 10:51 pm Aurelien Jarno

target-ppc: remove #ifdef FLOAT128

Now that PPC defaults to softfloat which always provides float128
support, there is no need to keep two version of the code, depending if
float128 support is available or not. Suggested by Peter Maydell.

Reviewed-by: Peter Maydell <>...

4b4a72e5 04/10/2011 01:45 am Stefan Weil

Fix conversions from pointer to tcg_target_long

tcg_gen_exit_tb takes a parameter of type tcg_target_long,
so the type casts of pointer to long should be replaced by
type casts of pointer to tcg_target_long (suggested by Blue Swirl).

These changes are needed for build environments where...

69577857 04/08/2011 01:20 pm David Gibson

ppce500_mpc8544ds: Fix compile with --enable-debug and --disable-kvm

When configured with --enable-debug, we compile without optimization.
This means that the function mpc8544_copy_soc_cell() in ppce500_mpc8544ds.c
is not optimized out, even though it is never called without kvm. That in...

3601ff11 04/08/2011 12:32 pm David Gibson

Use existing helper function to implement popcntd instruction

The recent patches adding partial support for POWER7 cpu emulation included
implementing the popcntd instruction. The support for this was open coded,
but host-utils.h already included a function implementing an equivalent...

ed120055 04/01/2011 07:34 pm David Gibson

Implement PAPR VPA functions for pSeries shared processor partitions

Shared-processor partitions are those where a CPU is time-sliced between
partitions, rather than being permanently dedicated to a single
partition. qemu emulated partitions, since they are just scheduled with...

b45d63b6 04/01/2011 07:34 pm Ben Herrenschmidt

Implement PAPR CRQ hypercalls

This patch implements the infrastructure and hypercalls necessary for the
PAPR specified CRQ (Command Request Queue) mechanism. This general
request queueing system is used by many of the PAPR virtual IO devices,
including the virtual scsi adapter....

8500e3a9 04/01/2011 07:34 pm David Gibson

Clean up slb_lookup() function

The slb_lookup() function, used in the ppc translation path returns a
number of slb entry fields in reference parameters. However, only one
of the two callers of slb_lookup() actually wants this information.

This patch, therefore, makes slb_lookup() return a simple pointer to the...

bb593904 04/01/2011 07:34 pm David Gibson

Parse SDR1 on mtspr instead of at translate time

On ppc machines with hash table MMUs, the special purpose register SDR1
contains both the base address of the encoded size (hashed) page tables.

At present, we interpret the SDR1 value within the address translation...

fda6a0ec 04/01/2011 07:34 pm David Gibson

Use "hash" more consistently in ppc mmu code

Currently, get_segment() has a variable called hash. However it doesn't
(quite) get the hash value for the ppc hashed page table. Instead it
gets the hash shifted - effectively the offset of the hash bucket within...

256cebe5 04/01/2011 07:34 pm David Gibson

Better factor the ppc hash translation path

Currently the path handling hash page table translation in get_segment()
has a mix of common and 32 or 64 bit specific code. However the
division is not done terribly well which results in a lot of messy code
flipping between common and divided paths....

cdaee006 04/01/2011 07:34 pm David Gibson

Support 1T segments on ppc

Traditionally, the "segments" used for the two-stage translation used on
powerpc MMUs were 256MB in size. This was the only option on all hash
page table based 32-bit powerpc cpus, and on the earlier 64-bit hash page
table based cpus. However, newer 64-bit cpus also permit 1TB segments...

9d52e907 04/01/2011 07:34 pm David Gibson

Add POWER7 support for ppc

This adds emulation support for the recent POWER7 cpu to qemu. It's far
from perfect - it's missing a number of POWER7 features so far, including
any support for VSX or decimal floating point instructions. However, it's
close enough to boot a kernel with the POWER7 PVR....

f43e3525 04/01/2011 07:34 pm David Gibson

Virtual hash page table handling on pSeries machine

On pSeries logical partitions, excepting the old POWER4-style full system
partitions, the guest does not have direct access to the hardware page
table. Instead, the pagetable exists in hypervisor memory, and the guest...

81762d6d 04/01/2011 07:34 pm David Gibson

Clean up PowerPC SLB handling code

Currently the SLB information when emulating a PowerPC 970 is
storeed in a structure with the unhelpfully named fields 'tmp'
and 'tmp64'. While the layout in these fields does match the
description of the SLB in the architecture document, it is not...

d569956e 04/01/2011 07:34 pm David Gibson

Add a hook to allow hypercalls to be emulated on PowerPC

PowerPC and POWER chips since the POWER4 and 970 have a special
hypervisor mode, and a corresponding form of the system call
instruction which traps to the hypervisor.

qemu currently has stub implementations of hypervisor mode. That...

efdef95f 04/01/2011 07:34 pm David Gibson

Implement PowerPC slbmfee and slbmfev instructions

For a 64-bit PowerPC target, qemu correctly implements translation
through the segment lookaside buffer. Likewise it supports the
slbmte instruction which is used to load entries into the SLB.

However, it does not emulate the slbmfee and slbmfev instructions...

3a7f009a 04/01/2011 07:34 pm David Gibson

Implement missing parts of the logic for the POWER PURR

The PURR (Processor Utilization Resource Register) is a register found
on recent POWER CPUs. The guts of implementing it at least enough to
get by are already present in qemu, however some of the helper...

eaabeef2 04/01/2011 07:34 pm David Gibson

Correct ppc popcntb logic, implement popcntw and popcntd

qemu already includes support for the popcntb instruction introduced
in POWER5 (although it doesn't actually allow you to choose POWER5).

However, the logic is slightly incorrect: it will generate results...

17d9b3af 04/01/2011 07:34 pm Aurelien Jarno

target-ppc: ext32u instead of andi with constant

Cc: Alexander Graf <>
Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>

a0e13900 03/22/2011 08:17 am Fabien Chouteau

target-ppc: add support for 6 SPE instructions

Add support for 6 SPE instructions: evmra, evmwsmi{a{a}}, evmwumi{a{a}}

Signed-off-by: Fabien Chouteau <>
Reviewed-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

31b7c261 03/22/2011 12:42 am Anthony Liguori

Merge remote branch 'qemu-kvm/uq/master' into staging

74475455 03/21/2011 10:23 am Paolo Bonzini

change all other clock references to use nanosecond resolution accessors

This was done with:

sed -i 's/qemu_get_clock\>/qemu_get_clock_ns/' \
$(git grep -l 'qemu_get_clock\>' )
sed -i 's/qemu_new_timer\>/qemu_new_timer_ns/' \
$(git grep -l 'qemu_new_timer\>' )...
bb4ea393 03/16/2011 10:11 pm Jan Kiszka

kvm: Align kvm_arch_handle_exit to kvm_cpu_exec changes

Make the return code of kvm_arch_handle_exit directly usable for
kvm_cpu_exec. This is straightforward for x86 and ppc, just s390
would require more work. Avoid this for now by pushing the return code...

99036865 03/15/2011 06:19 am Jan Kiszka

kvm: Rename kvm_arch_process_irqchip_events to async_events

We will broaden the scope of this function on x86 beyond irqchip events.

Signed-off-by: Jan Kiszka <>
Signed-off-by: Marcelo Tosatti <>

bdcbd3e2 03/15/2011 06:19 am Jan Kiszka

kvm: ppc: Fix breakage of kvm_arch_pre_run/process_irqchip_events

Commit 7a39fe5882 failed to convert the right arch function.

Signed-off-by: Jan Kiszka <>
Signed-off-by: Marcelo Tosatti <>

eda48c34 03/13/2011 04:44 pm Paolo Bonzini

inline cpu_halted into sole caller

All implementations are now the same, and there is only one caller,
so inline the function there.

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Blue Swirl <>

c5d69e6b 02/16/2011 04:47 pm Anthony Liguori

Merge remote branch 'qemu-kvm/uq/master' into staging

630ecca0 02/16/2011 04:35 pm Tristan Gingold

Handle icount for powerpc tbl/tbu/decr load and store.

Handle option '-icount X' on powerpc targets.

Signed-off-by: Tristan Gingold <>
Signed-off-by: Edgar E. Iglesias <>

7a39fe58 02/14/2011 04:39 pm Jan Kiszka

kvm: Drop return values from kvm_arch_pre/post_run

We do not check them, and the only arch with non-empty implementations
always returns 0 (this is also true for qemu-kvm).

Signed-off-by: Jan Kiszka <>
CC: Alexander Graf <>...

a1b87fe0 02/14/2011 04:39 pm Jan Kiszka

kvm: Provide sigbus services arch-independently

Provide arch-independent kvm_on_sigbus* stubs to remove the #ifdef'ery
from cpus.c. This patch also fixes --disable-kvm build by providing the
missing kvm_on_sigbus_vcpu kvm-stub.

Signed-off-by: Jan Kiszka <>...

b3a98367 02/01/2011 11:32 pm Anthony Liguori

Merge remote branch 'qemu-kvm/uq/master' into staging

aliguori: fix build with !defined(KVM_CAP_ASYNC_PF)

Signed-off-by: Anthony Liguori <>

94a8d39a 01/23/2011 06:27 am Jan Kiszka

kvm: Consolidate must-have capability checks

Instead of splattering the code with #ifdefs and runtime checks for
capabilities we cannot work without anyway, provide central test
infrastructure for verifying their availability both at build and
runtime.

Signed-off-by: Jan Kiszka <>...

cad1e282 01/23/2011 06:27 am Jan Kiszka

kvm: Drop smp_cpus argument from init functions

No longer used.

Signed-off-by: Jan Kiszka <>
Signed-off-by: Marcelo Tosatti <>

73aaec4a 01/23/2011 06:27 am Jan Kiszka

kvm: Stop on all fatal exit reasons

Ensure that we stop the guest whenever we face a fatal or unknown exit
reason. If we stop, we also have to enforce a cpu loop exit.

Signed-off-by: Jan Kiszka <>
Signed-off-by: Marcelo Tosatti <>

5823947f 01/22/2011 12:12 am Edgar E. Iglesias

ppc: Correct BookE tlb reads

Call the tlb read helper (and not the write helper) for tlb
reads.

Signed-off-by: Edgar E. Iglesias <>

d788b570 01/20/2011 04:11 pm Aurelien Jarno

target-ppc: fix wrong NaN tests

Some tests in FPU emulation code were wrongly using float64_is_nan()
before commit 185698715dfb18c82ad2a5dbc169908602d43e81, and wrongly
using float64_is_quiet_nan() after. Fix them by using float64_is_any_nan()
instead.

Reviewed-by: Nathan Froyd <>...

96912e39 01/20/2011 04:11 pm Aurelien Jarno

target-ppc: fix sNaN propagation

The current FPU code returns 0.0 if one of the operand is a
signaling NaN and the VXSNAN exception is disabled.

fload_invalid_op_excp() doesn't return a qNaN in case of a VXSNAN
exception as the operand should be propagated instead of a new...

82b323cd 01/06/2011 05:12 pm Aurelien Jarno

target-ppc: use float32_is_any_nan()

Use the new function float32_is_any_nan() instead of
float32_is_quiet_nan() || float32_is_signaling_nan().

Acked-by: Alexander Graf <>
Signed-off-by: Aurelien Jarno <>

3eb28bbd 01/06/2011 05:10 pm Aurelien Jarno

target-ppc: fix default qNaN

On PPC the default qNaN doesn't have the sign bit set.

Acked-by: Alexander Graf <>
Signed-off-by: Aurelien Jarno <>

dd94ad96 01/06/2011 05:10 pm Aurelien Jarno

target-ppc: remove PRECISE_EMULATION define

The PRECISE_EMULATION is "hardcoded" to one in target-ppc/exec.h and not
something easily tunable. Remove it and non-precise emulation code as
it doesn't make a noticeable difference in speed. People wanting speed...

18569871 01/02/2011 12:15 pm Peter Maydell

softfloat: Rename float*_is_nan() functions to float*_is_quiet_nan()

The softfloat functions float*_is_nan() were badly misnamed,
because they return true only for quiet NaNs, not for all NaNs.
Rename them to float*_is_quiet_nan() to more accurately reflect...

6d5c34fa 12/31/2010 10:17 pm Mike Pall

Fix translation of unary PPC/SPE instructions (efdneg etc.).

Signed-off-by: Mike Pall <>
Signed-off-by: Aurelien Jarno <>

138b38b6 12/08/2010 10:30 pm Alexander Graf

ppc: kvm: fix signedness warning

I get a warning on a signed comparison with an unsigned variable, so
let's make the variable signed and be happy.

Signed-off-by: Alexander Graf <>
Signed-off-by: Edgar E. Iglesias <>

9a78eead 10/30/2010 11:01 am Stefan Weil

target-xxx: Use fprintf_function (format checking)

fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
  • target-i386/helper.c
  • target-mips/translate.c
  • target-ppc/translate.c

Cc: Blue Swirl <>
Signed-off-by: Stefan Weil <>...

577f25a5 10/13/2010 09:43 pm Blue Swirl

ppc: avoid write only variables

Compiling with GCC 4.6.0 20100925 produced warnings:
/src/qemu/target-ppc/op_helper.c: In function 'helper_icbi':
/src/qemu/target-ppc/op_helper.c:351:14: error: variable 'tmp' set but not used [-Werror=unused-but-set-variable]...

ae0bfb79 10/13/2010 09:38 pm Blue Swirl

ppc: remove video.x

Only Mac-on-Linux stuff used video.x, OpenBIOS does not need it.

Remove video.x MoL hacks.

Signed-off-by: Alexander Graf <>
Signed-off-by: Blue Swirl <>

999fa40e 10/05/2010 07:38 pm John Clark

ppc: Minor 40x MMU fixes

  • Fix swapped reading of tlblo/hi.
  • Fix tlb exec permissions

Signed-off-by: John Clark <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Edgar E. Iglesias <>

2c50e26e 09/30/2010 07:53 pm Edgar E. Iglesias

powerpc: Add a virtex5 ml507 refdesign board

Signed-off-by: Edgar E. Iglesias <>
Signed-off-by: Alexander Graf <>

95070372 09/30/2010 07:53 pm Edgar E. Iglesias

powerpc: Add a ppc-440x5 Xilinx model

Add a powerpc 440x5 with the model ID on the Xilinx virtex5.
Connect the 440x5 to the 40x interrupt logic.

Signed-off-by: Edgar E. Iglesias <>
Signed-off-by: Alexander Graf <>

a586e548 09/24/2010 11:01 pm Edgar E. Iglesias

powerpc: Improve emulation of the BookE MMU

Improve the emulation of the BookE MMU to be able to boot linux
on virtex5 boards.

Signed-off-by: Edgar E. Iglesias <>

d62d2863 09/18/2010 08:53 am Blue Swirl

PPC: Suppress gcc warnings with -Wtype-limits

The hack added by c5b76b381081680633e2e0a91216507430409fb2 was not
enough to avoid warnings with gcc flag -Wtype-limits. Add a new macro
to fix both problems.

Signed-off-by: Blue Swirl <>

41557447 09/15/2010 05:18 pm Alexander Graf

PPC: Redesign interrupt trigger path

According to the Book3S spec, the interrupt context starts with an MSR
value that is rather simple. If we leave out the HV case, it's almost
always 0.

To reflect this, let's redesign the way that MSR value gets calculated....

f844c817 09/15/2010 05:18 pm Alexander Graf

PPC: Enable hint bits for lwarx/ldarx

The lwarx and ldarx instructions have a bit to give some hint to the
CPU which is safe to ignore. We currently refuse to accept any instruction
with that bit set, as it used to be declared MBZ.

Let's remove the reserved bit and make the instruction work as expected....

24e0e38b 09/11/2010 03:29 pm Edgar E. Iglesias

powerpc: Avoid TLB related log spamming

Invalid TLB entries are normal and should not spam the log.

Signed-off-by: Edgar E. Iglesias <>

fc87e185 09/05/2010 12:50 pm Alexander Graf

KVM: PPC: Add level based interrupt logic

KVM on PowerPC used to have completely broken interrupt logic. Usually,
interrupts work by having a PIC that pulls a line up/down, so the CPU knows
that an interrupt is active. This line stays active until some action is...

45024f09 08/26/2010 07:13 pm Alexander Graf

PPC: Add PV hypercall transport through fw_cfg

On KVM for PPC we need to tell the guest which instructions to use when
doing a hypercall. The clean way to do this is to go through an ioctl
from userspace and passing it on to the guest using the device tree....

488243b0 07/19/2010 01:33 am Aurelien Jarno

target-ppc: fix power mode checking on 7400/7410

Only the PowerPC 7440/7450 family don't support DOZE mode. PowerPC
7400 and 7410 support it.

0bffbc6c 07/13/2010 07:18 pm Aurelien Jarno

target-ppc: add vexptefp instruction

Signed-off-by: Aurelien Jarno <>

a88790a1 07/03/2010 09:48 am Paolo Bonzini

remove exec-all.h inclusion from cpu.h

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Blue Swirl <>

10eb0cc0 07/03/2010 09:48 am Paolo Bonzini

move cpu_pc_from_tb to target-*/exec.h

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Blue Swirl <>

2bece2c8 06/16/2010 12:29 pm Richard Henderson

tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.

Some hosts (amd64, ia64) have an ABI that ignores the high bits
of the 64-bit register when passing 32-bit arguments. Others
require the value to be properly sign-extended for the type.
I.e. "int32_t" must be sign-extended and "uint32_t" must be...

0f89cc7b 05/31/2010 08:18 pm Thomas Monjalon

target-ppc: remove useless line

This line was a bit clear.
The next lines set or reset this bit (LE) depending of another bit (ILE).
So the first line is useless.

Signed-off-by: Thomas Monjalon <>
Signed-off-by: Aurelien Jarno <>

c3d420ea 05/31/2010 08:17 pm Thomas Monjalon

target-ppc: fix RFI by clearing some bits of MSR

Since commit 2ada0ed, "Return From Interrupt" is broken for PPC processors
because some interrupt specifics bits of SRR1 are copied to MSR.

SRR1 is a save of MSR during interrupt.
During RFI, MSR must be restored from SRR1....

0bfcd599 05/22/2010 11:02 am Blue Swirl

Fix %lld or %llx printf format use

Signed-off-by: Blue Swirl <>

c821c2bd 05/18/2010 09:21 pm Alexander Graf

PPC/KVM: make iothread work

When running with --enable-io-thread the timer we have doesn't help,
because it doesn't wake up the CPU thread. So instead we need to
actually kick it.

While at it I refined the logic a bit to not dumbly trigger a timer
every 500ms, but rather do it more often after an interrupt got injected....

4513d923 05/11/2010 08:03 pm Gleb Natapov

Do not stop VM if emulation failed in userspace.

Continue vcpu execution in case emulation failure happened while vcpu
was in userspace. In this case #UD will be injected into the guest
allowing guest OS to kill offending process and continue.

Signed-off-by: Gleb Natapov <>...

0af691d7 05/11/2010 08:02 pm Marcelo Tosatti

kvm: enable smp > 1

Process INIT/SIPI requests and enable -smp > 1.

Signed-off-by: Marcelo Tosatti <>
Signed-off-by: Avi Kivity <>

8d0d2eb6 05/05/2010 01:20 pm Richard Henderson

target-ppc: Remove duplicate cpu log.

Logging for -d cpu is done in generic code.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

05f92404 04/25/2010 11:32 pm Blue Swirl

ppc: remove dead assignments, spotted by clang analyzer

Value stored is never read.

Signed-off-by: Blue Swirl <>

7b13448f 04/18/2010 05:26 pm Blue Swirl

PPC: avoid function pointer type mismatch, spotted by clang

Fixes clang errors:
CC ppc-softmmu/translate.o
/src/qemu/target-ppc/translate.c:3748:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *')
if (likely(read_cb != SPR_NOACCESS)) {...

de6a1dec 03/27/2010 12:37 am Dmitry Ilyevsky

target-ppc: generic PowerPC TBL

Time base SPRs TBL/TBU should be accessible in user/priv modes for reading
as specified in POWER ISA documentation. Therefore SPRs permissions were
changed in gen_tbl function.

Signed-off-by: Dmitry Ilyevsky <>...

d4c430a8 03/17/2010 04:44 am Paul Brook

Large page TLB flush

QEMU uses a fixed page size for the CPU TLB. If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate...

3c7b48b7 03/12/2010 08:44 pm Paul Brook

Target specific usermode cleanup

Disable various target specific code that is only relevant to system emulation.

Signed-off-by: Paul Brook <>

4fcc562b 03/12/2010 08:34 pm Paul Brook

Remove cpu_get_phys_page_debug from userspace emulation

cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <>

52705890 03/12/2010 06:28 pm Richard Henderson

Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.

Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha. This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place....

0aef4261 03/11/2010 10:29 pm Aurelien Jarno

target-ppc: fix evsrwu and evsrws (second try)

Signed-off-by: Aurelien Jarno <>

26b14dc4 03/11/2010 10:22 pm Aurelien Jarno

target-ppc: fix evsrwu and evsrws

Signed-off-by: Aurelien Jarno <>

e29ef9fa 03/11/2010 10:14 pm Aurelien Jarno

target-ppc: fix evslw instruction

Signed-off-by: Aurelien Jarno <>

ea375f9a 03/04/2010 05:29 am Jan Kiszka

KVM: Rework VCPU state writeback API

This grand cleanup drops all reset and vmsave/load related
synchronization points in favor of four(!) generic hooks:

- cpu_synchronize_all_states in qemu_savevm_state_complete
(initial sync from kernel before vmsave)...

db9a231d 02/28/2010 05:36 pm Aurelien Jarno

Revert "target-ppc: stop translation after a trap instruction"

This reverts commit 6454e7be1b2504533f7ffb190d54ebe2993cb434.

6c712321 02/28/2010 05:36 pm Aurelien Jarno

target-ppc: don't print invalid opcode messages on the console

Invalid opcode messages can be perfectly normal, for example if this
code is never executed. Don't print an error message on the console,
but keep the message in the log for debugging purposes....

6454e7be 02/28/2010 03:11 pm Aurelien Jarno

target-ppc: stop translation after a trap instruction

Signed-off-by: Aurelien Jarno <>

ae01847f 02/27/2010 05:10 pm Nathan Froyd

target-ppc: fix SPE evsplat* instructions

The shifts in the gen_evsplat* functions were expecting rA to be masked,
not extracted, and so used the wrong shift amounts to sign-extend or pad
with zeroes.

Signed-off-by: Nathan Froyd <>...

e6bba2ef 02/27/2010 05:10 pm Nathan Froyd

target-ppc: fix SPE evcmp* instructions

The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit
position. Because of this, the SPE evcmp* family of instructions would
store values in the result condition register that were also off by one
bit position....

dc333cd6 02/14/2010 04:10 pm Alexander Graf

PPC: tell the guest about the time base frequency

Our guest systems need to know by how much the timebase increases every second,
so there usually is a "timebase-frequency" property in the cpu leaf of the
device tree.

This property is missing in OpenBIOS....

b2eca445 02/14/2010 04:10 pm Alexander Graf

PPC: Fix large pages

We were masking 1TB SLB entries on the feature bit of 16 MB pages. Obviously
that breaks, so let's just ignore 1TB SLB entries for now and instead do
16MB pages correctly.

This fixes PPC64 Linux boot with -m above 256.

Signed-off-by: Alexander Graf <>...

c6a94ba5 02/14/2010 04:10 pm Alexander Graf

PPC: Add timer when running KVM

For some odd reason we sometimes hang inside KVM forever. I'd guess it's
a race condition where we actually have a level triggered interrupt, but
the infrastructure can't expose that yet, so the guest ACKs it, goes to
sleep and never gets notified that there's still an interrupt pending....