/ - Diff - qemu - Greek Research and Technology Network's projects

Revision a750fc0b

                 /* Level sensitive - active high */
     #if defined(PPC_DEBUG_IRQ)
                 if (loglevel & CPU_LOG_INT) {
                     fprintf(logfile, "%s: set the external IRQ state to %d\n",
                     fprintf(logfile, "%s: set the debug pin state to %d\n",
                             __func__, level);
+                }
     #endif
                 ppc_set_irq(env, EXCP_40x_DEBUG, level);
                 ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
                 break;
             default:
                 /* Unknown pin - do nothing */
-...
         void *opaque;
     };
     /* XXX: on 460, DCR addresses are 32 bits wide,
      *      using DCRIPR to get the 22 upper bits of the DCR address
      */
     #define DCRN_NB 1024
     struct ppc_dcr_t {
         ppc_dcrn_t dcrn[DCRN_NB];

         return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
+    }
     /* XXX: to be fixed */
     int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
+    {
         return -1;
+    }
     int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
+    {
         return -1;
+    }
     void cpu_loop(CPUPPCState *env)
+    {
         target_siginfo_t info;
-...
             case EXCP_MACHINE_CHECK:
                 fprintf(stderr, "Machine check exeption...  Stop emulation\n");
                 if (loglevel)
                     fprintf(logfile, "RESET asked... Stop emulation\n");
                     fprintf(logfile, "Machine check exception. Stop emulation\n");
                 info.si_signo = TARGET_SIGBUS;
                 info.si_errno = 0;
                 info.si_code = TARGET_BUS_OBJERR;
-...
                         info.si_code = TARGET_ILL_ILLOPC;
                         break;
                     case EXCP_INVAL_LSWX:
                 info.si_code = TARGET_ILL_ILLOPN;
                         info.si_code = TARGET_ILL_ILLOPN;
                         break;
                     case EXCP_INVAL_SPR:
                         info.si_code = TARGET_ILL_PRVREG;
-...
                     if (loglevel)
                         fprintf(logfile, "Tried to go into supervisor mode !\n");
                     abort();
+            }
+                }
                 break;
             case EXCP_BRANCH:
                 /* We stopped because of a jump... */

     ===============================================================================
     PowerPC core emulation status
 bits PowerPC
     PowerPC 601:
     INSN
     SPR
     MMU
     EXCP
     PowerPC 602:
     INSN
     SPR
     MMU
     EXCP
     PowerPC 603:
     INSN OK
     SPR  OK
     MMU  OK
     EXCP OK
     PowerPC 604:
     INSN OK
     SPR  OK
     MMU  OK
     EXCP OK
     PowerPC 740:
     INSN OK
     SPR  OK
     MMU  OK
     EXCP OK
     PowerPC 745:
     INSN
     SPR
     MMU
     EXCP
     PowerPC 750:
     INSN OK
     SPR  OK
     MMU  OK
     EXCP OK
     PowerPC 755:
     INSN
     SPR
     MMU
     EXCP
     INSN: instruction set.
           OK => all instructions are emulated
           KO => some insns are missing or some should be removed
           ?  => unchecked
     SPR:  special purpose registers set
           OK => all SPR registered (but some may be fake)
           KO => some SPR are missing or should be removed
           ?  => uncheked
     MSR:  MSR bits definitions
           OK => all MSR bits properly defined
           KO => MSR definition is incorrect
           ?  => unchecked
     IRQ:  input signals definitions (mostly interrupts)
           OK => input signals are properly defined
           KO => input signals are not implemented (system emulation does not work)
           ?  => input signals definitions may be incorrect
     MMU:  MMU model implementation
           OK => MMU model is implemented and Linux is able to boot
           KO => MMU model not implemented or bugged
           ?  => MMU model not tested
     EXCP: exceptions model implementation
           OK => exception model is implemented and Linux is able to boot
           KO => exception model not implemented or known to be buggy
           ?  => exception model may be incorrect or is untested
     PowerPC 7400:
     INSN KO
     SPR  KO
     MMU  OK
     EXCP OK
     Embedded PowerPC cores
     ***
     PowerPC 401:
     INSN  OK
     SPR   OK 401A1
     MSR   OK
     IRQ   KO partially implemented
     MMU   OK
     EXCP  ?
     PowerPC 7410:
     INSN KO
     SPR  KO
     MMU  OK
     EXCP OK
     PowerPC 7450:
     INSN KO
     SPR  KO
     MMU  OK
     EXCP OK
     PowerPC 7455:
     INSN KO
     SPR  KO
     MMU  OK
     EXCP OK
     PowerPC 7457:
     INSN KO
     SPR  KO
     MMU  OK
     EXCP OK
     PowerPC 7457A:
     INSN KO
     SPR  KO
     MMU  OK
     EXCP OK
     PowerPC 401x2:
     INSN  OK
     SPR   OK 401B2 401C2 401D2 401E2 401F2
     MSR   OK
     IRQ   KO partially implemented
     MMU   OK
     EXCP  ?
 bits PowerPC
     PowerPC 970:
     INSN KO
     SPR  KO
     MMU  KO
     EXCP KO
     PowerPC 620: (lack of precise informations)
     INSN KO
     SPR  KO
     MMU  KO
     EXCP KO
     PowerPC 630: (lack of precise informations)
     INSN KO
     SPR  KO
     MMU  KO
     EXCP KO
     PowerPC 631: (lack of precise informations)
     INSN KO
     SPR  KO
     MMU  KO
     EXCP KO
     POWER4: (lack of precise informations)
     INSN KO
     SPR  KO
     MMU  KO
     EXCP KO
     POWER4+: (lack of precise informations)
     INSN KO
     SPR  KO
     MMU  KO
     EXCP KO
     POWER5: (lack of precise informations)
     INSN KO
     SPR  KO
     MMU  KO
     EXCP KO
     POWER5+: (lack of precise informations)
     INSN KO
     SPR  KO
     MMU  KO
     EXCP KO
     POWER6: (lack of precise informations)
     INSN KO
     SPR  KO
     MMU  KO
     EXCP KO
     RS64: (lack of precise informations)
     INSN KO
     SPR  KO
     MMU  KO
     EXCP KO
     RS64-II: (lack of precise informations)
     INSN KO
     SPR  KO
     MMU  KO
     EXCP KO
     RS64-III: (lack of precise informations)
     INSN KO
     SPR  KO
     MMU  KO
     EXCP KO
     RS64-IV: (lack of precise informations)
     INSN KO
     SPR  KO
     MMU  KO
     EXCP KO
     PowerPC IOP480:
     INSN  OK
     SPR   OK IOP480
     MSR   OK
     IRQ   KO partially implemented
     MMU   OK
     EXCP  ?
     Embedded PowerPC cores
     PowerPC 401:
     INSN OK
     SPR  OK
     MMU  OK
     EXCP ?
     To be checked: 401G2 401B3 Cobra
     ***
     PowerPC 403:
     INSN OK
     SPR  OK
     MMU  OK
     EXCP ?
     INSN  OK
     SPR   OK 403GA 403GB
     MMU   OK
     MSR   OK
     IRQ   KO not implemented
     EXCP  ?
     PowerPC 403GCX:
     INSN  OK
     SPR   OK 403GCX
     MMU   OK
     MSR   OK
     IRQ   KO not implemented
     EXCP  ?
     To be checked: 403GC
     ***
     PowerPC 405:
     INSN OK
     SPR  OK
     MMU  OK
     EXCP OK
     Checked: 405CRa 405CRb 405CRc 405EP 405GPa 405GPb 405GPc 405GPd 405GPe 405GPR
              Npe405H Npe405H2 Npe405L
     INSN  OK
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   OK
     EXCP  OK
     => Linux 2.4 boots (at least 1 proprietary firmware).
     To be checked: 405D2 405D4 405EZ 405LP Npe4GS3 STB03 STB04 STB25
                    x2vp4 x2vp7 x2vp20 x2vp50
     XXX: find what is IBM e407b4
     ***
     PowerPC 440:
     Checked: 440EPa 440EPb 440GXa 440GXb 440GXc 440GXf 440SP 440SP2
     INSN  OK
     SPR   OK
     MSR   OK
     IRQ   KO not implemented
     MMU   ?
     EXCP  ?
     PowerPC 440GP:
     Checked: 440GPb 440GPc
     INSN  OK
     SPR   OK
     MSR   OK
     IRQ   KO not implemented
     MMU   ?
     EXCP  ?
     PowerPC 440x4:
     Checked: 440A4 440B4 440G4 440H4
     INSN  OK
     SPR   OK
     MSR   OK
     IRQ   KO not implemented
     MMU   ?
     EXCP  ?
     PowerPC 460: (lack of precise informations)
     PowerPC 440x5:
     Checked: 440A5 440F5 440G5 440H6 440GRa
     INSN  OK
     SPR   OK
     MSR   OK
     IRQ   KO not implemented
     MMU   ?
     EXCP  ?
     To be checked: 440EPx 440GRx 440SPE
     ***
     PowerPC 460: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     PowerPC 460F: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     Freescale (to be completed) ...
     ***
     PowerPC e200: (not implemented)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     Original POWER
     POWER: (lack of precise informations)
     ***
     PowerPC e300: (not implemented)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     POWER2: (lack of precise informations)
     ***
     PowerPC e500: (not implemented)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     PowerPC CPU known to work (ie booting at least Linux 2.4):
     * main stream PowerPC cores
     - PowerPC 603 & derivatives
     - PowerPC 604 & derivatives
     - PowerPC 740 & derivatives
     - PowerPC 750 & derivatives
     - PowerPC 405
     PowerPC that should work but are not supported by standard Linux kernel
     (then remain mostly untested)
     - PowerPC 745
     - PowerPC 755
     Work in progress:
     * embedded PowerPC cores
     - BookE PowerPC
     - e500 core (Freescale PowerQUICC)
     * main stream PowerPC cores
     - PowerPC 601
     - PowerPC 602
     ***
     PowerPC e600: (not implemented)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     TODO:
     * embedded PowerPC cores
     - PowerPC 401
     - PowerPC 403
     - PowerPC 440
     - PowerPC 460
     * main stream PowerPC cores
     - PowerPC 7400 (aka G4)
     - PowerPC 7410
     - PowerPC 7450
     - PowerPC 7455
     - PowerPC 7457
     - PowerPC 7457A
     * original POWER
     - POWER
     - POWER2
     * 64 bits PowerPC cores
     - PowerPC 620
     - PowerPC 630 (aka POWER3)
     - PowerPC 631 (aka POWER3+)
     - POWER4
     - POWER4+
     - POWER5
     - POWER5+
     - PowerPC 970
     * RS64 series
     - RS64
     - RS64-II
     - RS64-III
     - RS64-IV
     ***
 bits PowerPC
     PowerPC 601: (601 601v2)
     INSN  OK
     SPR   OK is HID15 only on 601v2 ?
     MSR   OK
     IRQ   KO not implemented
     MMU   ?
     EXCP  ?
     Remarks: some instructions should have a specific behavior (not implemented)
     PowerPC 602: 602
     INSN  OK
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   ?
     EXCP  ? at least timer and external interrupt are OK
     Remarks: Linux crashes when entering user-mode. But it seems it does not
              know about this CPU. As this CPU is close to 603e, it should be OK.
     PowerPC 603: (603)
     INSN  OK
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   OK
     EXCP  OK
     Remarks: Linux 2.4 boots and properly recognizes the CPU
     PowerPC 603e: (603e11)
     INSN  OK
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   OK
     EXCP  OK
     Remarks: Linux 2.4 boots and properly recognizes the CPU
     PowerPC G2:
     INSN  OK
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   OK
     EXCP  OK
     Remarks: Linux 2.4 boots, recognizes the CPU as a 82xx.
     PowerPC G2le:
     INSN  OK
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   OK
     EXCP  OK
     Remarks: Linux 2.4 does not boots. Same symptoms as 602.
     PowerPC 604:
     INSN  OK
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   OK
     EXCP  OK
     Remarks: Linux 2.4 boots and properly recognizes the CPU.
     PowerPC 7x0:
     INSN  OK
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   OK
     EXCP  OK
     Remarks: Linux 2.4 boots and properly recognizes the CPU.
     PowerPC 750fx:
     INSN  OK
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   OK
     EXCP  OK
     Remarks: Linux 2.4 boots but does not properly recognizes the CPU.
     PowerPC 7x5:
     INSN  ?
     SPR   ?
     MSR   ?
     IRQ   OK
     MMU   ?
     EXCP  OK
     => Linux 2.4 does not boot.
     PowerPC 7400:
     INSN  KO Altivec missing
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   OK
     EXCP  ?  Altivec, ...
     => Linux 2.4 boots and properly recognize the CPU.
     PowerPC 7410:
     INSN  KO Altivec missing
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   OK
     EXCP  ?  Altivec, ...
     => Linux 2.4 boots and properly recognize the CPU.
        Note that UM says tlbld & tlbli are implemented bus this may be a mistake
        as TLB load are managed by the hardware and it does not implement the
        needed registers.
     PowerPC 7441:
     INSN  KO Altivec missing + TLB load insns missing
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   KO not implemented
     EXCP  ?  Altivec, ...
     PowerPC 7450/7451:
     INSN  KO Altivec missing + TLB load insns missing
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   KO not implemented
     EXCP  ?  Altivec, ...
     PowerPC 7445/7447:
     INSN  KO Altivec missing + TLB load insns missing
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   KO not implemented
     EXCP  ?  Altivec, ...
     PowerPC 7455/7457:
     INSN  KO Altivec missing + TLB load insns missing
     SPR   OK
     MSR   OK
     IRQ   OK
     MMU   KO not implemented
     EXCP  ?  Altivec, ...
 bits PowerPC
     PowerPC 620: (disabled)
     INSN  KO
     SPR   KO
     MSR   ?
     IRQ   KO
     MMU   KO
     EXCP  KO
     PowerPC 970: (disabled)
     INSN  KO Altivec missing and more
     SPR   KO
     MSR   ?
     IRQ   OK
     MMU   KO partially implemented
     EXCP  KO
     PowerPC 970FX: (disabled)
     INSN  KO Altivec missing and more
     SPR   KO
     MSR   ?
     IRQ   OK
     MMU   KO partially implemented
     EXCP  KO
     PowerPC 630: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     PowerPC 631: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     POWER4: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     POWER4+: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     POWER5: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     POWER5+: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     POWER6: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     RS64: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     RS64-II: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     RS64-III: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     RS64-IV: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     Original POWER
     POWER: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     POWER2: (disabled: lack of detailed specifications)
     INSN  KO
     SPR   KO
     MSR   KO
     IRQ   KO
     MMU   KO
     EXCP  KO
     ===============================================================================
     PowerPC microcontrollers emulation status

     #define DCACHE_LINE_SIZE 32
     /*****************************************************************************/
     /* PVR definitions for most known PowerPC */
     /* MMU model                                                                 */
     enum {
         /* PowerPC 401 cores */
         CPU_PPC_401A1     = 0x00210000,
         CPU_PPC_401B2     = 0x00220000,
     #if 0
         CPU_PPC_401B3     = xxx,
     #endif
         CPU_PPC_401C2     = 0x00230000,
         CPU_PPC_401D2     = 0x00240000,
         CPU_PPC_401E2     = 0x00250000,
         CPU_PPC_401F2     = 0x00260000,
         CPU_PPC_401G2     = 0x00270000,
     #if 0
         CPU_PPC_401GF     = xxx,
     #endif
     #define CPU_PPC_401 CPU_PPC_401G2
         CPU_PPC_IOP480    = 0x40100000, /* 401B2 ? */
         CPU_PPC_COBRA     = 0x10100000, /* IBM Processor for Network Resources */
         /* PowerPC 403 cores */
         CPU_PPC_403GA     = 0x00200011,
         CPU_PPC_403GB     = 0x00200100,
         CPU_PPC_403GC     = 0x00200200,
         CPU_PPC_403GCX    = 0x00201400,
     #if 0
         CPU_PPC_403GP     = xxx,
     #endif
     #define CPU_PPC_403 CPU_PPC_403GCX
         /* PowerPC 405 cores */
     #if 0
         CPU_PPC_405A3     = xxx,
     #endif
     #if 0
         CPU_PPC_405A4     = xxx,
     #endif
     #if 0
         CPU_PPC_405B3     = xxx,
     #endif
         CPU_PPC_405D2     = 0x20010000,
         CPU_PPC_405D4     = 0x41810000,
         CPU_PPC_405CR     = 0x40110145,
     #define CPU_PPC_405GP CPU_PPC_405CR
         CPU_PPC_405EP     = 0x51210950,
     #if 0
         CPU_PPC_405EZ     = xxx,
     #endif
         CPU_PPC_405GPR    = 0x50910951,
     #if 0
         CPU_PPC_405LP     = xxx,
     #endif
     #define CPU_PPC_405 CPU_PPC_405D4
         CPU_PPC_NPE405H   = 0x414100C0,
         CPU_PPC_NPE405H2  = 0x41410140,
         CPU_PPC_NPE405L   = 0x416100C0,
     #if 0
         CPU_PPC_LC77700   = xxx,
     #endif
         /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
     #if 0
         CPU_PPC_STB01000  = xxx,
     #endif
     #if 0
         CPU_PPC_STB01010  = xxx,
     #endif
     #if 0
         CPU_PPC_STB0210   = xxx,
     #endif
         CPU_PPC_STB03     = 0x40310000,
     #if 0
         CPU_PPC_STB043    = xxx,
     #endif
     #if 0
         CPU_PPC_STB045    = xxx,
     #endif
         CPU_PPC_STB25     = 0x51510950,
     #if 0
         CPU_PPC_STB130    = xxx,
     #endif
         /* Xilinx cores */
         CPU_PPC_X2VP4     = 0x20010820,
     #define CPU_PPC_X2VP7 CPU_PPC_X2VP4
         CPU_PPC_X2VP20    = 0x20010860,
     #define CPU_PPC_X2VP50 CPU_PPC_X2VP20
         /* PowerPC 440 cores */
         CPU_PPC_440EP     = 0x422218D3,
     #define CPU_PPC_440GR CPU_PPC_440EP
         CPU_PPC_440GP     = 0x40120481,
     #if 0
         CPU_PPC_440GRX    = xxx,
     #endif
         CPU_PPC_440GX     = 0x51B21850,
         CPU_PPC_440GXc    = 0x51B21892,
         CPU_PPC_440GXf    = 0x51B21894,
         CPU_PPC_440SP     = 0x53221850,
         CPU_PPC_440SP2    = 0x53221891,
         CPU_PPC_440SPE    = 0x53421890,
         /* PowerPC 460 cores */
     #if 0
         CPU_PPC_464H90    = xxx,
     #endif
     #if 0
         CPU_PPC_464H90FP  = xxx,
     #endif
         /* PowerPC MPC 5xx cores */
         CPU_PPC_5xx       = 0x00020020,
         /* PowerPC MPC 8xx cores (aka PowerQUICC) */
         CPU_PPC_8xx       = 0x00500000,
         /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
         CPU_PPC_82xx_HIP3 = 0x00810101,
         CPU_PPC_82xx_HIP4 = 0x80811014,
         CPU_PPC_827x      = 0x80822013,
         /* eCores */
         CPU_PPC_e200      = 0x81120000,
         CPU_PPC_e500v110  = 0x80200010,
         CPU_PPC_e500v120  = 0x80200020,
         CPU_PPC_e500v210  = 0x80210010,
         CPU_PPC_e500v220  = 0x80210020,
     #define CPU_PPC_e500 CPU_PPC_e500v220
         CPU_PPC_e600      = 0x80040010,
         /* PowerPC 6xx cores */
         CPU_PPC_601       = 0x00010001,
         CPU_PPC_602       = 0x00050100,
         CPU_PPC_603       = 0x00030100,
         CPU_PPC_603E      = 0x00060101,
         CPU_PPC_603P      = 0x00070000,
         CPU_PPC_603E7v    = 0x00070100,
         CPU_PPC_603E7v2   = 0x00070201,
         CPU_PPC_603E7     = 0x00070200,
         CPU_PPC_603R      = 0x00071201,
         CPU_PPC_G2        = 0x00810011,
         CPU_PPC_G2H4      = 0x80811010,
         CPU_PPC_G2gp      = 0x80821010,
         CPU_PPC_G2ls      = 0x90810010,
         CPU_PPC_G2LE      = 0x80820010,
         CPU_PPC_G2LEgp    = 0x80822010,
         CPU_PPC_G2LEls    = 0xA0822010,
         CPU_PPC_604       = 0x00040000,
         CPU_PPC_604E      = 0x00090100, /* Also 2110 & 2120 */
         CPU_PPC_604R      = 0x000a0101,
         /* PowerPC 74x/75x cores (aka G3) */
         CPU_PPC_74x       = 0x00080000,
         CPU_PPC_740E      = 0x00080100,
         CPU_PPC_74xP      = 0x10080000,
         CPU_PPC_750E      = 0x00080200,
         CPU_PPC_750CXE21  = 0x00082201,
         CPU_PPC_750CXE22  = 0x00082212,
         CPU_PPC_750CXE23  = 0x00082203,
         CPU_PPC_750CXE24  = 0x00082214,
         CPU_PPC_750CXE24b = 0x00083214,
         CPU_PPC_750CXE31  = 0x00083211,
         CPU_PPC_750CXE31b = 0x00083311,
     #define CPU_PPC_750CXE CPU_PPC_750CXE31b
         CPU_PPC_750CXR    = 0x00083410,
         CPU_PPC_750FX10   = 0x70000100,
         CPU_PPC_750FX20   = 0x70000200,
         CPU_PPC_750FX21   = 0x70000201,
         CPU_PPC_750FX22   = 0x70000202,
         CPU_PPC_750FX23   = 0x70000203,
     #define CPU_PPC_750FX CPU_PPC_750FX23
         CPU_PPC_750FL     = 0x700A0203,
         CPU_PPC_750GX10   = 0x70020100,
         CPU_PPC_750GX11   = 0x70020101,
         CPU_PPC_750GX12   = 0x70020102,
     #define CPU_PPC_750GX CPU_PPC_750GX12
         CPU_PPC_750GL     = 0x70020102,
         CPU_PPC_750L30    = 0x00088300,
         CPU_PPC_750L32    = 0x00088302,
     #define CPU_PPC_750L CPU_PPC_750L32
         CPU_PPC_750CL     = 0x00087200,
         CPU_PPC_755_10    = 0x00083100,
         CPU_PPC_755_11    = 0x00083101,
         CPU_PPC_755_20    = 0x00083200,
         CPU_PPC_755D      = 0x00083202,
         CPU_PPC_755E      = 0x00083203,
     #define CPU_PPC_755 CPU_PPC_755E
         /* PowerPC 74xx cores (aka G4) */
         CPU_PPC_7400      = 0x000C0100,
         CPU_PPC_7410C     = 0x800C1102,
         CPU_PPC_7410D     = 0x800C1103,
         CPU_PPC_7410E     = 0x800C1104,
     #define CPU_PPC_7410 CPU_PPC_7410E
         CPU_PPC_7441      = 0x80000210,
         CPU_PPC_7445      = 0x80010100,
         CPU_PPC_7447      = 0x80020100,
         CPU_PPC_7447A     = 0x80030101,
         CPU_PPC_7448      = 0x80040100,
         CPU_PPC_7450      = 0x80000200,
         CPU_PPC_7450b     = 0x80000201,
         CPU_PPC_7451      = 0x80000203,
         CPU_PPC_7451G     = 0x80000210,
         CPU_PPC_7455      = 0x80010201,
         CPU_PPC_7455F     = 0x80010303,
         CPU_PPC_7455G     = 0x80010304,
         CPU_PPC_7457      = 0x80020101,
         CPU_PPC_7457C     = 0x80020102,
         CPU_PPC_7457A     = 0x80030000,
         /* 64 bits PowerPC */
         CPU_PPC_620       = 0x00140000,
         CPU_PPC_630       = 0x00400000,
         CPU_PPC_631       = 0x00410000,
         CPU_PPC_POWER4    = 0x00350000,
         CPU_PPC_POWER4P   = 0x00380000,
         CPU_PPC_POWER5    = 0x003A0000,
         CPU_PPC_POWER5P   = 0x003B0000,
     #if 0
         CPU_PPC_POWER6    = xxx,
     #endif
         CPU_PPC_970       = 0x00390000,
         CPU_PPC_970FX10   = 0x00391100,
         CPU_PPC_970FX20   = 0x003C0200,
         CPU_PPC_970FX21   = 0x003C0201,
         CPU_PPC_970FX30   = 0x003C0300,
         CPU_PPC_970FX31   = 0x003C0301,
     #define CPU_PPC_970FX CPU_PPC_970FX31
         CPU_PPC_970MP10   = 0x00440100,
         CPU_PPC_970MP11   = 0x00440101,
     #define CPU_PPC_970MP CPU_PPC_970MP11
         CPU_PPC_CELL10    = 0x00700100,
         CPU_PPC_CELL20    = 0x00700400,
         CPU_PPC_CELL30    = 0x00700500,
         CPU_PPC_CELL31    = 0x00700501,
     #define CPU_PPC_CELL32 CPU_PPC_CELL31
     #define CPU_PPC_CELL CPU_PPC_CELL32
         CPU_PPC_RS64      = 0x00330000,
         CPU_PPC_RS64II    = 0x00340000,
         CPU_PPC_RS64III   = 0x00360000,
         CPU_PPC_RS64IV    = 0x00370000,
         /* Original POWER */
         /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
          * POWER2 (RIOS2) & RSC2 (P2SC) here
          */
     #if 0
         CPU_POWER         = xxx,
     #endif
     #if 0
         CPU_POWER2        = xxx,
     #endif
     };
     /* System version register (used on MPC 8xxx) */
     enum {
         PPC_SVR_8540      = 0x80300000,
         PPC_SVR_8541E     = 0x807A0010,
         PPC_SVR_8543v10   = 0x80320010,
         PPC_SVR_8543v11   = 0x80320011,
         PPC_SVR_8543v20   = 0x80320020,
         PPC_SVR_8543Ev10  = 0x803A0010,
         PPC_SVR_8543Ev11  = 0x803A0011,
         PPC_SVR_8543Ev20  = 0x803A0020,
         PPC_SVR_8545      = 0x80310220,
         PPC_SVR_8545E     = 0x80390220,
         PPC_SVR_8547E     = 0x80390120,
         PPC_SCR_8548v10   = 0x80310010,
         PPC_SCR_8548v11   = 0x80310011,
         PPC_SCR_8548v20   = 0x80310020,
         PPC_SVR_8548Ev10  = 0x80390010,
         PPC_SVR_8548Ev11  = 0x80390011,
         PPC_SVR_8548Ev20  = 0x80390020,
         PPC_SVR_8555E     = 0x80790010,
         PPC_SVR_8560v10   = 0x80700010,
         PPC_SVR_8560v20   = 0x80700020,
         POWERPC_MMU_UNKNOWN    = 0,
         /* Standard 32 bits PowerPC MMU                            */
         POWERPC_MMU_32B,
         /* Standard 64 bits PowerPC MMU                            */
         POWERPC_MMU_64B,
         /* PowerPC 601 MMU                                         */
         POWERPC_MMU_601,
         /* PowerPC 6xx MMU with software TLB                       */
         POWERPC_MMU_SOFT_6xx,
         /* PowerPC 74xx MMU with software TLB                      */
         POWERPC_MMU_SOFT_74xx,
         /* PowerPC 4xx MMU with software TLB                       */
         POWERPC_MMU_SOFT_4xx,
         /* PowerPC 4xx MMU with software TLB and zones protections */
         POWERPC_MMU_SOFT_4xx_Z,
         /* PowerPC 4xx MMU in real mode only                       */
         POWERPC_MMU_REAL_4xx,
         /* BookE MMU model                                         */
         POWERPC_MMU_BOOKE,
         /* BookE FSL MMU model                                     */
         POWERPC_MMU_BOOKE_FSL,
         /* 64 bits "bridge" PowerPC MMU                            */
         POWERPC_MMU_64BRIDGE,
     };
     /*****************************************************************************/
     /* Instruction types */
     enum {
         PPC_NONE        = 0x00000000,
         /* integer operations instructions             */
         /* flow control instructions                   */
         /* virtual memory instructions                 */
         /* ld/st with reservation instructions         */
         /* cache control instructions                  */
         /* spr/msr access instructions                 */
         PPC_INSNS_BASE  = 0x0000000000000001ULL,
     #define PPC_INTEGER PPC_INSNS_BASE
     #define PPC_FLOW    PPC_INSNS_BASE
     #define PPC_MEM     PPC_INSNS_BASE
     #define PPC_RES     PPC_INSNS_BASE
     #define PPC_CACHE   PPC_INSNS_BASE
     #define PPC_MISC    PPC_INSNS_BASE
         /* floating point operations instructions      */
         PPC_FLOAT       = 0x0000000000000002ULL,
         /* more floating point operations instructions */
         PPC_FLOAT_EXT   = 0x0000000000000004ULL,
         /* external control instructions               */
         PPC_EXTERN      = 0x0000000000000008ULL,
         /* segment register access instructions        */
         PPC_SEGMENT     = 0x0000000000000010ULL,
         /* Optional cache control instructions         */
         PPC_CACHE_OPT   = 0x0000000000000020ULL,
         /* Optional floating point op instructions     */
         PPC_FLOAT_OPT   = 0x0000000000000040ULL,
         /* Optional memory control instructions        */
         PPC_MEM_TLBIA   = 0x0000000000000080ULL,
         PPC_MEM_TLBIE   = 0x0000000000000100ULL,
         PPC_MEM_TLBSYNC = 0x0000000000000200ULL,
         /* eieio & sync                                */
         PPC_MEM_SYNC    = 0x0000000000000400ULL,
         /* PowerPC 6xx TLB management instructions     */
         PPC_6xx_TLB     = 0x0000000000000800ULL,
         /* Altivec support                             */
         PPC_ALTIVEC     = 0x0000000000001000ULL,
         /* Time base support                           */
         PPC_TB          = 0x0000000000002000ULL,
         /* Embedded PowerPC dedicated instructions     */
         PPC_EMB_COMMON  = 0x0000000000004000ULL,
         /* PowerPC 40x exception model                 */
         PPC_40x_EXCP    = 0x0000000000008000ULL,
         /* PowerPC 40x specific instructions           */
         PPC_40x_SPEC    = 0x0000000000010000ULL,
         /* PowerPC 405 Mac instructions                */
         PPC_405_MAC     = 0x0000000000020000ULL,
         /* PowerPC 440 specific instructions           */
         PPC_440_SPEC    = 0x0000000000040000ULL,
         /* Specific extensions */
         /* Power-to-PowerPC bridge (601)               */
         PPC_POWER_BR    = 0x0000000000080000ULL,
         /* PowerPC 602 specific */
         PPC_602_SPEC    = 0x0000000000100000ULL,
         /* Deprecated instructions                     */
         /* Original POWER instruction set              */
         PPC_POWER       = 0x0000000000200000ULL,
         /* POWER2 instruction set extension            */
         PPC_POWER2      = 0x0000000000400000ULL,
         /* Power RTC support */
         PPC_POWER_RTC   = 0x0000000000800000ULL,
         /* 64 bits PowerPC instructions                */
         /* 64 bits PowerPC instruction set             */
         PPC_64B         = 0x0000000001000000ULL,
         /* 64 bits hypervisor extensions               */
         PPC_64H         = 0x0000000002000000ULL,
         /* 64 bits PowerPC "bridge" features           */
         PPC_64_BRIDGE   = 0x0000000004000000ULL,
         /* BookE (embedded) PowerPC specification      */
         PPC_BOOKE       = 0x0000000008000000ULL,
         /* eieio                                       */
         PPC_MEM_EIEIO   = 0x0000000010000000ULL,
         /* e500 vector instructions                    */
         PPC_E500_VECTOR = 0x0000000020000000ULL,
         /* PowerPC 4xx dedicated instructions          */
         PPC_4xx_COMMON  = 0x0000000040000000ULL,
         /* PowerPC 2.03 specification extensions       */
         PPC_203         = 0x0000000080000000ULL,
         /* PowerPC 2.03 SPE extension                  */
         PPC_SPE         = 0x0000000100000000ULL,
         /* PowerPC 2.03 SPE floating-point extension   */
         PPC_SPEFPU      = 0x0000000200000000ULL,
         /* SLB management                              */
         PPC_SLBI        = 0x0000000400000000ULL,
         /* PowerPC 40x ibct instructions               */
         PPC_40x_ICBT    = 0x0000000800000000ULL,
     };
     /* CPU run-time flags (MMU and exception model) */
     /* Exception model                                                           */
     enum {
         /* MMU model                         */
         PPC_FLAGS_MMU_MASK       = 0x000000FF,
         /* Standard 32 bits PowerPC MMU      */
         PPC_FLAGS_MMU_32B        = 0x00000000,
         /* Standard 64 bits PowerPC MMU      */
         PPC_FLAGS_MMU_64B        = 0x00000001,
         /* PowerPC 601 MMU                   */
         PPC_FLAGS_MMU_601        = 0x00000002,
         /* PowerPC 6xx MMU with software TLB */
         PPC_FLAGS_MMU_SOFT_6xx   = 0x00000003,
         /* PowerPC 4xx MMU with software TLB */
         PPC_FLAGS_MMU_SOFT_4xx   = 0x00000004,
         /* PowerPC 403 MMU                  */
         PPC_FLAGS_MMU_403        = 0x00000005,
         /* BookE FSL MMU model              */
         PPC_FLAGS_MMU_BOOKE_FSL  = 0x00000006,
         /* BookE MMU model                  */
         PPC_FLAGS_MMU_BOOKE      = 0x00000007,
         /* 64 bits "bridge" PowerPC MMU     */
         PPC_FLAGS_MMU_64BRIDGE   = 0x00000008,
         /* PowerPC 401 MMU (real mode only) */
         PPC_FLAGS_MMU_401        = 0x00000009,
         /* Exception model                  */
         PPC_FLAGS_EXCP_MASK      = 0x0000FF00,
         POWERPC_EXCP_UNKNOWN   = 0,
         /* Standard PowerPC exception model */
         PPC_FLAGS_EXCP_STD       = 0x00000000,
         POWERPC_EXCP_STD,
         /* PowerPC 40x exception model      */
         PPC_FLAGS_EXCP_40x       = 0x00000100,
         POWERPC_EXCP_40x,
         /* PowerPC 601 exception model      */
         PPC_FLAGS_EXCP_601       = 0x00000200,
         POWERPC_EXCP_601,
         /* PowerPC 602 exception model      */
         PPC_FLAGS_EXCP_602       = 0x00000300,
         POWERPC_EXCP_602,
         /* PowerPC 603 exception model      */
         PPC_FLAGS_EXCP_603       = 0x00000400,
         POWERPC_EXCP_603,
         /* PowerPC 603e exception model     */
         POWERPC_EXCP_603E,
         /* PowerPC G2 exception model       */
         POWERPC_EXCP_G2,
         /* PowerPC 604 exception model      */
         PPC_FLAGS_EXCP_604       = 0x00000500,
         POWERPC_EXCP_604,
         /* PowerPC 7x0 exception model      */
         PPC_FLAGS_EXCP_7x0       = 0x00000600,
         POWERPC_EXCP_7x0,
         /* PowerPC 7x5 exception model      */
         PPC_FLAGS_EXCP_7x5       = 0x00000700,
         POWERPC_EXCP_7x5,
         /* PowerPC 74xx exception model     */
         PPC_FLAGS_EXCP_74xx      = 0x00000800,
         POWERPC_EXCP_74xx,
         /* PowerPC 970 exception model      */
         PPC_FLAGS_EXCP_970       = 0x00000900,
         POWERPC_EXCP_970,
         /* BookE exception model            */
         PPC_FLAGS_EXCP_BOOKE     = 0x00000A00,
         /* Input pins model                 */
         PPC_FLAGS_INPUT_MASK     = 0x000F0000,
         POWERPC_EXCP_BOOKE,
     };
     /*****************************************************************************/
     /* Input pins model                                                          */
     enum {
         PPC_FLAGS_INPUT_UNKNOWN = 0,
         /* PowerPC 6xx bus                  */
         PPC_FLAGS_INPUT_6xx      = 0x00000000,
         PPC_FLAGS_INPUT_6xx,
         /* BookE bus                        */
         PPC_FLAGS_INPUT_BookE    = 0x00010000,
         /* PowerPC 4xx bus                  */
         PPC_FLAGS_INPUT_40x      = 0x00020000,
         PPC_FLAGS_INPUT_BookE,
         /* PowerPC 405 bus                  */
         PPC_FLAGS_INPUT_405,
         /* PowerPC 970 bus                  */
         PPC_FLAGS_INPUT_970      = 0x00030000,
         PPC_FLAGS_INPUT_970,
         /* PowerPC 401 bus                  */
         PPC_FLAGS_INPUT_401,
     };
     #define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
     #define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
     #define PPC_INPUT(env) (env->flags & PPC_FLAGS_INPUT_MASK)
     #define PPC_INPUT(env) (env->bus_model)
     /*****************************************************************************/
     /* Supported instruction set definitions */
     /* This generates an empty opcode table... */
     #define PPC_INSNS_TODO (PPC_NONE)
     #define PPC_FLAGS_TODO (0x00000000)
     /* PowerPC 40x instruction set */
     #define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON)
     /* PowerPC 401 */
     #define PPC_INSNS_401 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO |         \
                            PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
     #define PPC_FLAGS_401 (PPC_FLAGS_MMU_401 | PPC_FLAGS_EXCP_40x |               \
                            PPC_FLAGS_INPUT_40x)
     /* PowerPC 403 */
     #define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO |         \
                            PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_4xx_COMMON |     \
                            PPC_40x_EXCP | PPC_40x_SPEC | PPC_40x_ICBT)
     #define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x |               \
                            PPC_FLAGS_INPUT_40x)
     /* PowerPC 405 */
     #define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO |         \
                            PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |      \
                            PPC_TB | PPC_4xx_COMMON | PPC_40x_SPEC |               \
                            PPC_40x_ICBT | PPC_40x_EXCP | PPC_405_MAC)
     #define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x |          \
                            PPC_FLAGS_INPUT_40x)
     /* PowerPC 440 */
     #define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE |            \
                            PPC_MEM_TLBSYNC | PPC_4xx_COMMON | PPC_405_MAC |       \
                            PPC_440_SPEC)
     #define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE |           \
                            PPC_FLAGS_INPUT_BookE)
     /* Generic BookE PowerPC */
     #define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_MEM_TLBSYNC | PPC_BOOKE |        \
                              PPC_MEM_EIEIO | PPC_FLOAT | PPC_FLOAT_OPT |          \
                              PPC_CACHE_OPT)
     #define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE |         \
                              PPC_FLAGS_INPUT_BookE)
     /* e500 core */
     #define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_MEM_TLBSYNC | PPC_BOOKE |         \
                             PPC_MEM_EIEIO | PPC_CACHE_OPT | PPC_E500_VECTOR)
     #define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x |         \
                             PPC_FLAGS_INPUT_BookE)
     /* Non-embedded PowerPC */
     #define PPC_INSNS_COMMON  (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC |        \
                                PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
     /* PowerPC 601 */
     #define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
     #define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601 |               \
                            PPC_FLAGS_INPUT_6xx)
     /* PowerPC 602 */
     #define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \
                            PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)
     #define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602 |          \
                            PPC_FLAGS_INPUT_6xx)
     /* PowerPC 603 */
     #define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \
                            PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
     #define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 |          \
                            PPC_FLAGS_INPUT_6xx)
     /* PowerPC G2 */
     #define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |        \
                           PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
     #define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 |           \
                           PPC_FLAGS_INPUT_6xx)
     /* PowerPC 604 */
     #define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
                            PPC_MEM_TLBSYNC | PPC_TB)
     #define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604 |               \
                            PPC_FLAGS_INPUT_6xx)
     /* PowerPC 740/750 (aka G3) */
     #define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
                            PPC_MEM_TLBSYNC | PPC_TB)
     #define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0 |               \
                            PPC_FLAGS_INPUT_6xx)
     /* PowerPC 745/755 */
     #define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
                            PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
     #define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5 |          \
                            PPC_FLAGS_INPUT_6xx)
     /* PowerPC 74xx (aka G4) */
     #define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC |      \
                             PPC_MEM_TLBSYNC | PPC_TB)
     #define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx |             \
                             PPC_FLAGS_INPUT_6xx)
     /* PowerPC 970 (aka G5) */
     #define PPC_INSNS_970  (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_FLOAT_OPT |    \
                             PPC_ALTIVEC | PPC_MEM_TLBSYNC | PPC_TB |              \
                             PPC_64B | PPC_64_BRIDGE | PPC_SLBI)
     #define PPC_FLAGS_970  (PPC_FLAGS_MMU_64BRIDGE | PPC_FLAGS_EXCP_970 |         \
                             PPC_FLAGS_INPUT_970)
     /* Default PowerPC will be 604/970 */
     #define PPC_INSNS_PPC32 PPC_INSNS_604
     #define PPC_FLAGS_PPC32 PPC_FLAGS_604
     #define PPC_INSNS_PPC64 PPC_INSNS_970
     #define PPC_FLAGS_PPC64 PPC_FLAGS_970
     #define PPC_INSNS_DEFAULT PPC_INSNS_604
     #define PPC_FLAGS_DEFAULT PPC_FLAGS_604
     typedef struct ppc_def_t ppc_def_t;
     typedef struct opc_handler_t opc_handler_t;
     /*****************************************************************************/
     /* Types used to describe some PowerPC registers */
     typedef struct CPUPPCState CPUPPCState;
     typedef struct opc_handler_t opc_handler_t;
     typedef struct ppc_tb_t ppc_tb_t;
     typedef struct ppc_spr_t ppc_spr_t;
     typedef struct ppc_dcr_t ppc_dcr_t;
-...
         /* Those resources are used during exception processing */
         /* CPU model definition */
         uint64_t msr_mask;
         target_ulong msr_mask;
         uint8_t mmu_model;
         uint8_t excp_model;
         uint8_t bus_model;
         uint8_t pad;
         uint32_t flags;
         int exception_index;
-...
     #define SPR_LR           (0x008)
     #define SPR_CTR          (0x009)
     #define SPR_DSISR        (0x012)
     #define SPR_DAR          (0x013)
     #define SPR_DAR          (0x013) /* DAE for PowerPC 601 */
     #define SPR_601_RTCU     (0x014)
     #define SPR_601_RTCL     (0x015)
     #define SPR_DECR         (0x016)
-...
     #define SPR_440_ITV1     (0x375)
     #define SPR_440_ITV2     (0x376)
     #define SPR_440_ITV3     (0x377)
     #define SPR_440_CCR1     (0x378)
     #define SPR_DCRIPR       (0x37B)
     #define SPR_PPR          (0x380)
     #define SPR_440_DNV0     (0x390)
     #define SPR_440_DNV1     (0x391)
-...
     #define SPR_BOOKE_DCDBTRH (0x39D)
     #define SPR_BOOKE_ICDBTRL (0x39E)
     #define SPR_BOOKE_ICDBTRH (0x39F)
     #define SPR_UMMCR2       (0x3A0)
     #define SPR_UPMC5        (0x3A1)
     #define SPR_UPMC6        (0x3A2)
     #define SPR_UBAMR        (0x3A7)
     #define SPR_UMMCR0       (0x3A8)
     #define SPR_UPMC1        (0x3A9)
     #define SPR_UPMC2        (0x3AA)
     #define SPR_USIA         (0x3AB)
     #define SPR_USIAR        (0x3AB)
     #define SPR_UMMCR1       (0x3AC)
     #define SPR_UPMC3        (0x3AD)
     #define SPR_UPMC4        (0x3AE)
     #define SPR_USDA         (0x3AF)
     #define SPR_40x_ZPR      (0x3B0)
     #define SPR_BOOKE_MAS7   (0x3B0)
     #define SPR_620_PMR0     (0x3B0)
     #define SPR_MMCR2        (0x3B0)
     #define SPR_PMC5         (0x3B1)
     #define SPR_40x_PID      (0x3B1)
     #define SPR_620_PMR1     (0x3B1)
     #define SPR_PMC6         (0x3B2)
     #define SPR_440_MMUCR    (0x3B2)
     #define SPR_620_PMR2     (0x3B2)
     #define SPR_4xx_CCR0     (0x3B3)
     #define SPR_BOOKE_EPLC   (0x3B3)
     #define SPR_620_PMR3     (0x3B3)
     #define SPR_405_IAC3     (0x3B4)
     #define SPR_BOOKE_EPSC   (0x3B4)
     #define SPR_620_PMR4     (0x3B4)
     #define SPR_405_IAC4     (0x3B5)
     #define SPR_620_PMR5     (0x3B5)
     #define SPR_405_DVC1     (0x3B6)
     #define SPR_620_PMR6     (0x3B6)
     #define SPR_405_DVC2     (0x3B7)
     #define SPR_620_PMR7     (0x3B7)
     #define SPR_BAMR         (0x3B7)
     #define SPR_MMCR0        (0x3B8)
     #define SPR_620_PMR8     (0x3B8)
     #define SPR_PMC1         (0x3B9)
     #define SPR_40x_SGR      (0x3B9)
     #define SPR_620_PMR9     (0x3B9)
     #define SPR_PMC2         (0x3BA)
     #define SPR_40x_DCWR     (0x3BA)
     #define SPR_SIA          (0x3BB)
     #define SPR_620_PMRA     (0x3BA)
     #define SPR_SIAR         (0x3BB)
     #define SPR_405_SLER     (0x3BB)
     #define SPR_620_PMRB     (0x3BB)
     #define SPR_MMCR1        (0x3BC)
     #define SPR_405_SU0R     (0x3BC)
     #define SPR_620_PMRC     (0x3BC)
     #define SPR_401_SKR      (0x3BC)
     #define SPR_PMC3         (0x3BD)
     #define SPR_405_DBCR1    (0x3BD)
     #define SPR_620_PMRD     (0x3BD)
     #define SPR_PMC4         (0x3BE)
     #define SPR_620_PMRE     (0x3BE)
     #define SPR_SDA          (0x3BF)
     #define SPR_620_PMRF     (0x3BF)
     #define SPR_403_VTBL     (0x3CC)
     #define SPR_403_VTBU     (0x3CD)
     #define SPR_DMISS        (0x3D0)
-...
     #define SPR_HASH1        (0x3D2)
     #define SPR_HASH2        (0x3D3)
     #define SPR_BOOKE_ICDBDR (0x3D3)
     #define SPR_TLBMISS      (0x3D4)
     #define SPR_IMISS        (0x3D4)
     #define SPR_40x_ESR      (0x3D4)
     #define SPR_PTEHI        (0x3D5)
     #define SPR_ICMP         (0x3D5)
     #define SPR_40x_DEAR     (0x3D5)
     #define SPR_PTELO        (0x3D6)
     #define SPR_RPA          (0x3D6)
     #define SPR_40x_EVPR     (0x3D6)
     #define SPR_L3PM         (0x3D7)
     #define SPR_403_CDBCR    (0x3D7)
     #define SPR_L3OHCR       (0x3D8)
     #define SPR_TCR          (0x3D8)
     #define SPR_40x_TSR      (0x3D8)
     #define SPR_IBR          (0x3DA)
     #define SPR_40x_TCR      (0x3DA)
     #define SPR_ESASR        (0x3DB)
     #define SPR_ESASRR       (0x3DB)

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Archipelago » qemu

Revision a750fc0b