Revision a750fc0b target-ppc/cpu.h
| b/target-ppc/cpu.h | ||
|---|---|---|
| 89 | 89 |
#define DCACHE_LINE_SIZE 32 |
| 90 | 90 |
|
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/*****************************************************************************/ |
| 92 |
/* PVR definitions for most known PowerPC */
|
|
| 92 |
/* MMU model */
|
|
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enum {
|
| 94 |
/* PowerPC 401 cores */ |
|
| 95 |
CPU_PPC_401A1 = 0x00210000, |
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| 96 |
CPU_PPC_401B2 = 0x00220000, |
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| 97 |
#if 0 |
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CPU_PPC_401B3 = xxx, |
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#endif |
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CPU_PPC_401C2 = 0x00230000, |
|
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CPU_PPC_401D2 = 0x00240000, |
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CPU_PPC_401E2 = 0x00250000, |
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CPU_PPC_401F2 = 0x00260000, |
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CPU_PPC_401G2 = 0x00270000, |
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#if 0 |
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CPU_PPC_401GF = xxx, |
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#endif |
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#define CPU_PPC_401 CPU_PPC_401G2 |
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CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */ |
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CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */ |
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/* PowerPC 403 cores */ |
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CPU_PPC_403GA = 0x00200011, |
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CPU_PPC_403GB = 0x00200100, |
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CPU_PPC_403GC = 0x00200200, |
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CPU_PPC_403GCX = 0x00201400, |
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#if 0 |
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CPU_PPC_403GP = xxx, |
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#endif |
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#define CPU_PPC_403 CPU_PPC_403GCX |
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/* PowerPC 405 cores */ |
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#if 0 |
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CPU_PPC_405A3 = xxx, |
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#endif |
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#if 0 |
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CPU_PPC_405A4 = xxx, |
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#endif |
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#if 0 |
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CPU_PPC_405B3 = xxx, |
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#endif |
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CPU_PPC_405D2 = 0x20010000, |
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CPU_PPC_405D4 = 0x41810000, |
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CPU_PPC_405CR = 0x40110145, |
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#define CPU_PPC_405GP CPU_PPC_405CR |
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CPU_PPC_405EP = 0x51210950, |
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#if 0 |
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CPU_PPC_405EZ = xxx, |
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#endif |
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CPU_PPC_405GPR = 0x50910951, |
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#if 0 |
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CPU_PPC_405LP = xxx, |
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#endif |
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#define CPU_PPC_405 CPU_PPC_405D4 |
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CPU_PPC_NPE405H = 0x414100C0, |
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CPU_PPC_NPE405H2 = 0x41410140, |
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CPU_PPC_NPE405L = 0x416100C0, |
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#if 0 |
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CPU_PPC_LC77700 = xxx, |
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#endif |
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/* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */ |
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#if 0 |
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CPU_PPC_STB01000 = xxx, |
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#endif |
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#if 0 |
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CPU_PPC_STB01010 = xxx, |
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#endif |
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#if 0 |
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CPU_PPC_STB0210 = xxx, |
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#endif |
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CPU_PPC_STB03 = 0x40310000, |
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#if 0 |
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CPU_PPC_STB043 = xxx, |
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#endif |
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#if 0 |
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CPU_PPC_STB045 = xxx, |
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#endif |
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CPU_PPC_STB25 = 0x51510950, |
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#if 0 |
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CPU_PPC_STB130 = xxx, |
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#endif |
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/* Xilinx cores */ |
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CPU_PPC_X2VP4 = 0x20010820, |
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#define CPU_PPC_X2VP7 CPU_PPC_X2VP4 |
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CPU_PPC_X2VP20 = 0x20010860, |
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#define CPU_PPC_X2VP50 CPU_PPC_X2VP20 |
|
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/* PowerPC 440 cores */ |
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CPU_PPC_440EP = 0x422218D3, |
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#define CPU_PPC_440GR CPU_PPC_440EP |
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CPU_PPC_440GP = 0x40120481, |
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#if 0 |
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CPU_PPC_440GRX = xxx, |
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#endif |
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CPU_PPC_440GX = 0x51B21850, |
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CPU_PPC_440GXc = 0x51B21892, |
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CPU_PPC_440GXf = 0x51B21894, |
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CPU_PPC_440SP = 0x53221850, |
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CPU_PPC_440SP2 = 0x53221891, |
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CPU_PPC_440SPE = 0x53421890, |
|
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/* PowerPC 460 cores */ |
|
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#if 0 |
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CPU_PPC_464H90 = xxx, |
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#endif |
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#if 0 |
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CPU_PPC_464H90FP = xxx, |
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#endif |
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/* PowerPC MPC 5xx cores */ |
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CPU_PPC_5xx = 0x00020020, |
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/* PowerPC MPC 8xx cores (aka PowerQUICC) */ |
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CPU_PPC_8xx = 0x00500000, |
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/* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */ |
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CPU_PPC_82xx_HIP3 = 0x00810101, |
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CPU_PPC_82xx_HIP4 = 0x80811014, |
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CPU_PPC_827x = 0x80822013, |
|
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/* eCores */ |
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CPU_PPC_e200 = 0x81120000, |
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CPU_PPC_e500v110 = 0x80200010, |
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CPU_PPC_e500v120 = 0x80200020, |
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CPU_PPC_e500v210 = 0x80210010, |
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CPU_PPC_e500v220 = 0x80210020, |
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#define CPU_PPC_e500 CPU_PPC_e500v220 |
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CPU_PPC_e600 = 0x80040010, |
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/* PowerPC 6xx cores */ |
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CPU_PPC_601 = 0x00010001, |
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CPU_PPC_602 = 0x00050100, |
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CPU_PPC_603 = 0x00030100, |
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CPU_PPC_603E = 0x00060101, |
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CPU_PPC_603P = 0x00070000, |
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CPU_PPC_603E7v = 0x00070100, |
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| 218 |
CPU_PPC_603E7v2 = 0x00070201, |
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CPU_PPC_603E7 = 0x00070200, |
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CPU_PPC_603R = 0x00071201, |
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CPU_PPC_G2 = 0x00810011, |
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| 222 |
CPU_PPC_G2H4 = 0x80811010, |
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| 223 |
CPU_PPC_G2gp = 0x80821010, |
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| 224 |
CPU_PPC_G2ls = 0x90810010, |
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| 225 |
CPU_PPC_G2LE = 0x80820010, |
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| 226 |
CPU_PPC_G2LEgp = 0x80822010, |
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CPU_PPC_G2LEls = 0xA0822010, |
|
| 228 |
CPU_PPC_604 = 0x00040000, |
|
| 229 |
CPU_PPC_604E = 0x00090100, /* Also 2110 & 2120 */ |
|
| 230 |
CPU_PPC_604R = 0x000a0101, |
|
| 231 |
/* PowerPC 74x/75x cores (aka G3) */ |
|
| 232 |
CPU_PPC_74x = 0x00080000, |
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| 233 |
CPU_PPC_740E = 0x00080100, |
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| 234 |
CPU_PPC_74xP = 0x10080000, |
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| 235 |
CPU_PPC_750E = 0x00080200, |
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| 236 |
CPU_PPC_750CXE21 = 0x00082201, |
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CPU_PPC_750CXE22 = 0x00082212, |
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CPU_PPC_750CXE23 = 0x00082203, |
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CPU_PPC_750CXE24 = 0x00082214, |
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CPU_PPC_750CXE24b = 0x00083214, |
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| 241 |
CPU_PPC_750CXE31 = 0x00083211, |
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| 242 |
CPU_PPC_750CXE31b = 0x00083311, |
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| 243 |
#define CPU_PPC_750CXE CPU_PPC_750CXE31b |
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| 244 |
CPU_PPC_750CXR = 0x00083410, |
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| 245 |
CPU_PPC_750FX10 = 0x70000100, |
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CPU_PPC_750FX20 = 0x70000200, |
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CPU_PPC_750FX21 = 0x70000201, |
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CPU_PPC_750FX22 = 0x70000202, |
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CPU_PPC_750FX23 = 0x70000203, |
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#define CPU_PPC_750FX CPU_PPC_750FX23 |
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| 251 |
CPU_PPC_750FL = 0x700A0203, |
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CPU_PPC_750GX10 = 0x70020100, |
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CPU_PPC_750GX11 = 0x70020101, |
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CPU_PPC_750GX12 = 0x70020102, |
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#define CPU_PPC_750GX CPU_PPC_750GX12 |
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CPU_PPC_750GL = 0x70020102, |
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CPU_PPC_750L30 = 0x00088300, |
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CPU_PPC_750L32 = 0x00088302, |
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#define CPU_PPC_750L CPU_PPC_750L32 |
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CPU_PPC_750CL = 0x00087200, |
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CPU_PPC_755_10 = 0x00083100, |
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CPU_PPC_755_11 = 0x00083101, |
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CPU_PPC_755_20 = 0x00083200, |
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CPU_PPC_755D = 0x00083202, |
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CPU_PPC_755E = 0x00083203, |
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#define CPU_PPC_755 CPU_PPC_755E |
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| 267 |
/* PowerPC 74xx cores (aka G4) */ |
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CPU_PPC_7400 = 0x000C0100, |
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CPU_PPC_7410C = 0x800C1102, |
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CPU_PPC_7410D = 0x800C1103, |
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CPU_PPC_7410E = 0x800C1104, |
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#define CPU_PPC_7410 CPU_PPC_7410E |
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CPU_PPC_7441 = 0x80000210, |
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| 274 |
CPU_PPC_7445 = 0x80010100, |
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CPU_PPC_7447 = 0x80020100, |
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CPU_PPC_7447A = 0x80030101, |
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| 277 |
CPU_PPC_7448 = 0x80040100, |
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| 278 |
CPU_PPC_7450 = 0x80000200, |
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CPU_PPC_7450b = 0x80000201, |
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CPU_PPC_7451 = 0x80000203, |
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CPU_PPC_7451G = 0x80000210, |
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| 282 |
CPU_PPC_7455 = 0x80010201, |
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| 283 |
CPU_PPC_7455F = 0x80010303, |
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CPU_PPC_7455G = 0x80010304, |
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CPU_PPC_7457 = 0x80020101, |
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CPU_PPC_7457C = 0x80020102, |
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CPU_PPC_7457A = 0x80030000, |
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| 288 |
/* 64 bits PowerPC */ |
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CPU_PPC_620 = 0x00140000, |
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CPU_PPC_630 = 0x00400000, |
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| 291 |
CPU_PPC_631 = 0x00410000, |
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CPU_PPC_POWER4 = 0x00350000, |
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CPU_PPC_POWER4P = 0x00380000, |
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CPU_PPC_POWER5 = 0x003A0000, |
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CPU_PPC_POWER5P = 0x003B0000, |
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#if 0 |
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| 297 |
CPU_PPC_POWER6 = xxx, |
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#endif |
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| 299 |
CPU_PPC_970 = 0x00390000, |
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| 300 |
CPU_PPC_970FX10 = 0x00391100, |
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| 301 |
CPU_PPC_970FX20 = 0x003C0200, |
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CPU_PPC_970FX21 = 0x003C0201, |
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CPU_PPC_970FX30 = 0x003C0300, |
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CPU_PPC_970FX31 = 0x003C0301, |
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#define CPU_PPC_970FX CPU_PPC_970FX31 |
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| 306 |
CPU_PPC_970MP10 = 0x00440100, |
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CPU_PPC_970MP11 = 0x00440101, |
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| 308 |
#define CPU_PPC_970MP CPU_PPC_970MP11 |
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CPU_PPC_CELL10 = 0x00700100, |
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| 310 |
CPU_PPC_CELL20 = 0x00700400, |
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| 311 |
CPU_PPC_CELL30 = 0x00700500, |
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CPU_PPC_CELL31 = 0x00700501, |
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| 313 |
#define CPU_PPC_CELL32 CPU_PPC_CELL31 |
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| 314 |
#define CPU_PPC_CELL CPU_PPC_CELL32 |
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| 315 |
CPU_PPC_RS64 = 0x00330000, |
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| 316 |
CPU_PPC_RS64II = 0x00340000, |
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| 317 |
CPU_PPC_RS64III = 0x00360000, |
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| 318 |
CPU_PPC_RS64IV = 0x00370000, |
|
| 319 |
/* Original POWER */ |
|
| 320 |
/* XXX: should be POWER (RIOS), RSC3308, RSC4608, |
|
| 321 |
* POWER2 (RIOS2) & RSC2 (P2SC) here |
|
| 322 |
*/ |
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| 323 |
#if 0 |
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| 324 |
CPU_POWER = xxx, |
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| 325 |
#endif |
|
| 326 |
#if 0 |
|
| 327 |
CPU_POWER2 = xxx, |
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| 328 |
#endif |
|
| 329 |
}; |
|
| 330 |
|
|
| 331 |
/* System version register (used on MPC 8xxx) */ |
|
| 332 |
enum {
|
|
| 333 |
PPC_SVR_8540 = 0x80300000, |
|
| 334 |
PPC_SVR_8541E = 0x807A0010, |
|
| 335 |
PPC_SVR_8543v10 = 0x80320010, |
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| 336 |
PPC_SVR_8543v11 = 0x80320011, |
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| 337 |
PPC_SVR_8543v20 = 0x80320020, |
|
| 338 |
PPC_SVR_8543Ev10 = 0x803A0010, |
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| 339 |
PPC_SVR_8543Ev11 = 0x803A0011, |
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| 340 |
PPC_SVR_8543Ev20 = 0x803A0020, |
|
| 341 |
PPC_SVR_8545 = 0x80310220, |
|
| 342 |
PPC_SVR_8545E = 0x80390220, |
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| 343 |
PPC_SVR_8547E = 0x80390120, |
|
| 344 |
PPC_SCR_8548v10 = 0x80310010, |
|
| 345 |
PPC_SCR_8548v11 = 0x80310011, |
|
| 346 |
PPC_SCR_8548v20 = 0x80310020, |
|
| 347 |
PPC_SVR_8548Ev10 = 0x80390010, |
|
| 348 |
PPC_SVR_8548Ev11 = 0x80390011, |
|
| 349 |
PPC_SVR_8548Ev20 = 0x80390020, |
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| 350 |
PPC_SVR_8555E = 0x80790010, |
|
| 351 |
PPC_SVR_8560v10 = 0x80700010, |
|
| 352 |
PPC_SVR_8560v20 = 0x80700020, |
|
| 94 |
POWERPC_MMU_UNKNOWN = 0, |
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| 95 |
/* Standard 32 bits PowerPC MMU */ |
|
| 96 |
POWERPC_MMU_32B, |
|
| 97 |
/* Standard 64 bits PowerPC MMU */ |
|
| 98 |
POWERPC_MMU_64B, |
|
| 99 |
/* PowerPC 601 MMU */ |
|
| 100 |
POWERPC_MMU_601, |
|
| 101 |
/* PowerPC 6xx MMU with software TLB */ |
|
| 102 |
POWERPC_MMU_SOFT_6xx, |
|
| 103 |
/* PowerPC 74xx MMU with software TLB */ |
|
| 104 |
POWERPC_MMU_SOFT_74xx, |
|
| 105 |
/* PowerPC 4xx MMU with software TLB */ |
|
| 106 |
POWERPC_MMU_SOFT_4xx, |
|
| 107 |
/* PowerPC 4xx MMU with software TLB and zones protections */ |
|
| 108 |
POWERPC_MMU_SOFT_4xx_Z, |
|
| 109 |
/* PowerPC 4xx MMU in real mode only */ |
|
| 110 |
POWERPC_MMU_REAL_4xx, |
|
| 111 |
/* BookE MMU model */ |
|
| 112 |
POWERPC_MMU_BOOKE, |
|
| 113 |
/* BookE FSL MMU model */ |
|
| 114 |
POWERPC_MMU_BOOKE_FSL, |
|
| 115 |
/* 64 bits "bridge" PowerPC MMU */ |
|
| 116 |
POWERPC_MMU_64BRIDGE, |
|
| 353 | 117 |
}; |
| 354 | 118 |
|
| 355 | 119 |
/*****************************************************************************/ |
| 356 |
/* Instruction types */ |
|
| 357 |
enum {
|
|
| 358 |
PPC_NONE = 0x00000000, |
|
| 359 |
/* integer operations instructions */ |
|
| 360 |
/* flow control instructions */ |
|
| 361 |
/* virtual memory instructions */ |
|
| 362 |
/* ld/st with reservation instructions */ |
|
| 363 |
/* cache control instructions */ |
|
| 364 |
/* spr/msr access instructions */ |
|
| 365 |
PPC_INSNS_BASE = 0x0000000000000001ULL, |
|
| 366 |
#define PPC_INTEGER PPC_INSNS_BASE |
|
| 367 |
#define PPC_FLOW PPC_INSNS_BASE |
|
| 368 |
#define PPC_MEM PPC_INSNS_BASE |
|
| 369 |
#define PPC_RES PPC_INSNS_BASE |
|
| 370 |
#define PPC_CACHE PPC_INSNS_BASE |
|
| 371 |
#define PPC_MISC PPC_INSNS_BASE |
|
| 372 |
/* floating point operations instructions */ |
|
| 373 |
PPC_FLOAT = 0x0000000000000002ULL, |
|
| 374 |
/* more floating point operations instructions */ |
|
| 375 |
PPC_FLOAT_EXT = 0x0000000000000004ULL, |
|
| 376 |
/* external control instructions */ |
|
| 377 |
PPC_EXTERN = 0x0000000000000008ULL, |
|
| 378 |
/* segment register access instructions */ |
|
| 379 |
PPC_SEGMENT = 0x0000000000000010ULL, |
|
| 380 |
/* Optional cache control instructions */ |
|
| 381 |
PPC_CACHE_OPT = 0x0000000000000020ULL, |
|
| 382 |
/* Optional floating point op instructions */ |
|
| 383 |
PPC_FLOAT_OPT = 0x0000000000000040ULL, |
|
| 384 |
/* Optional memory control instructions */ |
|
| 385 |
PPC_MEM_TLBIA = 0x0000000000000080ULL, |
|
| 386 |
PPC_MEM_TLBIE = 0x0000000000000100ULL, |
|
| 387 |
PPC_MEM_TLBSYNC = 0x0000000000000200ULL, |
|
| 388 |
/* eieio & sync */ |
|
| 389 |
PPC_MEM_SYNC = 0x0000000000000400ULL, |
|
| 390 |
/* PowerPC 6xx TLB management instructions */ |
|
| 391 |
PPC_6xx_TLB = 0x0000000000000800ULL, |
|
| 392 |
/* Altivec support */ |
|
| 393 |
PPC_ALTIVEC = 0x0000000000001000ULL, |
|
| 394 |
/* Time base support */ |
|
| 395 |
PPC_TB = 0x0000000000002000ULL, |
|
| 396 |
/* Embedded PowerPC dedicated instructions */ |
|
| 397 |
PPC_EMB_COMMON = 0x0000000000004000ULL, |
|
| 398 |
/* PowerPC 40x exception model */ |
|
| 399 |
PPC_40x_EXCP = 0x0000000000008000ULL, |
|
| 400 |
/* PowerPC 40x specific instructions */ |
|
| 401 |
PPC_40x_SPEC = 0x0000000000010000ULL, |
|
| 402 |
/* PowerPC 405 Mac instructions */ |
|
| 403 |
PPC_405_MAC = 0x0000000000020000ULL, |
|
| 404 |
/* PowerPC 440 specific instructions */ |
|
| 405 |
PPC_440_SPEC = 0x0000000000040000ULL, |
|
| 406 |
/* Specific extensions */ |
|
| 407 |
/* Power-to-PowerPC bridge (601) */ |
|
| 408 |
PPC_POWER_BR = 0x0000000000080000ULL, |
|
| 409 |
/* PowerPC 602 specific */ |
|
| 410 |
PPC_602_SPEC = 0x0000000000100000ULL, |
|
| 411 |
/* Deprecated instructions */ |
|
| 412 |
/* Original POWER instruction set */ |
|
| 413 |
PPC_POWER = 0x0000000000200000ULL, |
|
| 414 |
/* POWER2 instruction set extension */ |
|
| 415 |
PPC_POWER2 = 0x0000000000400000ULL, |
|
| 416 |
/* Power RTC support */ |
|
| 417 |
PPC_POWER_RTC = 0x0000000000800000ULL, |
|
| 418 |
/* 64 bits PowerPC instructions */ |
|
| 419 |
/* 64 bits PowerPC instruction set */ |
|
| 420 |
PPC_64B = 0x0000000001000000ULL, |
|
| 421 |
/* 64 bits hypervisor extensions */ |
|
| 422 |
PPC_64H = 0x0000000002000000ULL, |
|
| 423 |
/* 64 bits PowerPC "bridge" features */ |
|
| 424 |
PPC_64_BRIDGE = 0x0000000004000000ULL, |
|
| 425 |
/* BookE (embedded) PowerPC specification */ |
|
| 426 |
PPC_BOOKE = 0x0000000008000000ULL, |
|
| 427 |
/* eieio */ |
|
| 428 |
PPC_MEM_EIEIO = 0x0000000010000000ULL, |
|
| 429 |
/* e500 vector instructions */ |
|
| 430 |
PPC_E500_VECTOR = 0x0000000020000000ULL, |
|
| 431 |
/* PowerPC 4xx dedicated instructions */ |
|
| 432 |
PPC_4xx_COMMON = 0x0000000040000000ULL, |
|
| 433 |
/* PowerPC 2.03 specification extensions */ |
|
| 434 |
PPC_203 = 0x0000000080000000ULL, |
|
| 435 |
/* PowerPC 2.03 SPE extension */ |
|
| 436 |
PPC_SPE = 0x0000000100000000ULL, |
|
| 437 |
/* PowerPC 2.03 SPE floating-point extension */ |
|
| 438 |
PPC_SPEFPU = 0x0000000200000000ULL, |
|
| 439 |
/* SLB management */ |
|
| 440 |
PPC_SLBI = 0x0000000400000000ULL, |
|
| 441 |
/* PowerPC 40x ibct instructions */ |
|
| 442 |
PPC_40x_ICBT = 0x0000000800000000ULL, |
|
| 443 |
}; |
|
| 444 |
|
|
| 445 |
/* CPU run-time flags (MMU and exception model) */ |
|
| 120 |
/* Exception model */ |
|
| 446 | 121 |
enum {
|
| 447 |
/* MMU model */ |
|
| 448 |
PPC_FLAGS_MMU_MASK = 0x000000FF, |
|
| 449 |
/* Standard 32 bits PowerPC MMU */ |
|
| 450 |
PPC_FLAGS_MMU_32B = 0x00000000, |
|
| 451 |
/* Standard 64 bits PowerPC MMU */ |
|
| 452 |
PPC_FLAGS_MMU_64B = 0x00000001, |
|
| 453 |
/* PowerPC 601 MMU */ |
|
| 454 |
PPC_FLAGS_MMU_601 = 0x00000002, |
|
| 455 |
/* PowerPC 6xx MMU with software TLB */ |
|
| 456 |
PPC_FLAGS_MMU_SOFT_6xx = 0x00000003, |
|
| 457 |
/* PowerPC 4xx MMU with software TLB */ |
|
| 458 |
PPC_FLAGS_MMU_SOFT_4xx = 0x00000004, |
|
| 459 |
/* PowerPC 403 MMU */ |
|
| 460 |
PPC_FLAGS_MMU_403 = 0x00000005, |
|
| 461 |
/* BookE FSL MMU model */ |
|
| 462 |
PPC_FLAGS_MMU_BOOKE_FSL = 0x00000006, |
|
| 463 |
/* BookE MMU model */ |
|
| 464 |
PPC_FLAGS_MMU_BOOKE = 0x00000007, |
|
| 465 |
/* 64 bits "bridge" PowerPC MMU */ |
|
| 466 |
PPC_FLAGS_MMU_64BRIDGE = 0x00000008, |
|
| 467 |
/* PowerPC 401 MMU (real mode only) */ |
|
| 468 |
PPC_FLAGS_MMU_401 = 0x00000009, |
|
| 469 |
/* Exception model */ |
|
| 470 |
PPC_FLAGS_EXCP_MASK = 0x0000FF00, |
|
| 122 |
POWERPC_EXCP_UNKNOWN = 0, |
|
| 471 | 123 |
/* Standard PowerPC exception model */ |
| 472 |
PPC_FLAGS_EXCP_STD = 0x00000000,
|
|
| 124 |
POWERPC_EXCP_STD,
|
|
| 473 | 125 |
/* PowerPC 40x exception model */ |
| 474 |
PPC_FLAGS_EXCP_40x = 0x00000100,
|
|
| 126 |
POWERPC_EXCP_40x,
|
|
| 475 | 127 |
/* PowerPC 601 exception model */ |
| 476 |
PPC_FLAGS_EXCP_601 = 0x00000200,
|
|
| 128 |
POWERPC_EXCP_601,
|
|
| 477 | 129 |
/* PowerPC 602 exception model */ |
| 478 |
PPC_FLAGS_EXCP_602 = 0x00000300,
|
|
| 130 |
POWERPC_EXCP_602,
|
|
| 479 | 131 |
/* PowerPC 603 exception model */ |
| 480 |
PPC_FLAGS_EXCP_603 = 0x00000400, |
|
| 132 |
POWERPC_EXCP_603, |
|
| 133 |
/* PowerPC 603e exception model */ |
|
| 134 |
POWERPC_EXCP_603E, |
|
| 135 |
/* PowerPC G2 exception model */ |
|
| 136 |
POWERPC_EXCP_G2, |
|
| 481 | 137 |
/* PowerPC 604 exception model */ |
| 482 |
PPC_FLAGS_EXCP_604 = 0x00000500,
|
|
| 138 |
POWERPC_EXCP_604,
|
|
| 483 | 139 |
/* PowerPC 7x0 exception model */ |
| 484 |
PPC_FLAGS_EXCP_7x0 = 0x00000600,
|
|
| 140 |
POWERPC_EXCP_7x0,
|
|
| 485 | 141 |
/* PowerPC 7x5 exception model */ |
| 486 |
PPC_FLAGS_EXCP_7x5 = 0x00000700,
|
|
| 142 |
POWERPC_EXCP_7x5,
|
|
| 487 | 143 |
/* PowerPC 74xx exception model */ |
| 488 |
PPC_FLAGS_EXCP_74xx = 0x00000800,
|
|
| 144 |
POWERPC_EXCP_74xx,
|
|
| 489 | 145 |
/* PowerPC 970 exception model */ |
| 490 |
PPC_FLAGS_EXCP_970 = 0x00000900,
|
|
| 146 |
POWERPC_EXCP_970,
|
|
| 491 | 147 |
/* BookE exception model */ |
| 492 |
PPC_FLAGS_EXCP_BOOKE = 0x00000A00, |
|
| 493 |
/* Input pins model */ |
|
| 494 |
PPC_FLAGS_INPUT_MASK = 0x000F0000, |
|
| 148 |
POWERPC_EXCP_BOOKE, |
|
| 149 |
}; |
|
| 150 |
|
|
| 151 |
/*****************************************************************************/ |
|
| 152 |
/* Input pins model */ |
|
| 153 |
enum {
|
|
| 154 |
PPC_FLAGS_INPUT_UNKNOWN = 0, |
|
| 495 | 155 |
/* PowerPC 6xx bus */ |
| 496 |
PPC_FLAGS_INPUT_6xx = 0x00000000,
|
|
| 156 |
PPC_FLAGS_INPUT_6xx, |
|
| 497 | 157 |
/* BookE bus */ |
| 498 |
PPC_FLAGS_INPUT_BookE = 0x00010000,
|
|
| 499 |
/* PowerPC 4xx bus */
|
|
| 500 |
PPC_FLAGS_INPUT_40x = 0x00020000,
|
|
| 158 |
PPC_FLAGS_INPUT_BookE, |
|
| 159 |
/* PowerPC 405 bus */
|
|
| 160 |
PPC_FLAGS_INPUT_405,
|
|
| 501 | 161 |
/* PowerPC 970 bus */ |
| 502 |
PPC_FLAGS_INPUT_970 = 0x00030000, |
|
| 162 |
PPC_FLAGS_INPUT_970, |
|
| 163 |
/* PowerPC 401 bus */ |
|
| 164 |
PPC_FLAGS_INPUT_401, |
|
| 503 | 165 |
}; |
| 504 | 166 |
|
| 505 |
#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK) |
|
| 506 |
#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK) |
|
| 507 |
#define PPC_INPUT(env) (env->flags & PPC_FLAGS_INPUT_MASK) |
|
| 167 |
#define PPC_INPUT(env) (env->bus_model) |
|
| 508 | 168 |
|
| 509 |
/*****************************************************************************/ |
|
| 510 |
/* Supported instruction set definitions */ |
|
| 511 |
/* This generates an empty opcode table... */ |
|
| 512 |
#define PPC_INSNS_TODO (PPC_NONE) |
|
| 513 |
#define PPC_FLAGS_TODO (0x00000000) |
|
| 514 |
|
|
| 515 |
/* PowerPC 40x instruction set */ |
|
| 516 |
#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON) |
|
| 517 |
/* PowerPC 401 */ |
|
| 518 |
#define PPC_INSNS_401 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 519 |
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) |
|
| 520 |
#define PPC_FLAGS_401 (PPC_FLAGS_MMU_401 | PPC_FLAGS_EXCP_40x | \ |
|
| 521 |
PPC_FLAGS_INPUT_40x) |
|
| 522 |
/* PowerPC 403 */ |
|
| 523 |
#define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 524 |
PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_4xx_COMMON | \ |
|
| 525 |
PPC_40x_EXCP | PPC_40x_SPEC | PPC_40x_ICBT) |
|
| 526 |
#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x | \ |
|
| 527 |
PPC_FLAGS_INPUT_40x) |
|
| 528 |
/* PowerPC 405 */ |
|
| 529 |
#define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 530 |
PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
|
| 531 |
PPC_TB | PPC_4xx_COMMON | PPC_40x_SPEC | \ |
|
| 532 |
PPC_40x_ICBT | PPC_40x_EXCP | PPC_405_MAC) |
|
| 533 |
#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \ |
|
| 534 |
PPC_FLAGS_INPUT_40x) |
|
| 535 |
/* PowerPC 440 */ |
|
| 536 |
#define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \ |
|
| 537 |
PPC_MEM_TLBSYNC | PPC_4xx_COMMON | PPC_405_MAC | \ |
|
| 538 |
PPC_440_SPEC) |
|
| 539 |
#define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \ |
|
| 540 |
PPC_FLAGS_INPUT_BookE) |
|
| 541 |
/* Generic BookE PowerPC */ |
|
| 542 |
#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_MEM_TLBSYNC | PPC_BOOKE | \ |
|
| 543 |
PPC_MEM_EIEIO | PPC_FLOAT | PPC_FLOAT_OPT | \ |
|
| 544 |
PPC_CACHE_OPT) |
|
| 545 |
#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \ |
|
| 546 |
PPC_FLAGS_INPUT_BookE) |
|
| 547 |
/* e500 core */ |
|
| 548 |
#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_MEM_TLBSYNC | PPC_BOOKE | \ |
|
| 549 |
PPC_MEM_EIEIO | PPC_CACHE_OPT | PPC_E500_VECTOR) |
|
| 550 |
#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \ |
|
| 551 |
PPC_FLAGS_INPUT_BookE) |
|
| 552 |
/* Non-embedded PowerPC */ |
|
| 553 |
#define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \ |
|
| 554 |
PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE) |
|
| 555 |
/* PowerPC 601 */ |
|
| 556 |
#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR) |
|
| 557 |
#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601 | \ |
|
| 558 |
PPC_FLAGS_INPUT_6xx) |
|
| 559 |
/* PowerPC 602 */ |
|
| 560 |
#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \ |
|
| 561 |
PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC) |
|
| 562 |
#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602 | \ |
|
| 563 |
PPC_FLAGS_INPUT_6xx) |
|
| 564 |
/* PowerPC 603 */ |
|
| 565 |
#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \ |
|
| 566 |
PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB) |
|
| 567 |
#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \ |
|
| 568 |
PPC_FLAGS_INPUT_6xx) |
|
| 569 |
/* PowerPC G2 */ |
|
| 570 |
#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \ |
|
| 571 |
PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB) |
|
| 572 |
#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \ |
|
| 573 |
PPC_FLAGS_INPUT_6xx) |
|
| 574 |
/* PowerPC 604 */ |
|
| 575 |
#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \ |
|
| 576 |
PPC_MEM_TLBSYNC | PPC_TB) |
|
| 577 |
#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604 | \ |
|
| 578 |
PPC_FLAGS_INPUT_6xx) |
|
| 579 |
/* PowerPC 740/750 (aka G3) */ |
|
| 580 |
#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \ |
|
| 581 |
PPC_MEM_TLBSYNC | PPC_TB) |
|
| 582 |
#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0 | \ |
|
| 583 |
PPC_FLAGS_INPUT_6xx) |
|
| 584 |
/* PowerPC 745/755 */ |
|
| 585 |
#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \ |
|
| 586 |
PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB) |
|
| 587 |
#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5 | \ |
|
| 588 |
PPC_FLAGS_INPUT_6xx) |
|
| 589 |
/* PowerPC 74xx (aka G4) */ |
|
| 590 |
#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \ |
|
| 591 |
PPC_MEM_TLBSYNC | PPC_TB) |
|
| 592 |
#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx | \ |
|
| 593 |
PPC_FLAGS_INPUT_6xx) |
|
| 594 |
/* PowerPC 970 (aka G5) */ |
|
| 595 |
#define PPC_INSNS_970 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_FLOAT_OPT | \ |
|
| 596 |
PPC_ALTIVEC | PPC_MEM_TLBSYNC | PPC_TB | \ |
|
| 597 |
PPC_64B | PPC_64_BRIDGE | PPC_SLBI) |
|
| 598 |
#define PPC_FLAGS_970 (PPC_FLAGS_MMU_64BRIDGE | PPC_FLAGS_EXCP_970 | \ |
|
| 599 |
PPC_FLAGS_INPUT_970) |
|
| 600 |
|
|
| 601 |
/* Default PowerPC will be 604/970 */ |
|
| 602 |
#define PPC_INSNS_PPC32 PPC_INSNS_604 |
|
| 603 |
#define PPC_FLAGS_PPC32 PPC_FLAGS_604 |
|
| 604 |
#define PPC_INSNS_PPC64 PPC_INSNS_970 |
|
| 605 |
#define PPC_FLAGS_PPC64 PPC_FLAGS_970 |
|
| 606 |
#define PPC_INSNS_DEFAULT PPC_INSNS_604 |
|
| 607 |
#define PPC_FLAGS_DEFAULT PPC_FLAGS_604 |
|
| 608 | 169 |
typedef struct ppc_def_t ppc_def_t; |
| 170 |
typedef struct opc_handler_t opc_handler_t; |
|
| 609 | 171 |
|
| 610 | 172 |
/*****************************************************************************/ |
| 611 | 173 |
/* Types used to describe some PowerPC registers */ |
| 612 | 174 |
typedef struct CPUPPCState CPUPPCState; |
| 613 |
typedef struct opc_handler_t opc_handler_t; |
|
| 614 | 175 |
typedef struct ppc_tb_t ppc_tb_t; |
| 615 | 176 |
typedef struct ppc_spr_t ppc_spr_t; |
| 616 | 177 |
typedef struct ppc_dcr_t ppc_dcr_t; |
| ... | ... | |
| 832 | 393 |
|
| 833 | 394 |
/* Those resources are used during exception processing */ |
| 834 | 395 |
/* CPU model definition */ |
| 835 |
uint64_t msr_mask; |
|
| 396 |
target_ulong msr_mask; |
|
| 397 |
uint8_t mmu_model; |
|
| 398 |
uint8_t excp_model; |
|
| 399 |
uint8_t bus_model; |
|
| 400 |
uint8_t pad; |
|
| 836 | 401 |
uint32_t flags; |
| 837 | 402 |
|
| 838 | 403 |
int exception_index; |
| ... | ... | |
| 985 | 550 |
#define SPR_LR (0x008) |
| 986 | 551 |
#define SPR_CTR (0x009) |
| 987 | 552 |
#define SPR_DSISR (0x012) |
| 988 |
#define SPR_DAR (0x013) |
|
| 553 |
#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
|
|
| 989 | 554 |
#define SPR_601_RTCU (0x014) |
| 990 | 555 |
#define SPR_601_RTCL (0x015) |
| 991 | 556 |
#define SPR_DECR (0x016) |
| ... | ... | |
| 1203 | 768 |
#define SPR_440_ITV1 (0x375) |
| 1204 | 769 |
#define SPR_440_ITV2 (0x376) |
| 1205 | 770 |
#define SPR_440_ITV3 (0x377) |
| 771 |
#define SPR_440_CCR1 (0x378) |
|
| 772 |
#define SPR_DCRIPR (0x37B) |
|
| 1206 | 773 |
#define SPR_PPR (0x380) |
| 1207 | 774 |
#define SPR_440_DNV0 (0x390) |
| 1208 | 775 |
#define SPR_440_DNV1 (0x391) |
| ... | ... | |
| 1219 | 786 |
#define SPR_BOOKE_DCDBTRH (0x39D) |
| 1220 | 787 |
#define SPR_BOOKE_ICDBTRL (0x39E) |
| 1221 | 788 |
#define SPR_BOOKE_ICDBTRH (0x39F) |
| 789 |
#define SPR_UMMCR2 (0x3A0) |
|
| 790 |
#define SPR_UPMC5 (0x3A1) |
|
| 791 |
#define SPR_UPMC6 (0x3A2) |
|
| 792 |
#define SPR_UBAMR (0x3A7) |
|
| 1222 | 793 |
#define SPR_UMMCR0 (0x3A8) |
| 1223 | 794 |
#define SPR_UPMC1 (0x3A9) |
| 1224 | 795 |
#define SPR_UPMC2 (0x3AA) |
| 1225 |
#define SPR_USIA (0x3AB)
|
|
| 796 |
#define SPR_USIAR (0x3AB)
|
|
| 1226 | 797 |
#define SPR_UMMCR1 (0x3AC) |
| 1227 | 798 |
#define SPR_UPMC3 (0x3AD) |
| 1228 | 799 |
#define SPR_UPMC4 (0x3AE) |
| 1229 | 800 |
#define SPR_USDA (0x3AF) |
| 1230 | 801 |
#define SPR_40x_ZPR (0x3B0) |
| 1231 | 802 |
#define SPR_BOOKE_MAS7 (0x3B0) |
| 803 |
#define SPR_620_PMR0 (0x3B0) |
|
| 804 |
#define SPR_MMCR2 (0x3B0) |
|
| 805 |
#define SPR_PMC5 (0x3B1) |
|
| 1232 | 806 |
#define SPR_40x_PID (0x3B1) |
| 807 |
#define SPR_620_PMR1 (0x3B1) |
|
| 808 |
#define SPR_PMC6 (0x3B2) |
|
| 1233 | 809 |
#define SPR_440_MMUCR (0x3B2) |
| 810 |
#define SPR_620_PMR2 (0x3B2) |
|
| 1234 | 811 |
#define SPR_4xx_CCR0 (0x3B3) |
| 1235 | 812 |
#define SPR_BOOKE_EPLC (0x3B3) |
| 813 |
#define SPR_620_PMR3 (0x3B3) |
|
| 1236 | 814 |
#define SPR_405_IAC3 (0x3B4) |
| 1237 | 815 |
#define SPR_BOOKE_EPSC (0x3B4) |
| 816 |
#define SPR_620_PMR4 (0x3B4) |
|
| 1238 | 817 |
#define SPR_405_IAC4 (0x3B5) |
| 818 |
#define SPR_620_PMR5 (0x3B5) |
|
| 1239 | 819 |
#define SPR_405_DVC1 (0x3B6) |
| 820 |
#define SPR_620_PMR6 (0x3B6) |
|
| 1240 | 821 |
#define SPR_405_DVC2 (0x3B7) |
| 822 |
#define SPR_620_PMR7 (0x3B7) |
|
| 823 |
#define SPR_BAMR (0x3B7) |
|
| 1241 | 824 |
#define SPR_MMCR0 (0x3B8) |
| 825 |
#define SPR_620_PMR8 (0x3B8) |
|
| 1242 | 826 |
#define SPR_PMC1 (0x3B9) |
| 1243 | 827 |
#define SPR_40x_SGR (0x3B9) |
| 828 |
#define SPR_620_PMR9 (0x3B9) |
|
| 1244 | 829 |
#define SPR_PMC2 (0x3BA) |
| 1245 | 830 |
#define SPR_40x_DCWR (0x3BA) |
| 1246 |
#define SPR_SIA (0x3BB) |
|
| 831 |
#define SPR_620_PMRA (0x3BA) |
|
| 832 |
#define SPR_SIAR (0x3BB) |
|
| 1247 | 833 |
#define SPR_405_SLER (0x3BB) |
| 834 |
#define SPR_620_PMRB (0x3BB) |
|
| 1248 | 835 |
#define SPR_MMCR1 (0x3BC) |
| 1249 | 836 |
#define SPR_405_SU0R (0x3BC) |
| 837 |
#define SPR_620_PMRC (0x3BC) |
|
| 838 |
#define SPR_401_SKR (0x3BC) |
|
| 1250 | 839 |
#define SPR_PMC3 (0x3BD) |
| 1251 | 840 |
#define SPR_405_DBCR1 (0x3BD) |
| 841 |
#define SPR_620_PMRD (0x3BD) |
|
| 1252 | 842 |
#define SPR_PMC4 (0x3BE) |
| 843 |
#define SPR_620_PMRE (0x3BE) |
|
| 1253 | 844 |
#define SPR_SDA (0x3BF) |
| 845 |
#define SPR_620_PMRF (0x3BF) |
|
| 1254 | 846 |
#define SPR_403_VTBL (0x3CC) |
| 1255 | 847 |
#define SPR_403_VTBU (0x3CD) |
| 1256 | 848 |
#define SPR_DMISS (0x3D0) |
| ... | ... | |
| 1258 | 850 |
#define SPR_HASH1 (0x3D2) |
| 1259 | 851 |
#define SPR_HASH2 (0x3D3) |
| 1260 | 852 |
#define SPR_BOOKE_ICDBDR (0x3D3) |
| 853 |
#define SPR_TLBMISS (0x3D4) |
|
| 1261 | 854 |
#define SPR_IMISS (0x3D4) |
| 1262 | 855 |
#define SPR_40x_ESR (0x3D4) |
| 856 |
#define SPR_PTEHI (0x3D5) |
|
| 1263 | 857 |
#define SPR_ICMP (0x3D5) |
| 1264 | 858 |
#define SPR_40x_DEAR (0x3D5) |
| 859 |
#define SPR_PTELO (0x3D6) |
|
| 1265 | 860 |
#define SPR_RPA (0x3D6) |
| 1266 | 861 |
#define SPR_40x_EVPR (0x3D6) |
| 862 |
#define SPR_L3PM (0x3D7) |
|
| 1267 | 863 |
#define SPR_403_CDBCR (0x3D7) |
| 864 |
#define SPR_L3OHCR (0x3D8) |
|
| 1268 | 865 |
#define SPR_TCR (0x3D8) |
| 1269 | 866 |
#define SPR_40x_TSR (0x3D8) |
| 1270 | 867 |
#define SPR_IBR (0x3DA) |
| 1271 | 868 |
#define SPR_40x_TCR (0x3DA) |
| 1272 |
#define SPR_ESASR (0x3DB)
|
|
| 869 |
#define SPR_ESASRR (0x3DB)
|
|
| 1273 | 870 |
#define SPR_40x_PIT (0x3DB) |
| 1274 | 871 |
#define SPR_403_TBL (0x3DC) |
| 1275 | 872 |
#define SPR_403_TBU (0x3DD) |
| ... | ... | |
| 1277 | 874 |
#define SPR_40x_SRR2 (0x3DE) |
| 1278 | 875 |
#define SPR_SER (0x3DF) |
| 1279 | 876 |
#define SPR_40x_SRR3 (0x3DF) |
| 877 |
#define SPR_L3ITCR0 (0x3E8) |
|
| 878 |
#define SPR_L3ITCR1 (0x3E9) |
|
| 879 |
#define SPR_L3ITCR2 (0x3EA) |
|
| 880 |
#define SPR_L3ITCR3 (0x3EB) |
|
| 1280 | 881 |
#define SPR_HID0 (0x3F0) |
| 1281 | 882 |
#define SPR_40x_DBSR (0x3F0) |
| 1282 | 883 |
#define SPR_HID1 (0x3F1) |
| ... | ... | |
| 1284 | 885 |
#define SPR_40x_DBCR0 (0x3F2) |
| 1285 | 886 |
#define SPR_601_HID2 (0x3F2) |
| 1286 | 887 |
#define SPR_E500_L1CSR0 (0x3F2) |
| 888 |
#define SPR_ICTRL (0x3F3) |
|
| 1287 | 889 |
#define SPR_HID2 (0x3F3) |
| 1288 | 890 |
#define SPR_E500_L1CSR1 (0x3F3) |
| 1289 | 891 |
#define SPR_440_DBDR (0x3F3) |
| 892 |
#define SPR_LDSTDB (0x3F4) |
|
| 1290 | 893 |
#define SPR_40x_IAC1 (0x3F4) |
| 1291 | 894 |
#define SPR_BOOKE_MMUCSR0 (0x3F4) |
| 1292 | 895 |
#define SPR_DABR (0x3F5) |
| ... | ... | |
| 1295 | 898 |
#define SPR_40x_IAC2 (0x3F5) |
| 1296 | 899 |
#define SPR_601_HID5 (0x3F5) |
| 1297 | 900 |
#define SPR_40x_DAC1 (0x3F6) |
| 901 |
#define SPR_MSSCR0 (0x3F6) |
|
| 902 |
#define SPR_MSSSR0 (0x3F7) |
|
| 1298 | 903 |
#define SPR_DABRX (0x3F7) |
| 1299 | 904 |
#define SPR_40x_DAC2 (0x3F7) |
| 1300 | 905 |
#define SPR_BOOKE_MMUCFG (0x3F7) |
| 1301 |
#define SPR_L2PM (0x3F8) |
|
| 906 |
#define SPR_LDSTCR (0x3F8) |
|
| 907 |
#define SPR_L2PMCR (0x3F8) |
|
| 1302 | 908 |
#define SPR_750_HID2 (0x3F8) |
| 909 |
#define SPR_620_HID8 (0x3F8) |
|
| 1303 | 910 |
#define SPR_L2CR (0x3F9) |
| 911 |
#define SPR_620_HID9 (0x3F9) |
|
| 912 |
#define SPR_L3CR (0x3FA) |
|
| 1304 | 913 |
#define SPR_IABR2 (0x3FA) |
| 1305 | 914 |
#define SPR_40x_DCCR (0x3FA) |
| 1306 | 915 |
#define SPR_ICTC (0x3FB) |
| ... | ... | |
| 1310 | 919 |
#define SPR_SP (0x3FD) |
| 1311 | 920 |
#define SPR_THRM2 (0x3FD) |
| 1312 | 921 |
#define SPR_403_PBU1 (0x3FD) |
| 922 |
#define SPR_604_HID13 (0x3FD) |
|
| 1313 | 923 |
#define SPR_LT (0x3FE) |
| 1314 | 924 |
#define SPR_THRM3 (0x3FE) |
| 1315 | 925 |
#define SPR_FPECR (0x3FE) |
| ... | ... | |
| 1317 | 927 |
#define SPR_PIR (0x3FF) |
| 1318 | 928 |
#define SPR_403_PBU2 (0x3FF) |
| 1319 | 929 |
#define SPR_601_HID15 (0x3FF) |
| 930 |
#define SPR_604_HID15 (0x3FF) |
|
| 1320 | 931 |
#define SPR_E500_SVR (0x3FF) |
| 1321 | 932 |
|
| 1322 | 933 |
/*****************************************************************************/ |
| ... | ... | |
| 1367 | 978 |
#define EXCP_40x_DEBUG 0x2000 /* Debug exception */ |
| 1368 | 979 |
/* 405 specific exceptions */ |
| 1369 | 980 |
#define EXCP_405_APU 0x0F20 /* APU unavailable exception */ |
| 981 |
/* 440 specific exceptions */ |
|
| 982 |
#define EXCP_440_CRIT 0x0100 /* Critical interrupt */ |
|
| 983 |
#define EXCP_440_SPEU 0x1600 /* SPE unavailable exception */ |
|
| 984 |
#define EXCP_440_SPED 0x1700 /* SPE floating-point data exception */ |
|
| 985 |
#define EXCP_440_SPER 0x1800 /* SPE floating-point round exception */ |
|
| 1370 | 986 |
/* TLB assist exceptions (602/603) */ |
| 1371 | 987 |
#define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */ |
| 1372 | 988 |
#define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */ |
| ... | ... | |
| 1377 | 993 |
/* Altivec related exceptions */ |
| 1378 | 994 |
#define EXCP_VPU 0x0F20 /* VPU unavailable exception */ |
| 1379 | 995 |
/* 601 specific exceptions */ |
| 1380 |
#define EXCP_601_IO 0x0600 /* IO error exception */
|
|
| 996 |
#define EXCP_601_IO 0x0A00 /* IO error exception */
|
|
| 1381 | 997 |
#define EXCP_601_RUNM 0x2000 /* Run mode exception */ |
| 1382 | 998 |
/* 602 specific exceptions */ |
| 1383 | 999 |
#define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */ |
| ... | ... | |
| 1468 | 1084 |
}; |
| 1469 | 1085 |
|
| 1470 | 1086 |
enum {
|
| 1087 |
/* PowerPC 401/403 input pins */ |
|
| 1088 |
PPC401_INPUT_RESET = 0, |
|
| 1089 |
PPC401_INPUT_CINT = 1, |
|
| 1090 |
PPC401_INPUT_INT = 2, |
|
| 1091 |
PPC401_INPUT_BERR = 3, |
|
| 1092 |
PPC401_INPUT_HALT = 4, |
|
| 1093 |
}; |
|
| 1094 |
|
|
| 1095 |
enum {
|
|
| 1471 | 1096 |
/* PowerPC 405 input pins */ |
| 1472 | 1097 |
PPC405_INPUT_RESET_CORE = 0, |
| 1473 | 1098 |
PPC405_INPUT_RESET_CHIP = 1, |
| ... | ... | |
| 1479 | 1104 |
}; |
| 1480 | 1105 |
|
| 1481 | 1106 |
enum {
|
| 1107 |
/* PowerPC 620 (and probably others) input pins */ |
|
| 1108 |
PPC620_INPUT_HRESET = 0, |
|
| 1109 |
PPC620_INPUT_SRESET = 1, |
|
| 1110 |
PPC620_INPUT_CKSTP = 2, |
|
| 1111 |
PPC620_INPUT_TBEN = 3, |
|
| 1112 |
PPC620_INPUT_WAKEUP = 4, |
|
| 1113 |
PPC620_INPUT_MCP = 5, |
|
| 1114 |
PPC620_INPUT_SMI = 6, |
|
| 1115 |
PPC620_INPUT_INT = 7, |
|
| 1116 |
}; |
|
| 1117 |
|
|
| 1118 |
enum {
|
|
| 1482 | 1119 |
/* PowerPC 970 input pins */ |
| 1483 | 1120 |
PPC970_INPUT_HRESET = 0, |
| 1484 | 1121 |
PPC970_INPUT_SRESET = 1, |
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