Revision a750fc0b target-ppc/translate.c
| b/target-ppc/translate.c | ||
|---|---|---|
| 27 | 27 |
#include "exec-all.h" |
| 28 | 28 |
#include "disas.h" |
| 29 | 29 |
|
| 30 |
/* Include definitions for instructions classes and implementations flags */ |
|
| 30 | 31 |
//#define DO_SINGLE_STEP |
| 31 | 32 |
//#define PPC_DEBUG_DISAS |
| 32 | 33 |
//#define DEBUG_MEMORY_ACCESSES |
| 33 | 34 |
//#define DO_PPC_STATISTICS |
| 34 | 35 |
|
| 36 |
/*****************************************************************************/ |
|
| 37 |
/* Code translation helpers */ |
|
| 35 | 38 |
#if defined(USE_DIRECT_JUMP) |
| 36 | 39 |
#define TBPARAM(x) |
| 37 | 40 |
#else |
| ... | ... | |
| 175 | 178 |
uint64_t type; |
| 176 | 179 |
/* handler */ |
| 177 | 180 |
void (*handler)(DisasContext *ctx); |
| 178 |
#if defined(DO_PPC_STATISTICS) |
|
| 181 |
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
|
|
| 179 | 182 |
const unsigned char *oname; |
| 183 |
#endif |
|
| 184 |
#if defined(DO_PPC_STATISTICS) |
|
| 180 | 185 |
uint64_t count; |
| 181 | 186 |
#endif |
| 182 | 187 |
}; |
| ... | ... | |
| 249 | 254 |
const unsigned char *oname; |
| 250 | 255 |
} opcode_t; |
| 251 | 256 |
|
| 257 |
/*****************************************************************************/ |
|
| 252 | 258 |
/*** Instruction decoding ***/ |
| 253 | 259 |
#define EXTRACT_HELPER(name, shift, nb) \ |
| 254 | 260 |
static inline uint32_t name (uint32_t opcode) \ |
| ... | ... | |
| 365 | 371 |
return ret; |
| 366 | 372 |
} |
| 367 | 373 |
|
| 374 |
/*****************************************************************************/ |
|
| 375 |
/* PowerPC Instructions types definitions */ |
|
| 376 |
enum {
|
|
| 377 |
PPC_NONE = 0x0000000000000000ULL, |
|
| 378 |
/* integer operations instructions */ |
|
| 379 |
/* flow control instructions */ |
|
| 380 |
/* virtual memory instructions */ |
|
| 381 |
/* ld/st with reservation instructions */ |
|
| 382 |
/* cache control instructions */ |
|
| 383 |
/* spr/msr access instructions */ |
|
| 384 |
PPC_INSNS_BASE = 0x0000000000000001ULL, |
|
| 385 |
#define PPC_INTEGER PPC_INSNS_BASE |
|
| 386 |
#define PPC_FLOW PPC_INSNS_BASE |
|
| 387 |
#define PPC_MEM PPC_INSNS_BASE |
|
| 388 |
#define PPC_RES PPC_INSNS_BASE |
|
| 389 |
#define PPC_CACHE PPC_INSNS_BASE |
|
| 390 |
#define PPC_MISC PPC_INSNS_BASE |
|
| 391 |
/* Optional floating point instructions */ |
|
| 392 |
PPC_FLOAT = 0x0000000000000002ULL, |
|
| 393 |
PPC_FLOAT_FSQRT = 0x0000000000000004ULL, |
|
| 394 |
PPC_FLOAT_FRES = 0x0000000000000008ULL, |
|
| 395 |
PPC_FLOAT_FRSQRTE = 0x0000000000000010ULL, |
|
| 396 |
PPC_FLOAT_FSEL = 0x0000000000000020ULL, |
|
| 397 |
PPC_FLOAT_STFIWX = 0x0000000000000040ULL, |
|
| 398 |
/* external control instructions */ |
|
| 399 |
PPC_EXTERN = 0x0000000000000080ULL, |
|
| 400 |
/* segment register access instructions */ |
|
| 401 |
PPC_SEGMENT = 0x0000000000000100ULL, |
|
| 402 |
/* Optional cache control instruction */ |
|
| 403 |
PPC_CACHE_DCBA = 0x0000000000000200ULL, |
|
| 404 |
/* Optional memory control instructions */ |
|
| 405 |
PPC_MEM_TLBIA = 0x0000000000000400ULL, |
|
| 406 |
PPC_MEM_TLBIE = 0x0000000000000800ULL, |
|
| 407 |
PPC_MEM_TLBSYNC = 0x0000000000001000ULL, |
|
| 408 |
/* eieio & sync */ |
|
| 409 |
PPC_MEM_SYNC = 0x0000000000002000ULL, |
|
| 410 |
/* PowerPC 6xx TLB management instructions */ |
|
| 411 |
PPC_6xx_TLB = 0x0000000000004000ULL, |
|
| 412 |
/* Altivec support */ |
|
| 413 |
PPC_ALTIVEC = 0x0000000000008000ULL, |
|
| 414 |
/* Time base mftb instruction */ |
|
| 415 |
PPC_MFTB = 0x0000000000010000ULL, |
|
| 416 |
/* Embedded PowerPC dedicated instructions */ |
|
| 417 |
PPC_EMB_COMMON = 0x0000000000020000ULL, |
|
| 418 |
/* PowerPC 40x exception model */ |
|
| 419 |
PPC_40x_EXCP = 0x0000000000040000ULL, |
|
| 420 |
/* PowerPC 40x TLB management instructions */ |
|
| 421 |
PPC_40x_TLB = 0x0000000000080000ULL, |
|
| 422 |
/* PowerPC 405 Mac instructions */ |
|
| 423 |
PPC_405_MAC = 0x0000000000100000ULL, |
|
| 424 |
/* PowerPC 440 specific instructions */ |
|
| 425 |
PPC_440_SPEC = 0x0000000000200000ULL, |
|
| 426 |
/* Power-to-PowerPC bridge (601) */ |
|
| 427 |
PPC_POWER_BR = 0x0000000000400000ULL, |
|
| 428 |
/* PowerPC 602 specific */ |
|
| 429 |
PPC_602_SPEC = 0x0000000000800000ULL, |
|
| 430 |
/* Deprecated instructions */ |
|
| 431 |
/* Original POWER instruction set */ |
|
| 432 |
PPC_POWER = 0x0000000001000000ULL, |
|
| 433 |
/* POWER2 instruction set extension */ |
|
| 434 |
PPC_POWER2 = 0x0000000002000000ULL, |
|
| 435 |
/* Power RTC support */ |
|
| 436 |
PPC_POWER_RTC = 0x0000000004000000ULL, |
|
| 437 |
/* 64 bits PowerPC instructions */ |
|
| 438 |
/* 64 bits PowerPC instruction set */ |
|
| 439 |
PPC_64B = 0x0000000008000000ULL, |
|
| 440 |
/* 64 bits hypervisor extensions */ |
|
| 441 |
PPC_64H = 0x0000000010000000ULL, |
|
| 442 |
/* 64 bits PowerPC "bridge" features */ |
|
| 443 |
PPC_64_BRIDGE = 0x0000000020000000ULL, |
|
| 444 |
/* BookE (embedded) PowerPC specification */ |
|
| 445 |
PPC_BOOKE = 0x0000000040000000ULL, |
|
| 446 |
/* eieio */ |
|
| 447 |
PPC_MEM_EIEIO = 0x0000000080000000ULL, |
|
| 448 |
/* e500 vector instructions */ |
|
| 449 |
PPC_E500_VECTOR = 0x0000000100000000ULL, |
|
| 450 |
/* PowerPC 4xx dedicated instructions */ |
|
| 451 |
PPC_4xx_COMMON = 0x0000000200000000ULL, |
|
| 452 |
/* PowerPC 2.03 specification extensions */ |
|
| 453 |
PPC_203 = 0x0000000400000000ULL, |
|
| 454 |
/* PowerPC 2.03 SPE extension */ |
|
| 455 |
PPC_SPE = 0x0000000800000000ULL, |
|
| 456 |
/* PowerPC 2.03 SPE floating-point extension */ |
|
| 457 |
PPC_SPEFPU = 0x0000001000000000ULL, |
|
| 458 |
/* SLB management */ |
|
| 459 |
PPC_SLBI = 0x0000002000000000ULL, |
|
| 460 |
/* PowerPC 40x ibct instructions */ |
|
| 461 |
PPC_40x_ICBT = 0x0000004000000000ULL, |
|
| 462 |
/* PowerPC 74xx TLB management instructions */ |
|
| 463 |
PPC_74xx_TLB = 0x0000008000000000ULL, |
|
| 464 |
/* More BookE (embedded) instructions... */ |
|
| 465 |
PPC_BOOKE_EXT = 0x0000010000000000ULL, |
|
| 466 |
/* rfmci is not implemented in all BookE PowerPC */ |
|
| 467 |
PPC_RFMCI = 0x0000020000000000ULL, |
|
| 468 |
/* user-mode DCR access, implemented in PowerPC 460 */ |
|
| 469 |
PPC_DCRUX = 0x0000040000000000ULL, |
|
| 470 |
}; |
|
| 471 |
|
|
| 472 |
/*****************************************************************************/ |
|
| 473 |
/* PowerPC instructions table */ |
|
| 368 | 474 |
#if HOST_LONG_BITS == 64 |
| 369 | 475 |
#define OPC_ALIGN 8 |
| 370 | 476 |
#else |
| ... | ... | |
| 845 | 951 |
|
| 846 | 952 |
#if defined(TARGET_PPC64) |
| 847 | 953 |
/* mulhd mulhd. */ |
| 848 |
GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_INTEGER);
|
|
| 954 |
GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
|
|
| 849 | 955 |
/* mulhdu mulhdu. */ |
| 850 |
GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_INTEGER);
|
|
| 956 |
GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
|
|
| 851 | 957 |
/* mulld mulld. mulldo mulldo. */ |
| 852 |
GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_INTEGER);
|
|
| 958 |
GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
|
|
| 853 | 959 |
/* divd divd. divdo divdo. */ |
| 854 |
GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_INTEGER);
|
|
| 960 |
GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
|
|
| 855 | 961 |
/* divdu divdu. divduo divduo. */ |
| 856 |
GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_INTEGER);
|
|
| 962 |
GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
|
|
| 857 | 963 |
#endif |
| 858 | 964 |
|
| 859 | 965 |
/*** Integer comparison ***/ |
| ... | ... | |
| 1424 | 1530 |
#endif |
| 1425 | 1531 |
|
| 1426 | 1532 |
/*** Floating-Point arithmetic ***/ |
| 1427 |
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat) \
|
|
| 1428 |
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
|
|
| 1533 |
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, type) \
|
|
| 1534 |
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
|
|
| 1429 | 1535 |
{ \
|
| 1430 | 1536 |
if (unlikely(!ctx->fpu_enabled)) { \
|
| 1431 | 1537 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \ |
| ... | ... | |
| 1444 | 1550 |
gen_op_set_Rc1(); \ |
| 1445 | 1551 |
} |
| 1446 | 1552 |
|
| 1447 |
#define GEN_FLOAT_ACB(name, op2) \
|
|
| 1448 |
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0); \
|
|
| 1449 |
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1); |
|
| 1553 |
#define GEN_FLOAT_ACB(name, op2, type) \
|
|
| 1554 |
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, type); \
|
|
| 1555 |
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, type);
|
|
| 1450 | 1556 |
|
| 1451 | 1557 |
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \ |
| 1452 | 1558 |
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \ |
| ... | ... | |
| 1492 | 1598 |
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \ |
| 1493 | 1599 |
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1); |
| 1494 | 1600 |
|
| 1495 |
#define GEN_FLOAT_B(name, op2, op3) \
|
|
| 1496 |
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
|
|
| 1601 |
#define GEN_FLOAT_B(name, op2, op3, type) \
|
|
| 1602 |
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
|
|
| 1497 | 1603 |
{ \
|
| 1498 | 1604 |
if (unlikely(!ctx->fpu_enabled)) { \
|
| 1499 | 1605 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \ |
| ... | ... | |
| 1507 | 1613 |
gen_op_set_Rc1(); \ |
| 1508 | 1614 |
} |
| 1509 | 1615 |
|
| 1510 |
#define GEN_FLOAT_BS(name, op1, op2) \
|
|
| 1511 |
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
|
|
| 1616 |
#define GEN_FLOAT_BS(name, op1, op2, type) \
|
|
| 1617 |
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
|
|
| 1512 | 1618 |
{ \
|
| 1513 | 1619 |
if (unlikely(!ctx->fpu_enabled)) { \
|
| 1514 | 1620 |
RET_EXCP(ctx, EXCP_NO_FP, 0); \ |
| ... | ... | |
| 1529 | 1635 |
/* fmul - fmuls */ |
| 1530 | 1636 |
GEN_FLOAT_AC(mul, 0x19, 0x0000F800); |
| 1531 | 1637 |
|
| 1532 |
/* fres */ /* XXX: not in 601 */
|
|
| 1533 |
GEN_FLOAT_BS(res, 0x3B, 0x18); |
|
| 1638 |
/* fres */ |
|
| 1639 |
GEN_FLOAT_BS(res, 0x3B, 0x18, PPC_FLOAT_FRES);
|
|
| 1534 | 1640 |
|
| 1535 |
/* frsqrte */ /* XXX: not in 601 */
|
|
| 1536 |
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A); |
|
| 1641 |
/* frsqrte */ |
|
| 1642 |
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, PPC_FLOAT_FRSQRTE);
|
|
| 1537 | 1643 |
|
| 1538 |
/* fsel */ /* XXX: not in 601 */
|
|
| 1539 |
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0); |
|
| 1644 |
/* fsel */ |
|
| 1645 |
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, PPC_FLOAT_FSEL);
|
|
| 1540 | 1646 |
/* fsub - fsubs */ |
| 1541 | 1647 |
GEN_FLOAT_AB(sub, 0x14, 0x000007C0); |
| 1542 | 1648 |
/* Optional: */ |
| 1543 | 1649 |
/* fsqrt */ |
| 1544 |
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
|
|
| 1650 |
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
|
|
| 1545 | 1651 |
{
|
| 1546 | 1652 |
if (unlikely(!ctx->fpu_enabled)) {
|
| 1547 | 1653 |
RET_EXCP(ctx, EXCP_NO_FP, 0); |
| ... | ... | |
| 1555 | 1661 |
gen_op_set_Rc1(); |
| 1556 | 1662 |
} |
| 1557 | 1663 |
|
| 1558 |
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
|
|
| 1664 |
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
|
|
| 1559 | 1665 |
{
|
| 1560 | 1666 |
if (unlikely(!ctx->fpu_enabled)) {
|
| 1561 | 1667 |
RET_EXCP(ctx, EXCP_NO_FP, 0); |
| ... | ... | |
| 1572 | 1678 |
|
| 1573 | 1679 |
/*** Floating-Point multiply-and-add ***/ |
| 1574 | 1680 |
/* fmadd - fmadds */ |
| 1575 |
GEN_FLOAT_ACB(madd, 0x1D); |
|
| 1681 |
GEN_FLOAT_ACB(madd, 0x1D, PPC_FLOAT);
|
|
| 1576 | 1682 |
/* fmsub - fmsubs */ |
| 1577 |
GEN_FLOAT_ACB(msub, 0x1C); |
|
| 1683 |
GEN_FLOAT_ACB(msub, 0x1C, PPC_FLOAT);
|
|
| 1578 | 1684 |
/* fnmadd - fnmadds */ |
| 1579 |
GEN_FLOAT_ACB(nmadd, 0x1F); |
|
| 1685 |
GEN_FLOAT_ACB(nmadd, 0x1F, PPC_FLOAT);
|
|
| 1580 | 1686 |
/* fnmsub - fnmsubs */ |
| 1581 |
GEN_FLOAT_ACB(nmsub, 0x1E); |
|
| 1687 |
GEN_FLOAT_ACB(nmsub, 0x1E, PPC_FLOAT);
|
|
| 1582 | 1688 |
|
| 1583 | 1689 |
/*** Floating-Point round & convert ***/ |
| 1584 | 1690 |
/* fctiw */ |
| 1585 |
GEN_FLOAT_B(ctiw, 0x0E, 0x00); |
|
| 1691 |
GEN_FLOAT_B(ctiw, 0x0E, 0x00, PPC_FLOAT);
|
|
| 1586 | 1692 |
/* fctiwz */ |
| 1587 |
GEN_FLOAT_B(ctiwz, 0x0F, 0x00); |
|
| 1693 |
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, PPC_FLOAT);
|
|
| 1588 | 1694 |
/* frsp */ |
| 1589 |
GEN_FLOAT_B(rsp, 0x0C, 0x00); |
|
| 1695 |
GEN_FLOAT_B(rsp, 0x0C, 0x00, PPC_FLOAT);
|
|
| 1590 | 1696 |
#if defined(TARGET_PPC64) |
| 1591 | 1697 |
/* fcfid */ |
| 1592 |
GEN_FLOAT_B(cfid, 0x0E, 0x1A); |
|
| 1698 |
GEN_FLOAT_B(cfid, 0x0E, 0x1A, PPC_64B);
|
|
| 1593 | 1699 |
/* fctid */ |
| 1594 |
GEN_FLOAT_B(ctid, 0x0E, 0x19); |
|
| 1700 |
GEN_FLOAT_B(ctid, 0x0E, 0x19, PPC_64B);
|
|
| 1595 | 1701 |
/* fctidz */ |
| 1596 |
GEN_FLOAT_B(ctidz, 0x0F, 0x19); |
|
| 1702 |
GEN_FLOAT_B(ctidz, 0x0F, 0x19, PPC_64B);
|
|
| 1597 | 1703 |
#endif |
| 1598 | 1704 |
|
| 1599 | 1705 |
/*** Floating-Point compare ***/ |
| ... | ... | |
| 1627 | 1733 |
|
| 1628 | 1734 |
/*** Floating-point move ***/ |
| 1629 | 1735 |
/* fabs */ |
| 1630 |
GEN_FLOAT_B(abs, 0x08, 0x08); |
|
| 1736 |
GEN_FLOAT_B(abs, 0x08, 0x08, PPC_FLOAT);
|
|
| 1631 | 1737 |
|
| 1632 | 1738 |
/* fmr - fmr. */ |
| 1633 | 1739 |
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT) |
| ... | ... | |
| 1644 | 1750 |
} |
| 1645 | 1751 |
|
| 1646 | 1752 |
/* fnabs */ |
| 1647 |
GEN_FLOAT_B(nabs, 0x08, 0x04); |
|
| 1753 |
GEN_FLOAT_B(nabs, 0x08, 0x04, PPC_FLOAT);
|
|
| 1648 | 1754 |
/* fneg */ |
| 1649 |
GEN_FLOAT_B(neg, 0x08, 0x01); |
|
| 1755 |
GEN_FLOAT_B(neg, 0x08, 0x01, PPC_FLOAT);
|
|
| 1650 | 1756 |
|
| 1651 | 1757 |
/*** Floating-Point status & ctrl register ***/ |
| 1652 | 1758 |
/* mcrfs */ |
| ... | ... | |
| 2426 | 2532 |
#endif |
| 2427 | 2533 |
|
| 2428 | 2534 |
/* ldarx */ |
| 2429 |
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_RES)
|
|
| 2535 |
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
|
|
| 2430 | 2536 |
{
|
| 2431 | 2537 |
gen_addr_reg_index(ctx); |
| 2432 | 2538 |
op_ldarx(); |
| ... | ... | |
| 2434 | 2540 |
} |
| 2435 | 2541 |
|
| 2436 | 2542 |
/* stdcx. */ |
| 2437 |
GEN_HANDLER(stdcx_, 0x1F, 0x16, 0x06, 0x00000000, PPC_RES)
|
|
| 2543 |
GEN_HANDLER(stdcx_, 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
|
|
| 2438 | 2544 |
{
|
| 2439 | 2545 |
gen_addr_reg_index(ctx); |
| 2440 | 2546 |
gen_op_load_gpr_T1(rS(ctx->opcode)); |
| ... | ... | |
| 2591 | 2697 |
|
| 2592 | 2698 |
/* Optional: */ |
| 2593 | 2699 |
/* stfiwx */ |
| 2594 |
GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT) |
|
| 2700 |
GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT_STFIWX)
|
|
| 2595 | 2701 |
{
|
| 2596 | 2702 |
if (unlikely(!ctx->fpu_enabled)) {
|
| 2597 | 2703 |
RET_EXCP(ctx, EXCP_NO_FP, 0); |
| ... | ... | |
| 2886 | 2992 |
} |
| 2887 | 2993 |
|
| 2888 | 2994 |
#if defined(TARGET_PPC64) |
| 2889 |
GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_FLOW)
|
|
| 2995 |
GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
|
|
| 2890 | 2996 |
{
|
| 2891 | 2997 |
#if defined(CONFIG_USER_ONLY) |
| 2892 | 2998 |
RET_PRIVOPC(ctx); |
| ... | ... | |
| 3050 | 3156 |
} |
| 3051 | 3157 |
|
| 3052 | 3158 |
/* mftb */ |
| 3053 |
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_TB) |
|
| 3159 |
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
|
|
| 3054 | 3160 |
{
|
| 3055 | 3161 |
gen_op_mfspr(ctx); |
| 3056 | 3162 |
} |
| ... | ... | |
| 3074 | 3180 |
|
| 3075 | 3181 |
/* mtmsr */ |
| 3076 | 3182 |
#if defined(TARGET_PPC64) |
| 3077 |
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001FF801, PPC_MISC)
|
|
| 3183 |
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001FF801, PPC_64B)
|
|
| 3078 | 3184 |
{
|
| 3079 | 3185 |
#if defined(CONFIG_USER_ONLY) |
| 3080 | 3186 |
RET_PRIVREG(ctx); |
| ... | ... | |
| 3296 | 3402 |
|
| 3297 | 3403 |
/* Optional: */ |
| 3298 | 3404 |
/* dcba */ |
| 3299 |
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_OPT)
|
|
| 3405 |
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
|
|
| 3300 | 3406 |
{
|
| 3301 | 3407 |
} |
| 3302 | 3408 |
|
| ... | ... | |
| 3568 | 3674 |
} |
| 3569 | 3675 |
|
| 3570 | 3676 |
/* clcs */ |
| 3571 |
GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR) /* 601 ? */
|
|
| 3677 |
GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR) |
|
| 3572 | 3678 |
{
|
| 3573 | 3679 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 3574 | 3680 |
gen_op_POWER_clcs(); |
| ... | ... | |
| 4222 | 4328 |
|
| 4223 | 4329 |
/* BookE specific instructions */ |
| 4224 | 4330 |
/* XXX: not implemented on 440 ? */ |
| 4225 |
GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE) |
|
| 4331 |
GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
|
|
| 4226 | 4332 |
{
|
| 4227 | 4333 |
/* XXX: TODO */ |
| 4228 | 4334 |
RET_INVAL(ctx); |
| 4229 | 4335 |
} |
| 4230 | 4336 |
|
| 4231 | 4337 |
/* XXX: not implemented on 440 ? */ |
| 4232 |
GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE) |
|
| 4338 |
GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT)
|
|
| 4233 | 4339 |
{
|
| 4234 | 4340 |
#if defined(CONFIG_USER_ONLY) |
| 4235 | 4341 |
RET_PRIVOPC(ctx); |
| ... | ... | |
| 4331 | 4437 |
} |
| 4332 | 4438 |
} |
| 4333 | 4439 |
|
| 4334 |
#define GEN_MAC_HANDLER(name, opc2, opc3, is_440) \ |
|
| 4335 |
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, \ |
|
| 4336 |
is_440 ? PPC_440_SPEC : PPC_405_MAC) \ |
|
| 4440 |
#define GEN_MAC_HANDLER(name, opc2, opc3) \ |
|
| 4441 |
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \ |
|
| 4337 | 4442 |
{ \
|
| 4338 | 4443 |
gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ |
| 4339 | 4444 |
rD(ctx->opcode), Rc(ctx->opcode)); \ |
| 4340 | 4445 |
} |
| 4341 | 4446 |
|
| 4342 | 4447 |
/* macchw - macchw. */ |
| 4343 |
GEN_MAC_HANDLER(macchw, 0x0C, 0x05, 0);
|
|
| 4448 |
GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
|
| 4344 | 4449 |
/* macchwo - macchwo. */ |
| 4345 |
GEN_MAC_HANDLER(macchwo, 0x0C, 0x15, 0);
|
|
| 4450 |
GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
|
| 4346 | 4451 |
/* macchws - macchws. */ |
| 4347 |
GEN_MAC_HANDLER(macchws, 0x0C, 0x07, 0);
|
|
| 4452 |
GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
|
| 4348 | 4453 |
/* macchwso - macchwso. */ |
| 4349 |
GEN_MAC_HANDLER(macchwso, 0x0C, 0x17, 0);
|
|
| 4454 |
GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
|
| 4350 | 4455 |
/* macchwsu - macchwsu. */ |
| 4351 |
GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06, 0);
|
|
| 4456 |
GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
|
| 4352 | 4457 |
/* macchwsuo - macchwsuo. */ |
| 4353 |
GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16, 0);
|
|
| 4458 |
GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
|
| 4354 | 4459 |
/* macchwu - macchwu. */ |
| 4355 |
GEN_MAC_HANDLER(macchwu, 0x0C, 0x04, 0);
|
|
| 4460 |
GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
|
| 4356 | 4461 |
/* macchwuo - macchwuo. */ |
| 4357 |
GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14, 0);
|
|
| 4462 |
GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
|
| 4358 | 4463 |
/* machhw - machhw. */ |
| 4359 |
GEN_MAC_HANDLER(machhw, 0x0C, 0x01, 0);
|
|
| 4464 |
GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
|
| 4360 | 4465 |
/* machhwo - machhwo. */ |
| 4361 |
GEN_MAC_HANDLER(machhwo, 0x0C, 0x11, 0);
|
|
| 4466 |
GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
|
| 4362 | 4467 |
/* machhws - machhws. */ |
| 4363 |
GEN_MAC_HANDLER(machhws, 0x0C, 0x03, 0);
|
|
| 4468 |
GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
|
| 4364 | 4469 |
/* machhwso - machhwso. */ |
| 4365 |
GEN_MAC_HANDLER(machhwso, 0x0C, 0x13, 0);
|
|
| 4470 |
GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
|
| 4366 | 4471 |
/* machhwsu - machhwsu. */ |
| 4367 |
GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02, 0);
|
|
| 4472 |
GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
|
| 4368 | 4473 |
/* machhwsuo - machhwsuo. */ |
| 4369 |
GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12, 0);
|
|
| 4474 |
GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
|
| 4370 | 4475 |
/* machhwu - machhwu. */ |
| 4371 |
GEN_MAC_HANDLER(machhwu, 0x0C, 0x00, 0);
|
|
| 4476 |
GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
|
| 4372 | 4477 |
/* machhwuo - machhwuo. */ |
| 4373 |
GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10, 0);
|
|
| 4478 |
GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
|
| 4374 | 4479 |
/* maclhw - maclhw. */ |
| 4375 |
GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D, 0);
|
|
| 4480 |
GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
|
| 4376 | 4481 |
/* maclhwo - maclhwo. */ |
| 4377 |
GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D, 0);
|
|
| 4482 |
GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
|
| 4378 | 4483 |
/* maclhws - maclhws. */ |
| 4379 |
GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F, 0);
|
|
| 4484 |
GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
|
| 4380 | 4485 |
/* maclhwso - maclhwso. */ |
| 4381 |
GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F, 0);
|
|
| 4486 |
GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
|
| 4382 | 4487 |
/* maclhwu - maclhwu. */ |
| 4383 |
GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C, 0);
|
|
| 4488 |
GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
|
| 4384 | 4489 |
/* maclhwuo - maclhwuo. */ |
| 4385 |
GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C, 0);
|
|
| 4490 |
GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
|
| 4386 | 4491 |
/* maclhwsu - maclhwsu. */ |
| 4387 |
GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E, 0);
|
|
| 4492 |
GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
|
| 4388 | 4493 |
/* maclhwsuo - maclhwsuo. */ |
| 4389 |
GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E, 0);
|
|
| 4494 |
GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
|
| 4390 | 4495 |
/* nmacchw - nmacchw. */ |
| 4391 |
GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05, 0);
|
|
| 4496 |
GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
|
| 4392 | 4497 |
/* nmacchwo - nmacchwo. */ |
| 4393 |
GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15, 0);
|
|
| 4498 |
GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
|
| 4394 | 4499 |
/* nmacchws - nmacchws. */ |
| 4395 |
GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07, 0);
|
|
| 4500 |
GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
|
| 4396 | 4501 |
/* nmacchwso - nmacchwso. */ |
| 4397 |
GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17, 0);
|
|
| 4502 |
GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
|
| 4398 | 4503 |
/* nmachhw - nmachhw. */ |
| 4399 |
GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01, 0);
|
|
| 4504 |
GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
|
| 4400 | 4505 |
/* nmachhwo - nmachhwo. */ |
| 4401 |
GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11, 0);
|
|
| 4506 |
GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
|
| 4402 | 4507 |
/* nmachhws - nmachhws. */ |
| 4403 |
GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03, 1);
|
|
| 4508 |
GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
|
| 4404 | 4509 |
/* nmachhwso - nmachhwso. */ |
| 4405 |
GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13, 1);
|
|
| 4510 |
GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
|
| 4406 | 4511 |
/* nmaclhw - nmaclhw. */ |
| 4407 |
GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D, 1);
|
|
| 4512 |
GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
|
| 4408 | 4513 |
/* nmaclhwo - nmaclhwo. */ |
| 4409 |
GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D, 1);
|
|
| 4514 |
GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
|
| 4410 | 4515 |
/* nmaclhws - nmaclhws. */ |
| 4411 |
GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F, 1);
|
|
| 4516 |
GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
|
| 4412 | 4517 |
/* nmaclhwso - nmaclhwso. */ |
| 4413 |
GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F, 1);
|
|
| 4518 |
GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
|
| 4414 | 4519 |
|
| 4415 | 4520 |
/* mulchw - mulchw. */ |
| 4416 |
GEN_MAC_HANDLER(mulchw, 0x08, 0x05, 0);
|
|
| 4521 |
GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
|
| 4417 | 4522 |
/* mulchwu - mulchwu. */ |
| 4418 |
GEN_MAC_HANDLER(mulchwu, 0x08, 0x04, 0);
|
|
| 4523 |
GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
|
| 4419 | 4524 |
/* mulhhw - mulhhw. */ |
| 4420 |
GEN_MAC_HANDLER(mulhhw, 0x08, 0x01, 0);
|
|
| 4525 |
GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
|
| 4421 | 4526 |
/* mulhhwu - mulhhwu. */ |
| 4422 |
GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00, 0);
|
|
| 4527 |
GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
|
| 4423 | 4528 |
/* mullhw - mullhw. */ |
| 4424 |
GEN_MAC_HANDLER(mullhw, 0x08, 0x0D, 0);
|
|
| 4529 |
GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
|
| 4425 | 4530 |
/* mullhwu - mullhwu. */ |
| 4426 |
GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C, 0);
|
|
| 4531 |
GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
|
| 4427 | 4532 |
|
| 4428 | 4533 |
/* mfdcr */ |
| 4429 | 4534 |
GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON) |
| ... | ... | |
| 4463 | 4568 |
|
| 4464 | 4569 |
/* mfdcrx */ |
| 4465 | 4570 |
/* XXX: not implemented on 440 ? */ |
| 4466 |
GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000001, PPC_BOOKE)
|
|
| 4571 |
GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
|
|
| 4467 | 4572 |
{
|
| 4468 | 4573 |
#if defined(CONFIG_USER_ONLY) |
| 4469 | 4574 |
RET_PRIVREG(ctx); |
| ... | ... | |
| 4475 | 4580 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 4476 | 4581 |
gen_op_load_dcr(); |
| 4477 | 4582 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
| 4583 |
/* Note: Rc update flag set leads to undefined state of Rc0 */ |
|
| 4478 | 4584 |
#endif |
| 4479 | 4585 |
} |
| 4480 | 4586 |
|
| 4481 | 4587 |
/* mtdcrx */ |
| 4482 | 4588 |
/* XXX: not implemented on 440 ? */ |
| 4483 |
GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000001, PPC_BOOKE)
|
|
| 4589 |
GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT)
|
|
| 4484 | 4590 |
{
|
| 4485 | 4591 |
#if defined(CONFIG_USER_ONLY) |
| 4486 | 4592 |
RET_PRIVREG(ctx); |
| ... | ... | |
| 4492 | 4598 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 4493 | 4599 |
gen_op_load_gpr_T1(rS(ctx->opcode)); |
| 4494 | 4600 |
gen_op_store_dcr(); |
| 4601 |
/* Note: Rc update flag set leads to undefined state of Rc0 */ |
|
| 4495 | 4602 |
#endif |
| 4496 | 4603 |
} |
| 4497 | 4604 |
|
| 4605 |
/* mfdcrux (PPC 460) : user-mode access to DCR */ |
|
| 4606 |
GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX) |
|
| 4607 |
{
|
|
| 4608 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
|
| 4609 |
gen_op_load_dcr(); |
|
| 4610 |
gen_op_store_T0_gpr(rD(ctx->opcode)); |
|
| 4611 |
/* Note: Rc update flag set leads to undefined state of Rc0 */ |
|
| 4612 |
} |
|
| 4613 |
|
|
| 4614 |
/* mtdcrux (PPC 460) : user-mode access to DCR */ |
|
| 4615 |
GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX) |
|
| 4616 |
{
|
|
| 4617 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
|
| 4618 |
gen_op_load_gpr_T1(rS(ctx->opcode)); |
|
| 4619 |
gen_op_store_dcr(); |
|
| 4620 |
/* Note: Rc update flag set leads to undefined state of Rc0 */ |
|
| 4621 |
} |
|
| 4622 |
|
|
| 4498 | 4623 |
/* dccci */ |
| 4499 | 4624 |
GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON) |
| 4500 | 4625 |
{
|
| ... | ... | |
| 4595 | 4720 |
|
| 4596 | 4721 |
/* BookE specific */ |
| 4597 | 4722 |
/* XXX: not implemented on 440 ? */ |
| 4598 |
GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE) |
|
| 4723 |
GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT)
|
|
| 4599 | 4724 |
{
|
| 4600 | 4725 |
#if defined(CONFIG_USER_ONLY) |
| 4601 | 4726 |
RET_PRIVOPC(ctx); |
| ... | ... | |
| 4611 | 4736 |
} |
| 4612 | 4737 |
|
| 4613 | 4738 |
/* XXX: not implemented on 440 ? */ |
| 4614 |
GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_BOOKE)
|
|
| 4739 |
GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
|
|
| 4615 | 4740 |
{
|
| 4616 | 4741 |
#if defined(CONFIG_USER_ONLY) |
| 4617 | 4742 |
RET_PRIVOPC(ctx); |
| ... | ... | |
| 4628 | 4753 |
|
| 4629 | 4754 |
/* TLB management - PowerPC 405 implementation */ |
| 4630 | 4755 |
/* tlbre */ |
| 4631 |
GEN_HANDLER(tlbre_40x, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_SPEC)
|
|
| 4756 |
GEN_HANDLER(tlbre_40x, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
|
|
| 4632 | 4757 |
{
|
| 4633 | 4758 |
#if defined(CONFIG_USER_ONLY) |
| 4634 | 4759 |
RET_PRIVOPC(ctx); |
| ... | ... | |
| 4656 | 4781 |
} |
| 4657 | 4782 |
|
| 4658 | 4783 |
/* tlbsx - tlbsx. */ |
| 4659 |
GEN_HANDLER(tlbsx_40x, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_SPEC)
|
|
| 4784 |
GEN_HANDLER(tlbsx_40x, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
|
|
| 4660 | 4785 |
{
|
| 4661 | 4786 |
#if defined(CONFIG_USER_ONLY) |
| 4662 | 4787 |
RET_PRIVOPC(ctx); |
| ... | ... | |
| 4675 | 4800 |
} |
| 4676 | 4801 |
|
| 4677 | 4802 |
/* tlbwe */ |
| 4678 |
GEN_HANDLER(tlbwe_40x, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_SPEC)
|
|
| 4803 |
GEN_HANDLER(tlbwe_40x, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
|
|
| 4679 | 4804 |
{
|
| 4680 | 4805 |
#if defined(CONFIG_USER_ONLY) |
| 4681 | 4806 |
RET_PRIVOPC(ctx); |
| ... | ... | |
| 5701 | 5826 |
for (i = 0; i < 32; i++) {
|
| 5702 | 5827 |
if ((i & (RGPL - 1)) == 0) |
| 5703 | 5828 |
cpu_fprintf(f, "GPR%02d", i); |
| 5704 |
cpu_fprintf(f, " " REGX, env->gpr[i]); |
|
| 5829 |
cpu_fprintf(f, " " REGX, (target_ulong)env->gpr[i]);
|
|
| 5705 | 5830 |
if ((i & (RGPL - 1)) == (RGPL - 1)) |
| 5706 | 5831 |
cpu_fprintf(f, "\n"); |
| 5707 | 5832 |
} |
Also available in: Unified diff