Revision a750fc0b target-ppc/translate_init.c
| b/target-ppc/translate_init.c | ||
|---|---|---|
| 32 | 32 |
uint32_t pvr; |
| 33 | 33 |
uint32_t pvr_mask; |
| 34 | 34 |
uint64_t insns_flags; |
| 35 |
uint32_t flags; |
|
| 36 | 35 |
uint64_t msr_mask; |
| 36 |
uint8_t mmu_model; |
|
| 37 |
uint8_t excp_model; |
|
| 38 |
uint8_t bus_model; |
|
| 39 |
uint8_t pad; |
|
| 40 |
void (*init_proc)(CPUPPCState *env); |
|
| 37 | 41 |
}; |
| 38 | 42 |
|
| 39 | 43 |
/* For user-mode emulation, we don't emulate any IRQ controller */ |
| 40 | 44 |
#if defined(CONFIG_USER_ONLY) |
| 41 |
#define PPC_IRQ_INIT_FN(name) \ |
|
| 42 |
static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \ |
|
| 43 |
{ \
|
|
| 45 |
#define PPC_IRQ_INIT_FN(name) \
|
|
| 46 |
static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
|
|
| 47 |
{ \
|
|
| 44 | 48 |
} |
| 45 | 49 |
#else |
| 46 |
#define PPC_IRQ_INIT_FN(name) \ |
|
| 50 |
#define PPC_IRQ_INIT_FN(name) \
|
|
| 47 | 51 |
void glue(glue(ppc, name),_irq_init) (CPUPPCState *env); |
| 48 | 52 |
#endif |
| 53 |
|
|
| 54 |
PPC_IRQ_INIT_FN(401); |
|
| 49 | 55 |
PPC_IRQ_INIT_FN(405); |
| 50 | 56 |
PPC_IRQ_INIT_FN(6xx); |
| 51 | 57 |
PPC_IRQ_INIT_FN(970); |
| ... | ... | |
| 285 | 291 |
RET_STOP(ctx); |
| 286 | 292 |
} |
| 287 | 293 |
#endif |
| 288 |
#endif /* !defined(CONFIG_USER_ONLY) */
|
|
| 294 |
#endif |
|
| 289 | 295 |
|
| 290 | 296 |
/* PowerPC 601 specific registers */ |
| 291 | 297 |
/* RTC */ |
| ... | ... | |
| 582 | 588 |
SPR_NOACCESS, SPR_NOACCESS, |
| 583 | 589 |
&spr_read_dbat, &spr_write_dbatl, |
| 584 | 590 |
0x00000000); |
| 585 |
env->nb_BATs = 4; |
|
| 591 |
env->nb_BATs += 4;
|
|
| 586 | 592 |
} |
| 587 | 593 |
|
| 588 | 594 |
/* BATs 4-7 */ |
| ... | ... | |
| 652 | 658 |
SPR_NOACCESS, SPR_NOACCESS, |
| 653 | 659 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
| 654 | 660 |
0x00000000); |
| 655 |
env->nb_BATs = 8;
|
|
| 661 |
env->nb_BATs += 4;
|
|
| 656 | 662 |
} |
| 657 | 663 |
|
| 658 | 664 |
/* Generic PowerPC time base */ |
| ... | ... | |
| 797 | 803 |
&spr_read_generic, &spr_write_generic, |
| 798 | 804 |
0x00000000); |
| 799 | 805 |
/* XXX : not implemented */ |
| 800 |
spr_register(env, SPR_SIA, "SIA",
|
|
| 806 |
spr_register(env, SPR_SIAR, "SIAR",
|
|
| 801 | 807 |
SPR_NOACCESS, SPR_NOACCESS, |
| 802 | 808 |
&spr_read_generic, SPR_NOACCESS, |
| 803 | 809 |
0x00000000); |
| ... | ... | |
| 825 | 831 |
&spr_read_ureg, SPR_NOACCESS, |
| 826 | 832 |
&spr_read_ureg, SPR_NOACCESS, |
| 827 | 833 |
0x00000000); |
| 828 |
spr_register(env, SPR_USIA, "USIA",
|
|
| 834 |
spr_register(env, SPR_USIAR, "USIAR",
|
|
| 829 | 835 |
&spr_read_ureg, SPR_NOACCESS, |
| 830 | 836 |
&spr_read_ureg, SPR_NOACCESS, |
| 831 | 837 |
0x00000000); |
| 832 |
/* Thermal management */
|
|
| 838 |
/* External access control */
|
|
| 833 | 839 |
/* XXX : not implemented */ |
| 834 |
spr_register(env, SPR_THRM1, "THRM1",
|
|
| 840 |
spr_register(env, SPR_EAR, "EAR",
|
|
| 835 | 841 |
SPR_NOACCESS, SPR_NOACCESS, |
| 836 | 842 |
&spr_read_generic, &spr_write_generic, |
| 837 | 843 |
0x00000000); |
| 844 |
} |
|
| 845 |
|
|
| 846 |
static void gen_spr_thrm (CPUPPCState *env) |
|
| 847 |
{
|
|
| 848 |
/* Thermal management */ |
|
| 838 | 849 |
/* XXX : not implemented */ |
| 839 |
spr_register(env, SPR_THRM2, "THRM2",
|
|
| 850 |
spr_register(env, SPR_THRM1, "THRM1",
|
|
| 840 | 851 |
SPR_NOACCESS, SPR_NOACCESS, |
| 841 | 852 |
&spr_read_generic, &spr_write_generic, |
| 842 | 853 |
0x00000000); |
| 843 | 854 |
/* XXX : not implemented */ |
| 844 |
spr_register(env, SPR_THRM3, "THRM3",
|
|
| 855 |
spr_register(env, SPR_THRM2, "THRM2",
|
|
| 845 | 856 |
SPR_NOACCESS, SPR_NOACCESS, |
| 846 | 857 |
&spr_read_generic, &spr_write_generic, |
| 847 | 858 |
0x00000000); |
| 848 |
/* External access control */ |
|
| 849 | 859 |
/* XXX : not implemented */ |
| 850 |
spr_register(env, SPR_EAR, "EAR",
|
|
| 860 |
spr_register(env, SPR_THRM3, "THRM3",
|
|
| 851 | 861 |
SPR_NOACCESS, SPR_NOACCESS, |
| 852 | 862 |
&spr_read_generic, &spr_write_generic, |
| 853 | 863 |
0x00000000); |
| ... | ... | |
| 904 | 914 |
&spr_read_generic, &spr_write_generic, |
| 905 | 915 |
0x00000000); |
| 906 | 916 |
/* XXX : not implemented */ |
| 907 |
spr_register(env, SPR_SIA, "SIA",
|
|
| 917 |
spr_register(env, SPR_SIAR, "SIAR",
|
|
| 908 | 918 |
SPR_NOACCESS, SPR_NOACCESS, |
| 909 | 919 |
&spr_read_generic, SPR_NOACCESS, |
| 910 | 920 |
0x00000000); |
| ... | ... | |
| 1004 | 1014 |
&spr_read_generic, &spr_write_generic, |
| 1005 | 1015 |
0x00000000); |
| 1006 | 1016 |
/* XXX : not implemented */ |
| 1007 |
spr_register(env, SPR_ESASR, "ESASR",
|
|
| 1017 |
spr_register(env, SPR_ESASRR, "ESASRR",
|
|
| 1008 | 1018 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1009 | 1019 |
&spr_read_generic, &spr_write_generic, |
| 1010 | 1020 |
0x00000000); |
| ... | ... | |
| 1030 | 1040 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1031 | 1041 |
&spr_read_generic, &spr_write_generic, |
| 1032 | 1042 |
0x00000000); |
| 1043 |
/* XXX : not implemented */ |
|
| 1044 |
spr_register(env, SPR_IABR, "IABR", |
|
| 1045 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1046 |
&spr_read_generic, &spr_write_generic, |
|
| 1047 |
0x00000000); |
|
| 1033 | 1048 |
} |
| 1034 | 1049 |
|
| 1035 | 1050 |
/* SPR specific to PowerPC 601 implementation */ |
| ... | ... | |
| 1104 | 1119 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1105 | 1120 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
| 1106 | 1121 |
0x00000000); |
| 1122 |
env->nb_BATs = 4; |
|
| 1123 |
} |
|
| 1124 |
|
|
| 1125 |
static void gen_spr_74xx (CPUPPCState *env) |
|
| 1126 |
{
|
|
| 1127 |
/* Processor identification */ |
|
| 1128 |
spr_register(env, SPR_PIR, "PIR", |
|
| 1129 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1130 |
&spr_read_generic, &spr_write_pir, |
|
| 1131 |
0x00000000); |
|
| 1132 |
/* XXX : not implemented */ |
|
| 1133 |
spr_register(env, SPR_MMCR2, "MMCR2", |
|
| 1134 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1135 |
&spr_read_generic, &spr_write_generic, |
|
| 1136 |
0x00000000); |
|
| 1137 |
spr_register(env, SPR_UMMCR2, "UMMCR2", |
|
| 1138 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1139 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1140 |
0x00000000); |
|
| 1141 |
/* XXX: not implemented */ |
|
| 1142 |
spr_register(env, SPR_BAMR, "BAMR", |
|
| 1143 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1144 |
&spr_read_generic, &spr_write_generic, |
|
| 1145 |
0x00000000); |
|
| 1146 |
spr_register(env, SPR_UBAMR, "UBAMR", |
|
| 1147 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1148 |
&spr_read_ureg, SPR_NOACCESS, |
|
| 1149 |
0x00000000); |
|
| 1150 |
spr_register(env, SPR_MSSCR0, "MSSCR0", |
|
| 1151 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1152 |
&spr_read_generic, &spr_write_generic, |
|
| 1153 |
0x00000000); |
|
| 1154 |
/* Hardware implementation registers */ |
|
| 1155 |
/* XXX : not implemented */ |
|
| 1156 |
spr_register(env, SPR_HID0, "HID0", |
|
| 1157 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1158 |
&spr_read_generic, &spr_write_generic, |
|
| 1159 |
0x00000000); |
|
| 1160 |
/* XXX : not implemented */ |
|
| 1161 |
spr_register(env, SPR_HID1, "HID1", |
|
| 1162 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1163 |
&spr_read_generic, &spr_write_generic, |
|
| 1164 |
0x00000000); |
|
| 1165 |
/* Altivec */ |
|
| 1166 |
spr_register(env, SPR_VRSAVE, "VRSAVE", |
|
| 1167 |
&spr_read_generic, &spr_write_generic, |
|
| 1168 |
&spr_read_generic, &spr_write_generic, |
|
| 1169 |
0x00000000); |
|
| 1170 |
} |
|
| 1171 |
|
|
| 1172 |
#if defined (TODO) |
|
| 1173 |
static void gen_l3_ctrl (CPUPPCState *env) |
|
| 1174 |
{
|
|
| 1175 |
/* L3CR */ |
|
| 1176 |
/* XXX : not implemented */ |
|
| 1177 |
spr_register(env, SPR_L3CR, "L3CR", |
|
| 1178 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1179 |
&spr_read_generic, &spr_write_generic, |
|
| 1180 |
0x00000000); |
|
| 1181 |
/* L3ITCR0 */ |
|
| 1182 |
spr_register(env, SPR_L3ITCR0, "L3ITCR0", |
|
| 1183 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1184 |
&spr_read_generic, &spr_write_generic, |
|
| 1185 |
0x00000000); |
|
| 1186 |
/* L3ITCR1 */ |
|
| 1187 |
spr_register(env, SPR_L3ITCR1, "L3ITCR1", |
|
| 1188 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1189 |
&spr_read_generic, &spr_write_generic, |
|
| 1190 |
0x00000000); |
|
| 1191 |
/* L3ITCR2 */ |
|
| 1192 |
spr_register(env, SPR_L3ITCR2, "L3ITCR2", |
|
| 1193 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1194 |
&spr_read_generic, &spr_write_generic, |
|
| 1195 |
0x00000000); |
|
| 1196 |
/* L3ITCR3 */ |
|
| 1197 |
spr_register(env, SPR_L3ITCR3, "L3ITCR3", |
|
| 1198 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1199 |
&spr_read_generic, &spr_write_generic, |
|
| 1200 |
0x00000000); |
|
| 1201 |
/* L3OHCR */ |
|
| 1202 |
spr_register(env, SPR_L3OHCR, "L3OHCR", |
|
| 1203 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1204 |
&spr_read_generic, &spr_write_generic, |
|
| 1205 |
0x00000000); |
|
| 1206 |
/* L3PM */ |
|
| 1207 |
spr_register(env, SPR_L3PM, "L3PM", |
|
| 1208 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1209 |
&spr_read_generic, &spr_write_generic, |
|
| 1210 |
0x00000000); |
|
| 1211 |
} |
|
| 1212 |
#endif /* TODO */ |
|
| 1213 |
|
|
| 1214 |
#if defined (TODO) |
|
| 1215 |
static void gen_74xx_soft_tlb (CPUPPCState *env) |
|
| 1216 |
{
|
|
| 1217 |
/* XXX: TODO */ |
|
| 1218 |
spr_register(env, SPR_PTEHI, "PTEHI", |
|
| 1219 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1220 |
&spr_read_generic, &spr_write_generic, |
|
| 1221 |
0x00000000); |
|
| 1222 |
spr_register(env, SPR_PTELO, "PTELO", |
|
| 1223 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1224 |
&spr_read_generic, &spr_write_generic, |
|
| 1225 |
0x00000000); |
|
| 1226 |
spr_register(env, SPR_TLBMISS, "TLBMISS", |
|
| 1227 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1228 |
&spr_read_generic, &spr_write_generic, |
|
| 1229 |
0x00000000); |
|
| 1107 | 1230 |
} |
| 1231 |
#endif /* TODO */ |
|
| 1108 | 1232 |
|
| 1109 | 1233 |
/* PowerPC BookE SPR */ |
| 1110 | 1234 |
static void gen_spr_BookE (CPUPPCState *env) |
| ... | ... | |
| 1132 | 1256 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1133 | 1257 |
&spr_read_generic, &spr_write_generic, |
| 1134 | 1258 |
0x00000000); |
| 1135 |
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", |
|
| 1136 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1137 |
&spr_read_generic, &spr_write_generic, |
|
| 1138 |
0x00000000); |
|
| 1139 |
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", |
|
| 1140 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1141 |
&spr_read_generic, &spr_write_generic, |
|
| 1142 |
0x00000000); |
|
| 1143 | 1259 |
#endif |
| 1144 | 1260 |
/* Debug */ |
| 1145 | 1261 |
/* XXX : not implemented */ |
| ... | ... | |
| 1366 | 1482 |
} |
| 1367 | 1483 |
|
| 1368 | 1484 |
/* FSL storage control registers */ |
| 1485 |
#if defined(TODO) |
|
| 1369 | 1486 |
static void gen_spr_BookE_FSL (CPUPPCState *env) |
| 1370 | 1487 |
{
|
| 1371 | 1488 |
/* TLB assist registers */ |
| ... | ... | |
| 1447 | 1564 |
break; |
| 1448 | 1565 |
} |
| 1449 | 1566 |
} |
| 1567 |
#endif |
|
| 1450 | 1568 |
|
| 1451 | 1569 |
/* SPR specific to PowerPC 440 implementation */ |
| 1452 | 1570 |
static void gen_spr_440 (CPUPPCState *env) |
| ... | ... | |
| 1599 | 1717 |
&spr_read_generic, &spr_write_generic, |
| 1600 | 1718 |
0x00000000); |
| 1601 | 1719 |
/* XXX : not implemented */ |
| 1602 |
spr_register(env, SPR_40x_DCWR, "DCWR", |
|
| 1603 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1604 |
&spr_read_generic, &spr_write_generic, |
|
| 1605 |
0x00000000); |
|
| 1606 |
/* XXX : not implemented */ |
|
| 1607 | 1720 |
spr_register(env, SPR_40x_ICCR, "ICCR", |
| 1608 | 1721 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1609 | 1722 |
&spr_read_generic, &spr_write_generic, |
| ... | ... | |
| 1613 | 1726 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1614 | 1727 |
&spr_read_generic, SPR_NOACCESS, |
| 1615 | 1728 |
0x00000000); |
| 1616 |
/* Bus access control */ |
|
| 1617 |
spr_register(env, SPR_40x_SGR, "SGR", |
|
| 1618 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1619 |
&spr_read_generic, &spr_write_generic, |
|
| 1620 |
0xFFFFFFFF); |
|
| 1621 | 1729 |
/* Exception */ |
| 1622 | 1730 |
spr_register(env, SPR_40x_DEAR, "DEAR", |
| 1623 | 1731 |
SPR_NOACCESS, SPR_NOACCESS, |
| ... | ... | |
| 1834 | 1942 |
0x00000000); |
| 1835 | 1943 |
} |
| 1836 | 1944 |
|
| 1945 |
static void gen_spr_401x2 (CPUPPCState *env) |
|
| 1946 |
{
|
|
| 1947 |
gen_spr_401(env); |
|
| 1948 |
spr_register(env, SPR_40x_PID, "PID", |
|
| 1949 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1950 |
&spr_read_generic, &spr_write_generic, |
|
| 1951 |
0x00000000); |
|
| 1952 |
spr_register(env, SPR_40x_ZPR, "ZPR", |
|
| 1953 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1954 |
&spr_read_generic, &spr_write_generic, |
|
| 1955 |
0x00000000); |
|
| 1956 |
} |
|
| 1957 |
|
|
| 1837 | 1958 |
/* SPR specific to PowerPC 403 implementation */ |
| 1838 | 1959 |
static void gen_spr_403 (CPUPPCState *env) |
| 1839 | 1960 |
{
|
| ... | ... | |
| 1867 | 1988 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1868 | 1989 |
&spr_read_generic, &spr_write_generic, |
| 1869 | 1990 |
0x00000000); |
| 1870 |
/* MMU */ |
|
| 1871 |
spr_register(env, SPR_40x_PID, "PID", |
|
| 1872 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1873 |
&spr_read_generic, &spr_write_generic, |
|
| 1874 |
0x00000000); |
|
| 1991 |
} |
|
| 1992 |
|
|
| 1993 |
static void gen_spr_403_real (CPUPPCState *env) |
|
| 1994 |
{
|
|
| 1875 | 1995 |
spr_register(env, SPR_403_PBL1, "PBL1", |
| 1876 | 1996 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1877 | 1997 |
&spr_read_403_pbr, &spr_write_403_pbr, |
| ... | ... | |
| 1888 | 2008 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1889 | 2009 |
&spr_read_403_pbr, &spr_write_403_pbr, |
| 1890 | 2010 |
0x00000000); |
| 2011 |
} |
|
| 2012 |
|
|
| 2013 |
static void gen_spr_403_mmu (CPUPPCState *env) |
|
| 2014 |
{
|
|
| 2015 |
/* MMU */ |
|
| 2016 |
spr_register(env, SPR_40x_PID, "PID", |
|
| 2017 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2018 |
&spr_read_generic, &spr_write_generic, |
|
| 2019 |
0x00000000); |
|
| 1891 | 2020 |
spr_register(env, SPR_40x_ZPR, "ZPR", |
| 1892 | 2021 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1893 | 2022 |
&spr_read_generic, &spr_write_generic, |
| ... | ... | |
| 1895 | 2024 |
} |
| 1896 | 2025 |
|
| 1897 | 2026 |
/* SPR specific to PowerPC compression coprocessor extension */ |
| 1898 |
#if defined (TODO) |
|
| 1899 | 2027 |
static void gen_spr_compress (CPUPPCState *env) |
| 1900 | 2028 |
{
|
| 1901 | 2029 |
spr_register(env, SPR_401_SKR, "SKR", |
| ... | ... | |
| 1903 | 2031 |
&spr_read_generic, &spr_write_generic, |
| 1904 | 2032 |
0x00000000); |
| 1905 | 2033 |
} |
| 2034 |
|
|
| 2035 |
#if defined (TARGET_PPC64) |
|
| 2036 |
#if defined (TODO) |
|
| 2037 |
/* SPR specific to PowerPC 620 */ |
|
| 2038 |
static void gen_spr_620 (CPUPPCState *env) |
|
| 2039 |
{
|
|
| 2040 |
spr_register(env, SPR_620_PMR0, "PMR0", |
|
| 2041 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2042 |
&spr_read_generic, &spr_write_generic, |
|
| 2043 |
0x00000000); |
|
| 2044 |
spr_register(env, SPR_620_PMR1, "PMR1", |
|
| 2045 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2046 |
&spr_read_generic, &spr_write_generic, |
|
| 2047 |
0x00000000); |
|
| 2048 |
spr_register(env, SPR_620_PMR2, "PMR2", |
|
| 2049 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2050 |
&spr_read_generic, &spr_write_generic, |
|
| 2051 |
0x00000000); |
|
| 2052 |
spr_register(env, SPR_620_PMR3, "PMR3", |
|
| 2053 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2054 |
&spr_read_generic, &spr_write_generic, |
|
| 2055 |
0x00000000); |
|
| 2056 |
spr_register(env, SPR_620_PMR4, "PMR4", |
|
| 2057 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2058 |
&spr_read_generic, &spr_write_generic, |
|
| 2059 |
0x00000000); |
|
| 2060 |
spr_register(env, SPR_620_PMR5, "PMR5", |
|
| 2061 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2062 |
&spr_read_generic, &spr_write_generic, |
|
| 2063 |
0x00000000); |
|
| 2064 |
spr_register(env, SPR_620_PMR6, "PMR6", |
|
| 2065 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2066 |
&spr_read_generic, &spr_write_generic, |
|
| 2067 |
0x00000000); |
|
| 2068 |
spr_register(env, SPR_620_PMR7, "PMR7", |
|
| 2069 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2070 |
&spr_read_generic, &spr_write_generic, |
|
| 2071 |
0x00000000); |
|
| 2072 |
spr_register(env, SPR_620_PMR8, "PMR8", |
|
| 2073 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2074 |
&spr_read_generic, &spr_write_generic, |
|
| 2075 |
0x00000000); |
|
| 2076 |
spr_register(env, SPR_620_PMR9, "PMR9", |
|
| 2077 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2078 |
&spr_read_generic, &spr_write_generic, |
|
| 2079 |
0x00000000); |
|
| 2080 |
spr_register(env, SPR_620_PMRA, "PMR10", |
|
| 2081 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2082 |
&spr_read_generic, &spr_write_generic, |
|
| 2083 |
0x00000000); |
|
| 2084 |
spr_register(env, SPR_620_PMRB, "PMR11", |
|
| 2085 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2086 |
&spr_read_generic, &spr_write_generic, |
|
| 2087 |
0x00000000); |
|
| 2088 |
spr_register(env, SPR_620_PMRC, "PMR12", |
|
| 2089 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2090 |
&spr_read_generic, &spr_write_generic, |
|
| 2091 |
0x00000000); |
|
| 2092 |
spr_register(env, SPR_620_PMRD, "PMR13", |
|
| 2093 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2094 |
&spr_read_generic, &spr_write_generic, |
|
| 2095 |
0x00000000); |
|
| 2096 |
spr_register(env, SPR_620_PMRE, "PMR14", |
|
| 2097 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2098 |
&spr_read_generic, &spr_write_generic, |
|
| 2099 |
0x00000000); |
|
| 2100 |
spr_register(env, SPR_620_PMRF, "PMR15", |
|
| 2101 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2102 |
&spr_read_generic, &spr_write_generic, |
|
| 2103 |
0x00000000); |
|
| 2104 |
spr_register(env, SPR_620_HID8, "HID8", |
|
| 2105 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2106 |
&spr_read_generic, &spr_write_generic, |
|
| 2107 |
0x00000000); |
|
| 2108 |
spr_register(env, SPR_620_HID9, "HID9", |
|
| 2109 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2110 |
&spr_read_generic, &spr_write_generic, |
|
| 2111 |
0x00000000); |
|
| 2112 |
} |
|
| 1906 | 2113 |
#endif |
| 2114 |
#endif /* defined (TARGET_PPC64) */ |
|
| 1907 | 2115 |
|
| 1908 | 2116 |
// XXX: TODO |
| 1909 | 2117 |
/* |
| 1910 | 2118 |
* AMR => SPR 29 (Power 2.04) |
| 1911 | 2119 |
* CTRL => SPR 136 (Power 2.04) |
| 1912 | 2120 |
* CTRL => SPR 152 (Power 2.04) |
| 1913 |
* VRSAVE => SPR 256 (Altivec) |
|
| 1914 | 2121 |
* SCOMC => SPR 276 (64 bits ?) |
| 1915 | 2122 |
* SCOMD => SPR 277 (64 bits ?) |
| 1916 | 2123 |
* ASR => SPR 280 (64 bits) |
| ... | ... | |
| 1942 | 2149 |
* ... and more (thermal management, performance counters, ...) |
| 1943 | 2150 |
*/ |
| 1944 | 2151 |
|
| 1945 |
static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) |
|
| 1946 |
{
|
|
| 1947 |
env->reserve = -1; |
|
| 1948 |
/* Default MMU definitions */ |
|
| 1949 |
env->nb_BATs = -1; |
|
| 1950 |
env->nb_tlb = 0; |
|
| 1951 |
env->nb_ways = 0; |
|
| 1952 |
/* XXX: missing: |
|
| 1953 |
* 32 bits PowerPC: |
|
| 1954 |
* - MPC5xx(x) |
|
| 1955 |
* - MPC8xx(x) |
|
| 1956 |
* - RCPU (same as MPC5xx ?) |
|
| 1957 |
*/ |
|
| 1958 |
spr_register(env, SPR_PVR, "PVR", |
|
| 1959 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1960 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1961 |
def->pvr); |
|
| 1962 |
printf("%s: PVR %08x mask %08x => %08x\n", __func__,
|
|
| 1963 |
def->pvr, def->pvr_mask, def->pvr & def->pvr_mask); |
|
| 1964 |
switch (def->pvr) {
|
|
| 1965 |
/* Embedded PowerPC from IBM */ |
|
| 1966 |
case CPU_PPC_401A1: /* 401 A1 family */ |
|
| 1967 |
case CPU_PPC_401B2: /* 401 B2 family */ |
|
| 1968 |
#if 0 |
|
| 1969 |
case CPU_PPC_401B3: /* 401 B3 family */ |
|
| 1970 |
#endif |
|
| 1971 |
case CPU_PPC_401C2: /* 401 C2 family */ |
|
| 1972 |
case CPU_PPC_401D2: /* 401 D2 family */ |
|
| 1973 |
case CPU_PPC_401E2: /* 401 E2 family */ |
|
| 1974 |
case CPU_PPC_401F2: /* 401 F2 family */ |
|
| 1975 |
case CPU_PPC_401G2: /* 401 G2 family */ |
|
| 1976 |
case CPU_PPC_IOP480: /* IOP 480 family */ |
|
| 1977 |
case CPU_PPC_COBRA: /* IBM Processor for Network Resources */ |
|
| 1978 |
gen_spr_generic(env); |
|
| 1979 |
gen_spr_40x(env); |
|
| 1980 |
gen_spr_401_403(env); |
|
| 1981 |
gen_spr_401(env); |
|
| 1982 |
#if defined (TODO) |
|
| 1983 |
/* XXX: optional ? */ |
|
| 1984 |
gen_spr_compress(env); |
|
| 1985 |
#endif |
|
| 1986 |
env->nb_BATs = 0; |
|
| 1987 |
env->nb_tlb = 64; |
|
| 1988 |
env->nb_ways = 1; |
|
| 1989 |
env->id_tlbs = 0; |
|
| 1990 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 1991 |
break; |
|
| 1992 |
|
|
| 1993 |
case CPU_PPC_403GA: /* 403 GA family */ |
|
| 1994 |
case CPU_PPC_403GB: /* 403 GB family */ |
|
| 1995 |
case CPU_PPC_403GC: /* 403 GC family */ |
|
| 1996 |
case CPU_PPC_403GCX: /* 403 GCX family */ |
|
| 1997 |
gen_spr_generic(env); |
|
| 1998 |
gen_spr_40x(env); |
|
| 1999 |
gen_spr_401_403(env); |
|
| 2000 |
gen_spr_403(env); |
|
| 2001 |
env->nb_BATs = 0; |
|
| 2002 |
env->nb_tlb = 64; |
|
| 2003 |
env->nb_ways = 1; |
|
| 2004 |
env->id_tlbs = 0; |
|
| 2005 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 2006 |
break; |
|
| 2007 |
|
|
| 2008 |
case CPU_PPC_405CR: /* 405 GP/CR family */ |
|
| 2009 |
case CPU_PPC_405EP: /* 405 EP family */ |
|
| 2010 |
case CPU_PPC_405GPR: /* 405 GPR family */ |
|
| 2011 |
case CPU_PPC_405D2: /* 405 D2 family */ |
|
| 2012 |
case CPU_PPC_405D4: /* 405 D4 family */ |
|
| 2013 |
gen_spr_generic(env); |
|
| 2014 |
/* Time base */ |
|
| 2015 |
gen_tbl(env); |
|
| 2016 |
gen_spr_40x(env); |
|
| 2017 |
gen_spr_405(env); |
|
| 2018 |
env->nb_BATs = 0; |
|
| 2019 |
env->nb_tlb = 64; |
|
| 2020 |
env->nb_ways = 1; |
|
| 2021 |
env->id_tlbs = 0; |
|
| 2022 |
/* Allocate hardware IRQ controller */ |
|
| 2023 |
ppc405_irq_init(env); |
|
| 2024 |
break; |
|
| 2152 |
/*****************************************************************************/ |
|
| 2153 |
/* PowerPC implementations definitions */ |
|
| 2025 | 2154 |
|
| 2026 |
case CPU_PPC_NPE405H: /* NPe405 H family */ |
|
| 2027 |
case CPU_PPC_NPE405H2: |
|
| 2028 |
case CPU_PPC_NPE405L: /* Npe405 L family */ |
|
| 2029 |
gen_spr_generic(env); |
|
| 2030 |
/* Time base */ |
|
| 2031 |
gen_tbl(env); |
|
| 2032 |
gen_spr_40x(env); |
|
| 2033 |
gen_spr_405(env); |
|
| 2034 |
env->nb_BATs = 0; |
|
| 2035 |
env->nb_tlb = 64; |
|
| 2036 |
env->nb_ways = 1; |
|
| 2037 |
env->id_tlbs = 0; |
|
| 2038 |
/* Allocate hardware IRQ controller */ |
|
| 2039 |
ppc405_irq_init(env); |
|
| 2040 |
break; |
|
| 2155 |
/* PowerPC 40x instruction set */ |
|
| 2156 |
#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON) |
|
| 2041 | 2157 |
|
| 2042 |
#if defined (TODO) |
|
| 2043 |
case CPU_PPC_STB01000: |
|
| 2044 |
#endif |
|
| 2045 |
#if defined (TODO) |
|
| 2046 |
case CPU_PPC_STB01010: |
|
| 2047 |
#endif |
|
| 2048 |
#if defined (TODO) |
|
| 2049 |
case CPU_PPC_STB0210: |
|
| 2050 |
#endif |
|
| 2051 |
case CPU_PPC_STB03: /* STB03 family */ |
|
| 2052 |
#if defined (TODO) |
|
| 2053 |
case CPU_PPC_STB043: /* STB043 family */ |
|
| 2054 |
#endif |
|
| 2055 |
#if defined (TODO) |
|
| 2056 |
case CPU_PPC_STB045: /* STB045 family */ |
|
| 2057 |
#endif |
|
| 2058 |
case CPU_PPC_STB25: /* STB25 family */ |
|
| 2059 |
#if defined (TODO) |
|
| 2060 |
case CPU_PPC_STB130: /* STB130 family */ |
|
| 2061 |
#endif |
|
| 2062 |
gen_spr_generic(env); |
|
| 2063 |
/* Time base */ |
|
| 2064 |
gen_tbl(env); |
|
| 2065 |
gen_spr_40x(env); |
|
| 2066 |
gen_spr_405(env); |
|
| 2067 |
env->nb_BATs = 0; |
|
| 2068 |
env->nb_tlb = 64; |
|
| 2069 |
env->nb_ways = 1; |
|
| 2070 |
env->id_tlbs = 0; |
|
| 2071 |
/* Allocate hardware IRQ controller */ |
|
| 2072 |
ppc405_irq_init(env); |
|
| 2073 |
break; |
|
| 2158 |
/* PowerPC 401 */ |
|
| 2159 |
#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \ |
|
| 2160 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 2161 |
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) |
|
| 2162 |
#define POWERPC_MSRM_401 (0x00000000000FD201ULL) |
|
| 2163 |
#define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx) |
|
| 2164 |
#define POWERPC_EXCP_401 (POWERPC_EXCP_40x) |
|
| 2165 |
#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401) |
|
| 2074 | 2166 |
|
| 2075 |
case CPU_PPC_440EP: /* 440 EP family */ |
|
| 2076 |
case CPU_PPC_440GP: /* 440 GP family */ |
|
| 2077 |
case CPU_PPC_440GX: /* 440 GX family */ |
|
| 2078 |
case CPU_PPC_440GXc: /* 440 GXc family */ |
|
| 2079 |
case CPU_PPC_440GXf: /* 440 GXf family */ |
|
| 2080 |
case CPU_PPC_440SP: /* 440 SP family */ |
|
| 2081 |
case CPU_PPC_440SP2: |
|
| 2082 |
case CPU_PPC_440SPE: /* 440 SPE family */ |
|
| 2083 |
gen_spr_generic(env); |
|
| 2084 |
/* Time base */ |
|
| 2085 |
gen_tbl(env); |
|
| 2086 |
gen_spr_BookE(env); |
|
| 2087 |
gen_spr_440(env); |
|
| 2088 |
env->nb_BATs = 0; |
|
| 2089 |
env->nb_tlb = 64; |
|
| 2090 |
env->nb_ways = 1; |
|
| 2091 |
env->id_tlbs = 0; |
|
| 2092 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 2093 |
break; |
|
| 2167 |
static void init_proc_401 (CPUPPCState *env) |
|
| 2168 |
{
|
|
| 2169 |
gen_spr_40x(env); |
|
| 2170 |
gen_spr_401_403(env); |
|
| 2171 |
gen_spr_401(env); |
|
| 2172 |
/* Bus access control */ |
|
| 2173 |
spr_register(env, SPR_40x_SGR, "SGR", |
|
| 2174 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2175 |
&spr_read_generic, &spr_write_generic, |
|
| 2176 |
0xFFFFFFFF); |
|
| 2177 |
/* XXX : not implemented */ |
|
| 2178 |
spr_register(env, SPR_40x_DCWR, "DCWR", |
|
| 2179 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2180 |
&spr_read_generic, &spr_write_generic, |
|
| 2181 |
0x00000000); |
|
| 2182 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 2183 |
} |
|
| 2094 | 2184 |
|
| 2095 |
/* Embedded PowerPC from Freescale */ |
|
| 2096 |
#if defined (TODO) |
|
| 2097 |
case CPU_PPC_5xx: |
|
| 2098 |
break; |
|
| 2099 |
#endif |
|
| 2100 |
#if defined (TODO) |
|
| 2101 |
case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */ |
|
| 2102 |
break; |
|
| 2103 |
#endif |
|
| 2104 |
#if defined (TODO) |
|
| 2105 |
case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */ |
|
| 2106 |
case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */ |
|
| 2107 |
break; |
|
| 2108 |
#endif |
|
| 2109 |
#if defined (TODO) |
|
| 2110 |
case CPU_PPC_827x: /* MPC 827x / 828x */ |
|
| 2111 |
break; |
|
| 2112 |
#endif |
|
| 2113 |
|
|
| 2114 |
/* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */ |
|
| 2115 |
case CPU_PPC_e500v110: |
|
| 2116 |
case CPU_PPC_e500v120: |
|
| 2117 |
case CPU_PPC_e500v210: |
|
| 2118 |
case CPU_PPC_e500v220: |
|
| 2119 |
gen_spr_generic(env); |
|
| 2120 |
/* Time base */ |
|
| 2121 |
gen_tbl(env); |
|
| 2122 |
gen_spr_BookE(env); |
|
| 2123 |
gen_spr_BookE_FSL(env); |
|
| 2124 |
env->nb_BATs = 0; |
|
| 2125 |
env->nb_tlb = 64; |
|
| 2126 |
env->nb_ways = 1; |
|
| 2127 |
env->id_tlbs = 0; |
|
| 2128 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 2129 |
break; |
|
| 2130 |
|
|
| 2131 |
#if defined (TODO) |
|
| 2132 |
case CPU_PPC_e600: |
|
| 2133 |
break; |
|
| 2134 |
#endif |
|
| 2135 |
|
|
| 2136 |
/* 32 bits PowerPC */ |
|
| 2137 |
case CPU_PPC_601: /* PowerPC 601 */ |
|
| 2138 |
gen_spr_generic(env); |
|
| 2139 |
gen_spr_ne_601(env); |
|
| 2140 |
gen_spr_601(env); |
|
| 2141 |
/* Hardware implementation registers */ |
|
| 2142 |
/* XXX : not implemented */ |
|
| 2143 |
spr_register(env, SPR_HID0, "HID0", |
|
| 2144 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2145 |
&spr_read_generic, &spr_write_generic, |
|
| 2146 |
0x00000000); |
|
| 2147 |
/* XXX : not implemented */ |
|
| 2148 |
spr_register(env, SPR_HID1, "HID1", |
|
| 2149 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2150 |
&spr_read_generic, &spr_write_generic, |
|
| 2151 |
0x00000000); |
|
| 2152 |
/* XXX : not implemented */ |
|
| 2153 |
spr_register(env, SPR_601_HID2, "HID2", |
|
| 2154 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2155 |
&spr_read_generic, &spr_write_generic, |
|
| 2156 |
0x00000000); |
|
| 2157 |
/* XXX : not implemented */ |
|
| 2158 |
spr_register(env, SPR_601_HID5, "HID5", |
|
| 2159 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2160 |
&spr_read_generic, &spr_write_generic, |
|
| 2161 |
0x00000000); |
|
| 2162 |
/* XXX : not implemented */ |
|
| 2163 |
#if 0 /* ? */ |
|
| 2164 |
spr_register(env, SPR_601_HID15, "HID15", |
|
| 2165 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2166 |
&spr_read_generic, &spr_write_generic, |
|
| 2167 |
0x00000000); |
|
| 2168 |
#endif |
|
| 2169 |
env->nb_tlb = 64; |
|
| 2170 |
env->nb_ways = 2; |
|
| 2171 |
env->id_tlbs = 0; |
|
| 2172 |
env->id_tlbs = 0; |
|
| 2173 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 2174 |
break; |
|
| 2175 |
|
|
| 2176 |
case CPU_PPC_602: /* PowerPC 602 */ |
|
| 2177 |
gen_spr_generic(env); |
|
| 2178 |
gen_spr_ne_601(env); |
|
| 2179 |
/* Memory management */ |
|
| 2180 |
gen_low_BATs(env); |
|
| 2181 |
/* Time base */ |
|
| 2182 |
gen_tbl(env); |
|
| 2183 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
|
| 2184 |
gen_spr_602(env); |
|
| 2185 |
/* hardware implementation registers */ |
|
| 2186 |
/* XXX : not implemented */ |
|
| 2187 |
spr_register(env, SPR_HID0, "HID0", |
|
| 2188 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2189 |
&spr_read_generic, &spr_write_generic, |
|
| 2190 |
0x00000000); |
|
| 2191 |
/* XXX : not implemented */ |
|
| 2192 |
spr_register(env, SPR_HID1, "HID1", |
|
| 2193 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2194 |
&spr_read_generic, &spr_write_generic, |
|
| 2195 |
0x00000000); |
|
| 2196 |
/* Allocate hardware IRQ controller */ |
|
| 2197 |
ppc6xx_irq_init(env); |
|
| 2198 |
break; |
|
| 2199 |
|
|
| 2200 |
case CPU_PPC_603: /* PowerPC 603 */ |
|
| 2201 |
case CPU_PPC_603E: /* PowerPC 603e */ |
|
| 2202 |
case CPU_PPC_603E7v: |
|
| 2203 |
case CPU_PPC_603E7v2: |
|
| 2204 |
case CPU_PPC_603P: /* PowerPC 603p */ |
|
| 2205 |
case CPU_PPC_603R: /* PowerPC 603r */ |
|
| 2206 |
gen_spr_generic(env); |
|
| 2207 |
gen_spr_ne_601(env); |
|
| 2208 |
/* Memory management */ |
|
| 2209 |
gen_low_BATs(env); |
|
| 2210 |
/* Time base */ |
|
| 2211 |
gen_tbl(env); |
|
| 2212 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
|
| 2213 |
gen_spr_603(env); |
|
| 2214 |
/* hardware implementation registers */ |
|
| 2215 |
/* XXX : not implemented */ |
|
| 2216 |
spr_register(env, SPR_HID0, "HID0", |
|
| 2217 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2218 |
&spr_read_generic, &spr_write_generic, |
|
| 2219 |
0x00000000); |
|
| 2220 |
/* XXX : not implemented */ |
|
| 2221 |
spr_register(env, SPR_HID1, "HID1", |
|
| 2222 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2223 |
&spr_read_generic, &spr_write_generic, |
|
| 2224 |
0x00000000); |
|
| 2225 |
/* Allocate hardware IRQ controller */ |
|
| 2226 |
ppc6xx_irq_init(env); |
|
| 2227 |
break; |
|
| 2228 |
|
|
| 2229 |
case CPU_PPC_G2: /* PowerPC G2 family */ |
|
| 2230 |
case CPU_PPC_G2H4: |
|
| 2231 |
case CPU_PPC_G2gp: |
|
| 2232 |
case CPU_PPC_G2ls: |
|
| 2233 |
case CPU_PPC_G2LE: /* PowerPC G2LE family */ |
|
| 2234 |
case CPU_PPC_G2LEgp: |
|
| 2235 |
case CPU_PPC_G2LEls: |
|
| 2236 |
gen_spr_generic(env); |
|
| 2237 |
gen_spr_ne_601(env); |
|
| 2238 |
/* Memory management */ |
|
| 2239 |
gen_low_BATs(env); |
|
| 2240 |
/* Time base */ |
|
| 2241 |
gen_tbl(env); |
|
| 2242 |
/* Memory management */ |
|
| 2243 |
gen_high_BATs(env); |
|
| 2244 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
|
| 2245 |
gen_spr_G2_755(env); |
|
| 2246 |
gen_spr_G2(env); |
|
| 2247 |
/* Hardware implementation register */ |
|
| 2248 |
/* XXX : not implemented */ |
|
| 2249 |
spr_register(env, SPR_HID0, "HID0", |
|
| 2250 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2251 |
&spr_read_generic, &spr_write_generic, |
|
| 2252 |
0x00000000); |
|
| 2253 |
/* XXX : not implemented */ |
|
| 2254 |
spr_register(env, SPR_HID1, "HID1", |
|
| 2255 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2256 |
&spr_read_generic, &spr_write_generic, |
|
| 2257 |
0x00000000); |
|
| 2258 |
/* XXX : not implemented */ |
|
| 2259 |
spr_register(env, SPR_HID2, "HID2", |
|
| 2260 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2261 |
&spr_read_generic, &spr_write_generic, |
|
| 2262 |
0x00000000); |
|
| 2263 |
/* Allocate hardware IRQ controller */ |
|
| 2264 |
ppc6xx_irq_init(env); |
|
| 2265 |
break; |
|
| 2266 |
|
|
| 2267 |
case CPU_PPC_604: /* PowerPC 604 */ |
|
| 2268 |
case CPU_PPC_604E: /* PowerPC 604e */ |
|
| 2269 |
case CPU_PPC_604R: /* PowerPC 604r */ |
|
| 2270 |
gen_spr_generic(env); |
|
| 2271 |
gen_spr_ne_601(env); |
|
| 2272 |
/* Memory management */ |
|
| 2273 |
gen_low_BATs(env); |
|
| 2274 |
/* Time base */ |
|
| 2275 |
gen_tbl(env); |
|
| 2276 |
gen_spr_604(env); |
|
| 2277 |
/* Hardware implementation registers */ |
|
| 2278 |
/* XXX : not implemented */ |
|
| 2279 |
spr_register(env, SPR_HID0, "HID0", |
|
| 2280 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2281 |
&spr_read_generic, &spr_write_generic, |
|
| 2282 |
0x00000000); |
|
| 2283 |
/* XXX : not implemented */ |
|
| 2284 |
spr_register(env, SPR_HID1, "HID1", |
|
| 2285 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2286 |
&spr_read_generic, &spr_write_generic, |
|
| 2287 |
0x00000000); |
|
| 2288 |
/* Allocate hardware IRQ controller */ |
|
| 2289 |
ppc6xx_irq_init(env); |
|
| 2290 |
break; |
|
| 2291 |
|
|
| 2292 |
case CPU_PPC_74x: /* PowerPC 740 / 750 */ |
|
| 2293 |
case CPU_PPC_740E: |
|
| 2294 |
case CPU_PPC_750E: |
|
| 2295 |
case CPU_PPC_74xP: /* PowerPC 740P / 750P */ |
|
| 2296 |
case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe */ |
|
| 2297 |
case CPU_PPC_750CXE22: |
|
| 2298 |
case CPU_PPC_750CXE23: |
|
| 2299 |
case CPU_PPC_750CXE24: |
|
| 2300 |
case CPU_PPC_750CXE24b: |
|
| 2301 |
case CPU_PPC_750CXE31: |
|
| 2302 |
case CPU_PPC_750CXE31b: |
|
| 2303 |
case CPU_PPC_750CXR: |
|
| 2304 |
gen_spr_generic(env); |
|
| 2305 |
gen_spr_ne_601(env); |
|
| 2306 |
/* Memory management */ |
|
| 2307 |
gen_low_BATs(env); |
|
| 2308 |
/* Time base */ |
|
| 2309 |
gen_tbl(env); |
|
| 2310 |
gen_spr_7xx(env); |
|
| 2311 |
/* Hardware implementation registers */ |
|
| 2312 |
/* XXX : not implemented */ |
|
| 2313 |
spr_register(env, SPR_HID0, "HID0", |
|
| 2314 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2315 |
&spr_read_generic, &spr_write_generic, |
|
| 2316 |
0x00000000); |
|
| 2317 |
/* XXX : not implemented */ |
|
| 2318 |
spr_register(env, SPR_HID1, "HID1", |
|
| 2319 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2320 |
&spr_read_generic, &spr_write_generic, |
|
| 2321 |
0x00000000); |
|
| 2322 |
/* Allocate hardware IRQ controller */ |
|
| 2323 |
ppc6xx_irq_init(env); |
|
| 2324 |
break; |
|
| 2325 |
|
|
| 2326 |
case CPU_PPC_750FX10: /* IBM PowerPC 750 FX */ |
|
| 2327 |
case CPU_PPC_750FX20: |
|
| 2328 |
case CPU_PPC_750FX21: |
|
| 2329 |
case CPU_PPC_750FX22: |
|
| 2330 |
case CPU_PPC_750FX23: |
|
| 2331 |
case CPU_PPC_750GX10: /* IBM PowerPC 750 GX */ |
|
| 2332 |
case CPU_PPC_750GX11: |
|
| 2333 |
case CPU_PPC_750GX12: |
|
| 2334 |
gen_spr_generic(env); |
|
| 2335 |
gen_spr_ne_601(env); |
|
| 2336 |
/* Memory management */ |
|
| 2337 |
gen_low_BATs(env); |
|
| 2338 |
/* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ |
|
| 2339 |
gen_high_BATs(env); |
|
| 2340 |
/* Time base */ |
|
| 2341 |
gen_tbl(env); |
|
| 2342 |
gen_spr_7xx(env); |
|
| 2343 |
/* Hardware implementation registers */ |
|
| 2344 |
/* XXX : not implemented */ |
|
| 2345 |
spr_register(env, SPR_HID0, "HID0", |
|
| 2346 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2347 |
&spr_read_generic, &spr_write_generic, |
|
| 2348 |
0x00000000); |
|
| 2349 |
/* XXX : not implemented */ |
|
| 2350 |
spr_register(env, SPR_HID1, "HID1", |
|
| 2351 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2352 |
&spr_read_generic, &spr_write_generic, |
|
| 2353 |
0x00000000); |
|
| 2354 |
/* XXX : not implemented */ |
|
| 2355 |
spr_register(env, SPR_750_HID2, "HID2", |
|
| 2356 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2357 |
&spr_read_generic, &spr_write_generic, |
|
| 2358 |
0x00000000); |
|
| 2359 |
/* Allocate hardware IRQ controller */ |
|
| 2360 |
ppc6xx_irq_init(env); |
|
| 2361 |
break; |
|
| 2362 |
|
|
| 2363 |
case CPU_PPC_755_10: /* PowerPC 755 */ |
|
| 2364 |
case CPU_PPC_755_11: |
|
| 2365 |
case CPU_PPC_755_20: |
|
| 2366 |
case CPU_PPC_755D: |
|
| 2367 |
case CPU_PPC_755E: |
|
| 2368 |
gen_spr_generic(env); |
|
| 2369 |
gen_spr_ne_601(env); |
|
| 2370 |
/* Memory management */ |
|
| 2371 |
gen_low_BATs(env); |
|
| 2372 |
/* Time base */ |
|
| 2373 |
gen_tbl(env); |
|
| 2374 |
/* Memory management */ |
|
| 2375 |
gen_high_BATs(env); |
|
| 2376 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
|
| 2377 |
gen_spr_G2_755(env); |
|
| 2378 |
/* L2 cache control */ |
|
| 2379 |
/* XXX : not implemented */ |
|
| 2380 |
spr_register(env, SPR_ICTC, "ICTC", |
|
| 2381 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2382 |
&spr_read_generic, &spr_write_generic, |
|
| 2383 |
0x00000000); |
|
| 2384 |
/* XXX : not implemented */ |
|
| 2385 |
spr_register(env, SPR_L2PM, "L2PM", |
|
| 2386 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2387 |
&spr_read_generic, &spr_write_generic, |
|
| 2388 |
0x00000000); |
|
| 2389 |
/* Hardware implementation registers */ |
|
| 2390 |
/* XXX : not implemented */ |
|
| 2391 |
spr_register(env, SPR_HID0, "HID0", |
|
| 2392 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2393 |
&spr_read_generic, &spr_write_generic, |
|
| 2394 |
0x00000000); |
|
| 2395 |
/* XXX : not implemented */ |
|
| 2396 |
spr_register(env, SPR_HID1, "HID1", |
|
| 2397 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2398 |
&spr_read_generic, &spr_write_generic, |
|
| 2399 |
0x00000000); |
|
| 2400 |
/* XXX : not implemented */ |
|
| 2401 |
spr_register(env, SPR_HID2, "HID2", |
|
| 2402 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2403 |
&spr_read_generic, &spr_write_generic, |
|
| 2404 |
0x00000000); |
|
| 2405 |
/* Allocate hardware IRQ controller */ |
|
| 2406 |
ppc6xx_irq_init(env); |
|
| 2407 |
break; |
|
| 2408 |
|
|
| 2409 |
#if defined (TODO) |
|
| 2410 |
/* G4 family */ |
|
| 2411 |
case CPU_PPC_7400: /* PowerPC 7400 */ |
|
| 2412 |
case CPU_PPC_7410C: /* PowerPC 7410 */ |
|
| 2413 |
case CPU_PPC_7410D: |
|
| 2414 |
case CPU_PPC_7410E: |
|
| 2415 |
case CPU_PPC_7441: /* PowerPC 7441 */ |
|
| 2416 |
case CPU_PPC_7445: /* PowerPC 7445 */ |
|
| 2417 |
case CPU_PPC_7447: /* PowerPC 7447 */ |
|
| 2418 |
case CPU_PPC_7447A: /* PowerPC 7447A */ |
|
| 2419 |
case CPU_PPC_7448: /* PowerPC 7448 */ |
|
| 2420 |
case CPU_PPC_7450: /* PowerPC 7450 */ |
|
| 2421 |
case CPU_PPC_7450b: |
|
| 2422 |
case CPU_PPC_7451: /* PowerPC 7451 */ |
|
| 2423 |
case CPU_PPC_7451G: |
|
| 2424 |
case CPU_PPC_7455: /* PowerPC 7455 */ |
|
| 2425 |
case CPU_PPC_7455F: |
|
| 2426 |
case CPU_PPC_7455G: |
|
| 2427 |
case CPU_PPC_7457: /* PowerPC 7457 */ |
|
| 2428 |
case CPU_PPC_7457C: |
|
| 2429 |
case CPU_PPC_7457A: /* PowerPC 7457A */ |
|
| 2430 |
break; |
|
| 2431 |
#endif |
|
| 2432 |
|
|
| 2433 |
/* 64 bits PowerPC */ |
|
| 2434 |
#if defined (TARGET_PPC64) |
|
| 2435 |
#if defined (TODO) |
|
| 2436 |
case CPU_PPC_620: /* PowerPC 620 */ |
|
| 2437 |
case CPU_PPC_630: /* PowerPC 630 (Power 3) */ |
|
| 2438 |
case CPU_PPC_631: /* PowerPC 631 (Power 3+) */ |
|
| 2439 |
case CPU_PPC_POWER4: /* Power 4 */ |
|
| 2440 |
case CPU_PPC_POWER4P: /* Power 4+ */ |
|
| 2441 |
case CPU_PPC_POWER5: /* Power 5 */ |
|
| 2442 |
case CPU_PPC_POWER5P: /* Power 5+ */ |
|
| 2443 |
#endif |
|
| 2444 |
break; |
|
| 2445 |
|
|
| 2446 |
case CPU_PPC_970: /* PowerPC 970 */ |
|
| 2447 |
case CPU_PPC_970FX10: /* PowerPC 970 FX */ |
|
| 2448 |
case CPU_PPC_970FX20: |
|
| 2449 |
case CPU_PPC_970FX21: |
|
| 2450 |
case CPU_PPC_970FX30: |
|
| 2451 |
case CPU_PPC_970FX31: |
|
| 2452 |
case CPU_PPC_970MP10: /* PowerPC 970 MP */ |
|
| 2453 |
case CPU_PPC_970MP11: |
|
| 2454 |
gen_spr_generic(env); |
|
| 2455 |
gen_spr_ne_601(env); |
|
| 2456 |
/* XXX: not correct */ |
|
| 2457 |
gen_low_BATs(env); |
|
| 2458 |
/* Time base */ |
|
| 2459 |
gen_tbl(env); |
|
| 2460 |
gen_spr_7xx(env); |
|
| 2461 |
/* Hardware implementation registers */ |
|
| 2462 |
/* XXX : not implemented */ |
|
| 2463 |
spr_register(env, SPR_HID0, "HID0", |
|
| 2464 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2465 |
&spr_read_generic, &spr_write_generic, |
|
| 2466 |
0x00000000); |
|
| 2467 |
/* XXX : not implemented */ |
|
| 2468 |
spr_register(env, SPR_HID1, "HID1", |
|
| 2469 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2470 |
&spr_read_generic, &spr_write_generic, |
|
| 2471 |
0x00000000); |
|
| 2472 |
/* XXX : not implemented */ |
|
| 2473 |
spr_register(env, SPR_750_HID2, "HID2", |
|
| 2474 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2475 |
&spr_read_generic, &spr_write_generic, |
|
| 2476 |
0x00000000); |
|
| 2477 |
/* Allocate hardware IRQ controller */ |
|
| 2478 |
ppc970_irq_init(env); |
|
| 2479 |
break; |
|
| 2480 |
|
|
| 2481 |
#if defined (TODO) |
|
| 2482 |
case CPU_PPC_CELL10: /* Cell family */ |
|
| 2483 |
case CPU_PPC_CELL20: |
|
| 2484 |
case CPU_PPC_CELL30: |
|
| 2485 |
case CPU_PPC_CELL31: |
|
| 2486 |
#endif |
|
| 2487 |
break; |
|
| 2488 |
|
|
| 2489 |
#if defined (TODO) |
|
| 2490 |
case CPU_PPC_RS64: /* Apache (RS64/A35) */ |
|
| 2491 |
case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */ |
|
| 2492 |
case CPU_PPC_RS64III: /* Pulsar (RS64-III) */ |
|
| 2493 |
case CPU_PPC_RS64IV: /* IceStar/IStar/SStar (RS64-IV) */ |
|
| 2494 |
#endif |
|
| 2495 |
break; |
|
| 2496 |
#endif /* defined (TARGET_PPC64) */ |
|
| 2497 |
|
|
| 2498 |
#if defined (TODO) |
|
| 2499 |
/* POWER */ |
|
| 2500 |
case CPU_POWER: /* POWER */ |
|
| 2501 |
case CPU_POWER2: /* POWER2 */ |
|
| 2502 |
break; |
|
| 2503 |
#endif |
|
| 2504 |
|
|
| 2505 |
default: |
|
| 2506 |
gen_spr_generic(env); |
|
| 2507 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 2508 |
break; |
|
| 2509 |
} |
|
| 2510 |
if (env->nb_BATs == -1) |
|
| 2511 |
env->nb_BATs = 4; |
|
| 2512 |
/* Allocate TLBs buffer when needed */ |
|
| 2513 |
if (env->nb_tlb != 0) {
|
|
| 2514 |
int nb_tlb = env->nb_tlb; |
|
| 2515 |
if (env->id_tlbs != 0) |
|
| 2516 |
nb_tlb *= 2; |
|
| 2517 |
env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t)); |
|
| 2518 |
/* Pre-compute some useful values */ |
|
| 2519 |
env->tlb_per_way = env->nb_tlb / env->nb_ways; |
|
| 2520 |
} |
|
| 2185 |
/* PowerPC 401x2 */ |
|
| 2186 |
#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \ |
|
| 2187 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 2188 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
|
| 2189 |
PPC_CACHE_DCBA | PPC_MFTB | \ |
|
| 2190 |
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) |
|
| 2191 |
#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL) |
|
| 2192 |
#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z) |
|
| 2193 |
#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x) |
|
| 2194 |
#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401) |
|
| 2195 |
|
|
| 2196 |
static void init_proc_401x2 (CPUPPCState *env) |
|
| 2197 |
{
|
|
| 2198 |
gen_spr_40x(env); |
|
| 2199 |
gen_spr_401_403(env); |
|
| 2200 |
gen_spr_401x2(env); |
|
| 2201 |
gen_spr_compress(env); |
|
| 2202 |
/* Bus access control */ |
|
| 2203 |
spr_register(env, SPR_40x_SGR, "SGR", |
|
| 2204 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2205 |
&spr_read_generic, &spr_write_generic, |
|
| 2206 |
0xFFFFFFFF); |
|
| 2207 |
/* XXX : not implemented */ |
|
| 2208 |
spr_register(env, SPR_40x_DCWR, "DCWR", |
|
| 2209 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2210 |
&spr_read_generic, &spr_write_generic, |
|
| 2211 |
0x00000000); |
|
| 2212 |
/* Memory management */ |
|
| 2213 |
env->nb_tlb = 64; |
|
| 2214 |
env->nb_ways = 1; |
|
| 2215 |
env->id_tlbs = 0; |
|
| 2216 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 2521 | 2217 |
} |
| 2522 | 2218 |
|
| 2523 |
#if defined(PPC_DUMP_CPU) |
|
| 2524 |
static void dump_sprs (CPUPPCState *env) |
|
| 2219 |
/* PowerPC 401x3 */ |
|
| 2220 |
#if defined(TODO) |
|
| 2221 |
#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \ |
|
| 2222 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 2223 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
|
| 2224 |
PPC_CACHE_DCBA | PPC_MFTB | \ |
|
| 2225 |
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) |
|
| 2226 |
#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL) |
|
| 2227 |
#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z) |
|
| 2228 |
#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x) |
|
| 2229 |
#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401) |
|
| 2230 |
|
|
| 2231 |
static void init_proc_401x2 (CPUPPCState *env) |
|
| 2525 | 2232 |
{
|
| 2526 |
ppc_spr_t *spr; |
|
| 2527 |
uint32_t pvr = env->spr[SPR_PVR]; |
|
| 2528 |
uint32_t sr, sw, ur, uw; |
|
| 2529 |
int i, j, n; |
|
| 2530 |
|
|
| 2531 |
printf("* SPRs for PVR=%08x\n", pvr);
|
|
| 2532 |
for (i = 0; i < 32; i++) {
|
|
| 2533 |
for (j = 0; j < 32; j++) {
|
|
| 2534 |
n = (i << 5) | j; |
|
| 2535 |
spr = &env->spr_cb[n]; |
|
| 2536 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2537 |
sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS; |
|
| 2538 |
sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS; |
|
| 2539 |
#else |
|
| 2540 |
sw = 0; |
|
| 2541 |
sr = 0; |
|
| 2542 |
#endif |
|
| 2543 |
uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; |
|
| 2544 |
ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; |
|
| 2545 |
if (sw || sr || uw || ur) {
|
|
| 2546 |
printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
|
|
| 2547 |
(i << 5) | j, (i << 5) | j, spr->name, |
|
| 2548 |
sw ? 'w' : '-', sr ? 'r' : '-', |
|
| 2549 |
uw ? 'w' : '-', ur ? 'r' : '-'); |
|
| 2550 |
} |
|
| 2551 |
} |
|
| 2552 |
} |
|
| 2553 |
fflush(stdout); |
|
| 2554 |
fflush(stderr); |
|
| 2555 | 2233 |
} |
| 2556 |
#endif |
|
| 2557 |
|
|
| 2558 |
/*****************************************************************************/ |
|
| 2559 |
#include <stdlib.h> |
|
| 2560 |
#include <string.h> |
|
| 2561 |
|
|
| 2562 |
int fflush (FILE *stream); |
|
| 2563 |
|
|
| 2564 |
/* Opcode types */ |
|
| 2565 |
enum {
|
|
| 2566 |
PPC_DIRECT = 0, /* Opcode routine */ |
|
| 2567 |
PPC_INDIRECT = 1, /* Indirect opcode table */ |
|
| 2568 |
}; |
|
| 2569 |
|
|
| 2570 |
static inline int is_indirect_opcode (void *handler) |
|
| 2234 |
#endif /* TODO */ |
|
| 2235 |
|
|
| 2236 |
/* IOP480 */ |
|
| 2237 |
#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \ |
|
| 2238 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 2239 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
|
| 2240 |
PPC_CACHE_DCBA | \ |
|
| 2241 |
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) |
|
| 2242 |
#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL) |
|
| 2243 |
#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z) |
|
| 2244 |
#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x) |
|
| 2245 |
#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401) |
|
| 2246 |
|
|
| 2247 |
static void init_proc_IOP480 (CPUPPCState *env) |
|
| 2571 | 2248 |
{
|
| 2572 |
return ((unsigned long)handler & 0x03) == PPC_INDIRECT; |
|
| 2249 |
gen_spr_40x(env); |
|
| 2250 |
gen_spr_401_403(env); |
|
| 2251 |
gen_spr_401x2(env); |
|
| 2252 |
gen_spr_compress(env); |
|
| 2253 |
/* Bus access control */ |
|
| 2254 |
spr_register(env, SPR_40x_SGR, "SGR", |
|
| 2255 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2256 |
&spr_read_generic, &spr_write_generic, |
|
| 2257 |
0xFFFFFFFF); |
|
| 2258 |
/* XXX : not implemented */ |
|
| 2259 |
spr_register(env, SPR_40x_DCWR, "DCWR", |
|
| 2260 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2261 |
&spr_read_generic, &spr_write_generic, |
|
| 2262 |
0x00000000); |
|
| 2263 |
/* Memory management */ |
|
| 2264 |
env->nb_tlb = 64; |
|
| 2265 |
env->nb_ways = 1; |
|
| 2266 |
env->id_tlbs = 0; |
|
| 2267 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 2573 | 2268 |
} |
| 2574 | 2269 |
|
| 2575 |
static inline opc_handler_t **ind_table(void *handler) |
|
| 2270 |
/* PowerPC 403 */ |
|
| 2271 |
#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \ |
|
| 2272 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 2273 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
|
| 2274 |
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) |
|
| 2275 |
#define POWERPC_MSRM_403 (0x000000000007D00DULL) |
|
| 2276 |
#define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx) |
|
| 2277 |
#define POWERPC_EXCP_403 (POWERPC_EXCP_40x) |
|
| 2278 |
#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401) |
|
| 2279 |
|
|
| 2280 |
static void init_proc_403 (CPUPPCState *env) |
|
| 2576 | 2281 |
{
|
| 2577 |
return (opc_handler_t **)((unsigned long)handler & ~3); |
|
| 2282 |
gen_spr_40x(env); |
|
| 2283 |
gen_spr_401_403(env); |
|
| 2284 |
gen_spr_403(env); |
|
| 2285 |
gen_spr_403_real(env); |
|
| 2286 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 2578 | 2287 |
} |
| 2579 | 2288 |
|
| 2580 |
/* Instruction table creation */ |
|
| 2581 |
/* Opcodes tables creation */ |
|
| 2582 |
static void fill_new_table (opc_handler_t **table, int len) |
|
| 2289 |
/* PowerPC 403 GCX */ |
|
| 2290 |
#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \ |
|
| 2291 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
|
| 2292 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
|
| 2293 |
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) |
|
| 2294 |
#define POWERPC_MSRM_403GCX (0x000000000007D00DULL) |
|
| 2295 |
#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z) |
|
| 2296 |
#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x) |
|
| 2297 |
#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401) |
|
| 2298 |
|
|
| 2299 |
static void init_proc_403GCX (CPUPPCState *env) |
|
| 2583 | 2300 |
{
|
| 2584 |
int i; |
|
| 2585 |
|
|
| 2586 |
for (i = 0; i < len; i++) |
|
| 2587 |
table[i] = &invalid_handler; |
|
| 2301 |
gen_spr_40x(env); |
|
| 2302 |
gen_spr_401_403(env); |
|
| 2303 |
gen_spr_403(env); |
|
| 2304 |
gen_spr_403_real(env); |
|
| 2305 |
gen_spr_403_mmu(env); |
|
| 2306 |
/* Bus access control */ |
|
| 2307 |
spr_register(env, SPR_40x_SGR, "SGR", |
|
| 2308 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2309 |
&spr_read_generic, &spr_write_generic, |
|
| 2310 |
0xFFFFFFFF); |
|
| 2311 |
/* XXX : not implemented */ |
|
| 2312 |
spr_register(env, SPR_40x_DCWR, "DCWR", |
|
| 2313 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2314 |
&spr_read_generic, &spr_write_generic, |
|
| 2315 |
0x00000000); |
|
| 2316 |
/* Memory management */ |
|
| 2317 |
env->nb_tlb = 64; |
|
| 2318 |
env->nb_ways = 1; |
|
| 2319 |
env->id_tlbs = 0; |
|
| 2320 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 2588 | 2321 |
} |
| 2589 | 2322 |
|
| 2590 |
static int create_new_table (opc_handler_t **table, unsigned char idx) |
|
| 2323 |
/* PowerPC 405 */ |
|
| 2324 |
#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \ |
|
| 2325 |
PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \ |
|
| 2326 |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
|
| 2327 |
PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \ |
|
| 2328 |
PPC_405_MAC) |
|
| 2329 |
#define POWERPC_MSRM_405 (0x000000000006E630ULL) |
|
| 2330 |
#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx) |
|
| 2331 |
#define POWERPC_EXCP_405 (POWERPC_EXCP_40x) |
|
| 2332 |
#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405) |
|
| 2333 |
|
|
| 2334 |
static void init_proc_405 (CPUPPCState *env) |
|
| 2591 | 2335 |
{
|
| 2592 |
opc_handler_t **tmp; |
|
| 2593 |
|
|
| 2594 |
tmp = malloc(0x20 * sizeof(opc_handler_t)); |
|
| 2595 |
if (tmp == NULL) |
|
| 2596 |
return -1; |
|
| 2597 |
fill_new_table(tmp, 0x20); |
|
| 2598 |
table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT); |
|
| 2599 |
|
|
| 2600 |
return 0; |
|
| 2336 |
/* Time base */ |
|
| 2337 |
gen_tbl(env); |
|
| 2338 |
gen_spr_40x(env); |
|
| 2339 |
gen_spr_405(env); |
|
| 2340 |
/* Bus access control */ |
|
| 2341 |
spr_register(env, SPR_40x_SGR, "SGR", |
|
| 2342 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2343 |
&spr_read_generic, &spr_write_generic, |
|
| 2344 |
0xFFFFFFFF); |
|
| 2345 |
/* XXX : not implemented */ |
|
| 2346 |
spr_register(env, SPR_40x_DCWR, "DCWR", |
|
| 2347 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2348 |
&spr_read_generic, &spr_write_generic, |
|
| 2349 |
0x00000000); |
|
| 2350 |
/* Memory management */ |
|
| 2351 |
env->nb_tlb = 64; |
|
| 2352 |
env->nb_ways = 1; |
|
| 2353 |
env->id_tlbs = 0; |
|
| 2354 |
/* Allocate hardware IRQ controller */ |
|
| 2355 |
ppc405_irq_init(env); |
|
| 2601 | 2356 |
} |
| 2602 | 2357 |
|
| 2603 |
static int insert_in_table (opc_handler_t **table, unsigned char idx, |
|
| 2604 |
opc_handler_t *handler) |
|
| 2358 |
/* PowerPC 440 EP */ |
|
| 2359 |
#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \ |
|
| 2360 |
PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \ |
|
| 2361 |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ |
|
| 2362 |
PPC_440_SPEC | PPC_RFMCI) |
|
| 2363 |
#define POWERPC_MSRM_440EP (0x000000000006D630ULL) |
|
| 2364 |
#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE) |
|
| 2365 |
#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE) |
|
| 2366 |
#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE) |
|
| 2367 |
|
|
| 2368 |
static void init_proc_440EP (CPUPPCState *env) |
|
| 2605 | 2369 |
{
|
| 2606 |
if (table[idx] != &invalid_handler) |
|
| 2607 |
return -1; |
|
| 2608 |
table[idx] = handler; |
|
| 2609 |
|
|
| 2610 |
return 0; |
|
| 2370 |
/* Time base */ |
|
| 2371 |
gen_tbl(env); |
|
| 2372 |
gen_spr_BookE(env); |
|
| 2373 |
gen_spr_440(env); |
|
| 2374 |
spr_register(env, SPR_BOOKE_MCSR, "MCSR", |
|
| 2375 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2376 |
&spr_read_generic, &spr_write_generic, |
|
| 2377 |
0x00000000); |
|
| 2378 |
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", |
|
| 2379 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2380 |
&spr_read_generic, &spr_write_generic, |
|
| 2381 |
0x00000000); |
|
| 2382 |
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", |
|
| 2383 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2384 |
&spr_read_generic, &spr_write_generic, |
|
| 2385 |
0x00000000); |
|
| 2386 |
spr_register(env, SPR_440_CCR1, "CCR1", |
|
| 2387 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2388 |
&spr_read_generic, &spr_write_generic, |
|
| 2389 |
0x00000000); |
|
| 2390 |
/* Memory management */ |
|
| 2391 |
env->nb_tlb = 64; |
|
| 2392 |
env->nb_ways = 1; |
|
| 2393 |
env->id_tlbs = 0; |
|
| 2394 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 2611 | 2395 |
} |
| 2612 | 2396 |
|
| 2613 |
static int register_direct_insn (opc_handler_t **ppc_opcodes, |
|
| 2614 |
unsigned char idx, opc_handler_t *handler) |
|
| 2397 |
/* PowerPC 440 GP */ |
|
| 2398 |
#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \ |
|
| 2399 |
PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \ |
|
| 2400 |
PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \ |
|
| 2401 |
PPC_405_MAC | PPC_440_SPEC) |
|
| 2402 |
#define POWERPC_MSRM_440GP (0x000000000006FF30ULL) |
|
| 2403 |
#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE) |
|
| 2404 |
#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE) |
|
| 2405 |
#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE) |
|
| 2406 |
|
|
| 2407 |
static void init_proc_440GP (CPUPPCState *env) |
|
| 2615 | 2408 |
{
|
| 2616 |
if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
|
|
| 2617 |
printf("*** ERROR: opcode %02x already assigned in main "
|
|
| 2618 |
"opcode table\n", idx); |
|
| 2619 |
return -1; |
|
| 2620 |
} |
|
| 2621 |
|
|
| 2622 |
return 0; |
|
| 2409 |
/* Time base */ |
|
| 2410 |
gen_tbl(env); |
|
| 2411 |
gen_spr_BookE(env); |
|
| 2412 |
gen_spr_440(env); |
|
| 2413 |
/* Memory management */ |
|
| 2414 |
env->nb_tlb = 64; |
|
| 2415 |
env->nb_ways = 1; |
|
| 2416 |
env->id_tlbs = 0; |
|
| 2417 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 2623 | 2418 |
} |
| 2624 | 2419 |
|
| 2625 |
static int register_ind_in_table (opc_handler_t **table, |
|
| 2626 |
unsigned char idx1, unsigned char idx2, |
|
| 2627 |
opc_handler_t *handler) |
|
| 2420 |
/* PowerPC 440x4 */ |
|
| 2421 |
#if defined(TODO) |
|
| 2422 |
#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \ |
|
| 2423 |
PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \ |
|
| 2424 |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ |
|
| 2425 |
PPC_440_SPEC) |
|
| 2426 |
#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL) |
|
| 2427 |
#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE) |
|
| 2428 |
#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE) |
|
| 2429 |
#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE) |
|
| 2430 |
|
|
| 2431 |
static void init_proc_440x4 (CPUPPCState *env) |
|
| 2628 | 2432 |
{
|
| 2629 |
if (table[idx1] == &invalid_handler) {
|
|
| 2630 |
if (create_new_table(table, idx1) < 0) {
|
|
| 2631 |
printf("*** ERROR: unable to create indirect table "
|
|
| 2632 |
"idx=%02x\n", idx1); |
|
| 2633 |
return -1; |
|
| 2634 |
} |
|
| 2635 |
} else {
|
|
| 2636 |
if (!is_indirect_opcode(table[idx1])) {
|
|
| 2637 |
printf("*** ERROR: idx %02x already assigned to a direct "
|
|
| 2638 |
"opcode\n", idx1); |
|
| 2639 |
return -1; |
|
| 2640 |
} |
|
| 2641 |
} |
|
| 2642 |
if (handler != NULL && |
|
| 2643 |
insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
|
|
| 2644 |
printf("*** ERROR: opcode %02x already assigned in "
|
|
| 2645 |
"opcode table %02x\n", idx2, idx1); |
|
| 2646 |
return -1; |
|
| 2647 |
} |
|
| 2648 |
|
|
| 2649 |
return 0; |
|
| 2433 |
/* Time base */ |
|
| 2434 |
gen_tbl(env); |
|
| 2435 |
gen_spr_BookE(env); |
|
| 2436 |
gen_spr_440(env); |
|
| 2437 |
/* Memory management */ |
|
| 2438 |
env->nb_tlb = 64; |
|
| 2439 |
env->nb_ways = 1; |
|
| 2440 |
env->id_tlbs = 0; |
|
| 2441 |
/* XXX: TODO: allocate internal IRQ controller */ |
|
| 2650 | 2442 |
} |
| 2651 |
|
|
| 2652 |
static int register_ind_insn (opc_handler_t **ppc_opcodes, |
|
| 2653 |
unsigned char idx1, unsigned char idx2, |
|
| 2654 |
opc_handler_t *handler) |
|
| 2443 |
#endif /* TODO */ |
|
| 2444 |
|
|
| 2445 |
/* PowerPC 440x5 */ |
|
| 2446 |
#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \ |
|
| 2447 |
PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \ |
|
| 2448 |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ |
|
| 2449 |
PPC_440_SPEC | PPC_RFMCI) |
|
| 2450 |
#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL) |
|
| 2451 |
#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE) |
|
| 2452 |
#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE) |
|
| 2453 |
#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE) |
|
| 2454 |
|
|
| 2455 |
static void init_proc_440x5 (CPUPPCState *env) |
|
| 2655 | 2456 |
{
|
| 2656 |
int ret; |
|
| 2657 |
|
|
| 2658 |
ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler); |
|
| 2659 |
|
|
| 2660 |
return ret; |
|
| 2457 |
/* Time base */ |
|
| 2458 |
gen_tbl(env); |
|
| 2459 |
gen_spr_BookE(env); |
|
| 2460 |
gen_spr_440(env); |
|
| 2461 |
spr_register(env, SPR_BOOKE_MCSR, "MCSR", |
|
| 2462 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2463 |
&spr_read_generic, &spr_write_generic, |
|
| 2464 |
0x00000000); |
|
| 2465 |
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", |
|
| 2466 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2467 |
&spr_read_generic, &spr_write_generic, |
|
| 2468 |
0x00000000); |
|
| 2469 |
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", |
|
| 2470 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 2471 |
&spr_read_generic, &spr_write_generic, |
|
Also available in: Unified diff