Revision a7812ae4 target-alpha/translate.c
| b/target-alpha/translate.c | ||
|---|---|---|
| 26 | 26 |
#include "exec-all.h" |
| 27 | 27 |
#include "disas.h" |
| 28 | 28 |
#include "host-utils.h" |
| 29 |
#include "helper.h" |
|
| 30 | 29 |
#include "tcg-op.h" |
| 31 | 30 |
#include "qemu-common.h" |
| 32 | 31 |
|
| 32 |
#include "helper.h" |
|
| 33 |
#define GEN_HELPER 1 |
|
| 34 |
#include "helper.h" |
|
| 35 |
|
|
| 33 | 36 |
/* #define DO_SINGLE_STEP */ |
| 34 | 37 |
#define ALPHA_DEBUG_DISAS |
| 35 | 38 |
/* #define DO_TB_FLUSH */ |
| ... | ... | |
| 45 | 48 |
}; |
| 46 | 49 |
|
| 47 | 50 |
/* global register indexes */ |
| 48 |
static TCGv cpu_env; |
|
| 51 |
static TCGv_ptr cpu_env;
|
|
| 49 | 52 |
static TCGv cpu_ir[31]; |
| 50 | 53 |
static TCGv cpu_fir[31]; |
| 51 | 54 |
static TCGv cpu_pc; |
| ... | ... | |
| 65 | 68 |
if (done_init) |
| 66 | 69 |
return; |
| 67 | 70 |
|
| 68 |
cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
|
|
| 71 |
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
|
| 69 | 72 |
|
| 70 | 73 |
p = cpu_reg_names; |
| 71 | 74 |
for (i = 0; i < 31; i++) {
|
| 72 | 75 |
sprintf(p, "ir%d", i); |
| 73 |
cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
|
| 74 |
offsetof(CPUState, ir[i]), p); |
|
| 76 |
cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0,
|
|
| 77 |
offsetof(CPUState, ir[i]), p);
|
|
| 75 | 78 |
p += (i < 10) ? 4 : 5; |
| 76 | 79 |
|
| 77 | 80 |
sprintf(p, "fir%d", i); |
| 78 |
cpu_fir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
|
| 79 |
offsetof(CPUState, fir[i]), p); |
|
| 81 |
cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0,
|
|
| 82 |
offsetof(CPUState, fir[i]), p);
|
|
| 80 | 83 |
p += (i < 10) ? 5 : 6; |
| 81 | 84 |
} |
| 82 | 85 |
|
| 83 |
cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
|
| 84 |
offsetof(CPUState, pc), "pc"); |
|
| 86 |
cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
|
|
| 87 |
offsetof(CPUState, pc), "pc");
|
|
| 85 | 88 |
|
| 86 |
cpu_lock = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
|
| 87 |
offsetof(CPUState, lock), "lock"); |
|
| 89 |
cpu_lock = tcg_global_mem_new_i64(TCG_AREG0,
|
|
| 90 |
offsetof(CPUState, lock), "lock");
|
|
| 88 | 91 |
|
| 89 | 92 |
/* register helpers */ |
| 90 |
#undef DEF_HELPER |
|
| 91 |
#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); |
|
| 93 |
#define GEN_HELPER 2 |
|
| 92 | 94 |
#include "helper.h" |
| 93 | 95 |
|
| 94 | 96 |
done_init = 1; |
| ... | ... | |
| 97 | 99 |
static always_inline void gen_excp (DisasContext *ctx, |
| 98 | 100 |
int exception, int error_code) |
| 99 | 101 |
{
|
| 100 |
TCGv tmp1, tmp2; |
|
| 102 |
TCGv_i32 tmp1, tmp2;
|
|
| 101 | 103 |
|
| 102 | 104 |
tcg_gen_movi_i64(cpu_pc, ctx->pc); |
| 103 | 105 |
tmp1 = tcg_const_i32(exception); |
| 104 | 106 |
tmp2 = tcg_const_i32(error_code); |
| 105 |
tcg_gen_helper_0_2(helper_excp, tmp1, tmp2);
|
|
| 106 |
tcg_temp_free(tmp2); |
|
| 107 |
tcg_temp_free(tmp1); |
|
| 107 |
gen_helper_excp(tmp1, tmp2);
|
|
| 108 |
tcg_temp_free_i32(tmp2);
|
|
| 109 |
tcg_temp_free_i32(tmp1);
|
|
| 108 | 110 |
} |
| 109 | 111 |
|
| 110 | 112 |
static always_inline void gen_invalid (DisasContext *ctx) |
| ... | ... | |
| 114 | 116 |
|
| 115 | 117 |
static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags) |
| 116 | 118 |
{
|
| 117 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I32); |
|
| 119 |
TCGv tmp = tcg_temp_new(); |
|
| 120 |
TCGv_i32 tmp32 = tcg_temp_new_i32(); |
|
| 118 | 121 |
tcg_gen_qemu_ld32u(tmp, t1, flags); |
| 119 |
tcg_gen_helper_1_1(helper_memory_to_f, t0, tmp); |
|
| 122 |
tcg_gen_trunc_i64_i32(tmp32, tmp); |
|
| 123 |
gen_helper_memory_to_f(t0, tmp32); |
|
| 124 |
tcg_temp_free_i32(tmp32); |
|
| 120 | 125 |
tcg_temp_free(tmp); |
| 121 | 126 |
} |
| 122 | 127 |
|
| 123 | 128 |
static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags) |
| 124 | 129 |
{
|
| 125 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 130 |
TCGv tmp = tcg_temp_new(); |
|
| 126 | 131 |
tcg_gen_qemu_ld64(tmp, t1, flags); |
| 127 |
tcg_gen_helper_1_1(helper_memory_to_g, t0, tmp);
|
|
| 132 |
gen_helper_memory_to_g(t0, tmp);
|
|
| 128 | 133 |
tcg_temp_free(tmp); |
| 129 | 134 |
} |
| 130 | 135 |
|
| 131 | 136 |
static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags) |
| 132 | 137 |
{
|
| 133 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I32); |
|
| 138 |
TCGv tmp = tcg_temp_new(); |
|
| 139 |
TCGv_i32 tmp32 = tcg_temp_new_i32(); |
|
| 134 | 140 |
tcg_gen_qemu_ld32u(tmp, t1, flags); |
| 135 |
tcg_gen_helper_1_1(helper_memory_to_s, t0, tmp); |
|
| 141 |
tcg_gen_trunc_i64_i32(tmp32, tmp); |
|
| 142 |
gen_helper_memory_to_s(t0, tmp32); |
|
| 143 |
tcg_temp_free_i32(tmp32); |
|
| 136 | 144 |
tcg_temp_free(tmp); |
| 137 | 145 |
} |
| 138 | 146 |
|
| ... | ... | |
| 158 | 166 |
if (unlikely(ra == 31)) |
| 159 | 167 |
return; |
| 160 | 168 |
|
| 161 |
addr = tcg_temp_new(TCG_TYPE_I64);
|
|
| 169 |
addr = tcg_temp_new(); |
|
| 162 | 170 |
if (rb != 31) {
|
| 163 | 171 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); |
| 164 | 172 |
if (clear) |
| ... | ... | |
| 177 | 185 |
|
| 178 | 186 |
static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags) |
| 179 | 187 |
{
|
| 180 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I32); |
|
| 181 |
tcg_gen_helper_1_1(helper_f_to_memory, tmp, t0); |
|
| 188 |
TCGv_i32 tmp32 = tcg_temp_new_i32(); |
|
| 189 |
TCGv tmp = tcg_temp_new(); |
|
| 190 |
gen_helper_f_to_memory(tmp32, t0); |
|
| 191 |
tcg_gen_extu_i32_i64(tmp, tmp32); |
|
| 182 | 192 |
tcg_gen_qemu_st32(tmp, t1, flags); |
| 183 | 193 |
tcg_temp_free(tmp); |
| 194 |
tcg_temp_free_i32(tmp32); |
|
| 184 | 195 |
} |
| 185 | 196 |
|
| 186 | 197 |
static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags) |
| 187 | 198 |
{
|
| 188 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 189 |
tcg_gen_helper_1_1(helper_g_to_memory, tmp, t0);
|
|
| 199 |
TCGv tmp = tcg_temp_new(); |
|
| 200 |
gen_helper_g_to_memory(tmp, t0);
|
|
| 190 | 201 |
tcg_gen_qemu_st64(tmp, t1, flags); |
| 191 | 202 |
tcg_temp_free(tmp); |
| 192 | 203 |
} |
| 193 | 204 |
|
| 194 | 205 |
static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags) |
| 195 | 206 |
{
|
| 196 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I32); |
|
| 197 |
tcg_gen_helper_1_1(helper_s_to_memory, tmp, t0); |
|
| 207 |
TCGv_i32 tmp32 = tcg_temp_new_i32(); |
|
| 208 |
TCGv tmp = tcg_temp_new(); |
|
| 209 |
gen_helper_s_to_memory(tmp32, t0); |
|
| 210 |
tcg_gen_extu_i32_i64(tmp, tmp32); |
|
| 198 | 211 |
tcg_gen_qemu_st32(tmp, t1, flags); |
| 199 | 212 |
tcg_temp_free(tmp); |
| 213 |
tcg_temp_free_i32(tmp32); |
|
| 200 | 214 |
} |
| 201 | 215 |
|
| 202 | 216 |
static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags) |
| ... | ... | |
| 238 | 252 |
{
|
| 239 | 253 |
TCGv addr; |
| 240 | 254 |
if (local) |
| 241 |
addr = tcg_temp_local_new(TCG_TYPE_I64);
|
|
| 255 |
addr = tcg_temp_local_new(); |
|
| 242 | 256 |
else |
| 243 |
addr = tcg_temp_new(TCG_TYPE_I64);
|
|
| 257 |
addr = tcg_temp_new(); |
|
| 244 | 258 |
if (rb != 31) {
|
| 245 | 259 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); |
| 246 | 260 |
if (clear) |
| ... | ... | |
| 277 | 291 |
l2 = gen_new_label(); |
| 278 | 292 |
if (likely(ra != 31)) {
|
| 279 | 293 |
if (mask) {
|
| 280 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 294 |
TCGv tmp = tcg_temp_new(); |
|
| 281 | 295 |
tcg_gen_andi_i64(tmp, cpu_ir[ra], 1); |
| 282 | 296 |
tcg_gen_brcondi_i64(cond, tmp, 0, l1); |
| 283 | 297 |
tcg_temp_free(tmp); |
| ... | ... | |
| 296 | 310 |
gen_set_label(l2); |
| 297 | 311 |
} |
| 298 | 312 |
|
| 299 |
static always_inline void gen_fbcond (DisasContext *ctx, |
|
| 300 |
void* func, |
|
| 313 |
static always_inline void gen_fbcond (DisasContext *ctx, int opc, |
|
| 301 | 314 |
int ra, int32_t disp16) |
| 302 | 315 |
{
|
| 303 | 316 |
int l1, l2; |
| 304 | 317 |
TCGv tmp; |
| 318 |
TCGv src; |
|
| 305 | 319 |
|
| 306 | 320 |
l1 = gen_new_label(); |
| 307 | 321 |
l2 = gen_new_label(); |
| 308 | 322 |
if (ra != 31) {
|
| 309 |
tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 310 |
tcg_gen_helper_1_1(func, tmp, cpu_fir[ra]);
|
|
| 323 |
tmp = tcg_temp_new(); |
|
| 324 |
src = cpu_fir[ra];
|
|
| 311 | 325 |
} else {
|
| 312 | 326 |
tmp = tcg_const_i64(0); |
| 313 |
tcg_gen_helper_1_1(func, tmp, tmp); |
|
| 327 |
src = tmp; |
|
| 328 |
} |
|
| 329 |
switch (opc) {
|
|
| 330 |
case 0x31: /* FBEQ */ |
|
| 331 |
gen_helper_cmpfeq(tmp, src); |
|
| 332 |
break; |
|
| 333 |
case 0x32: /* FBLT */ |
|
| 334 |
gen_helper_cmpflt(tmp, src); |
|
| 335 |
break; |
|
| 336 |
case 0x33: /* FBLE */ |
|
| 337 |
gen_helper_cmpfle(tmp, src); |
|
| 338 |
break; |
|
| 339 |
case 0x35: /* FBNE */ |
|
| 340 |
gen_helper_cmpfne(tmp, src); |
|
| 341 |
break; |
|
| 342 |
case 0x36: /* FBGE */ |
|
| 343 |
gen_helper_cmpfge(tmp, src); |
|
| 344 |
break; |
|
| 345 |
case 0x37: /* FBGT */ |
|
| 346 |
gen_helper_cmpfgt(tmp, src); |
|
| 347 |
break; |
|
| 348 |
default: |
|
| 349 |
abort(); |
|
| 314 | 350 |
} |
| 315 | 351 |
tcg_gen_brcondi_i64(TCG_COND_NE, tmp, 0, l1); |
| 316 | 352 |
tcg_gen_movi_i64(cpu_pc, ctx->pc); |
| ... | ... | |
| 333 | 369 |
|
| 334 | 370 |
if (ra != 31) {
|
| 335 | 371 |
if (mask) {
|
| 336 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 372 |
TCGv tmp = tcg_temp_new(); |
|
| 337 | 373 |
tcg_gen_andi_i64(tmp, cpu_ir[ra], 1); |
| 338 | 374 |
tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1); |
| 339 | 375 |
tcg_temp_free(tmp); |
| ... | ... | |
| 353 | 389 |
gen_set_label(l1); |
| 354 | 390 |
} |
| 355 | 391 |
|
| 356 |
static always_inline void gen_farith2 (void *helper,
|
|
| 357 |
int rb, int rc)
|
|
| 358 |
{
|
|
| 359 |
if (unlikely(rc == 31)) |
|
| 360 |
return; |
|
| 361 |
|
|
| 362 |
if (rb != 31) |
|
| 363 |
tcg_gen_helper_1_1(helper, cpu_fir[rc], cpu_fir[rb]);
|
|
| 364 |
else {
|
|
| 365 |
TCGv tmp = tcg_const_i64(0); |
|
| 366 |
tcg_gen_helper_1_1(helper, cpu_fir[rc], tmp);
|
|
| 367 |
tcg_temp_free(tmp); |
|
| 368 |
} |
|
| 392 |
#define FARITH2(name) \
|
|
| 393 |
static always_inline void glue(gen_f, name)(int rb, int rc) \
|
|
| 394 |
{ \
|
|
| 395 |
if (unlikely(rc == 31)) \
|
|
| 396 |
return; \
|
|
| 397 |
\ |
|
| 398 |
if (rb != 31) \
|
|
| 399 |
gen_helper_ ## name (cpu_fir[rc], cpu_fir[rb]); \
|
|
| 400 |
else { \
|
|
| 401 |
TCGv tmp = tcg_const_i64(0); \
|
|
| 402 |
gen_helper_ ## name (cpu_fir[rc], tmp); \
|
|
| 403 |
tcg_temp_free(tmp); \
|
|
| 404 |
} \
|
|
| 369 | 405 |
} |
| 370 |
|
|
| 371 |
static always_inline void gen_farith3 (void *helper, |
|
| 372 |
int ra, int rb, int rc) |
|
| 373 |
{
|
|
| 374 |
if (unlikely(rc == 31)) |
|
| 375 |
return; |
|
| 376 |
|
|
| 377 |
if (ra != 31) {
|
|
| 378 |
if (rb != 31) |
|
| 379 |
tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]); |
|
| 380 |
else {
|
|
| 381 |
TCGv tmp = tcg_const_i64(0); |
|
| 382 |
tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], tmp); |
|
| 383 |
tcg_temp_free(tmp); |
|
| 384 |
} |
|
| 385 |
} else {
|
|
| 386 |
TCGv tmp = tcg_const_i64(0); |
|
| 387 |
if (rb != 31) |
|
| 388 |
tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, cpu_fir[rb]); |
|
| 389 |
else |
|
| 390 |
tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, tmp); |
|
| 391 |
tcg_temp_free(tmp); |
|
| 392 |
} |
|
| 406 |
FARITH2(sqrts) |
|
| 407 |
FARITH2(sqrtf) |
|
| 408 |
FARITH2(sqrtg) |
|
| 409 |
FARITH2(sqrtt) |
|
| 410 |
FARITH2(cvtgf) |
|
| 411 |
FARITH2(cvtgq) |
|
| 412 |
FARITH2(cvtqf) |
|
| 413 |
FARITH2(cvtqg) |
|
| 414 |
FARITH2(cvtst) |
|
| 415 |
FARITH2(cvtts) |
|
| 416 |
FARITH2(cvttq) |
|
| 417 |
FARITH2(cvtqs) |
|
| 418 |
FARITH2(cvtqt) |
|
| 419 |
FARITH2(cvtlq) |
|
| 420 |
FARITH2(cvtql) |
|
| 421 |
FARITH2(cvtqlv) |
|
| 422 |
FARITH2(cvtqlsv) |
|
| 423 |
|
|
| 424 |
#define FARITH3(name) \ |
|
| 425 |
static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \ |
|
| 426 |
{ \
|
|
| 427 |
if (unlikely(rc == 31)) \ |
|
| 428 |
return; \ |
|
| 429 |
\ |
|
| 430 |
if (ra != 31) { \
|
|
| 431 |
if (rb != 31) \ |
|
| 432 |
gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]); \ |
|
| 433 |
else { \
|
|
| 434 |
TCGv tmp = tcg_const_i64(0); \ |
|
| 435 |
gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], tmp); \ |
|
| 436 |
tcg_temp_free(tmp); \ |
|
| 437 |
} \ |
|
| 438 |
} else { \
|
|
| 439 |
TCGv tmp = tcg_const_i64(0); \ |
|
| 440 |
if (rb != 31) \ |
|
| 441 |
gen_helper_ ## name (cpu_fir[rc], tmp, cpu_fir[rb]); \ |
|
| 442 |
else \ |
|
| 443 |
gen_helper_ ## name (cpu_fir[rc], tmp, tmp); \ |
|
| 444 |
tcg_temp_free(tmp); \ |
|
| 445 |
} \ |
|
| 393 | 446 |
} |
| 394 | 447 |
|
| 395 |
static always_inline void gen_fcmov (void *func, |
|
| 396 |
int ra, int rb, int rc) |
|
| 397 |
{
|
|
| 398 |
int l1; |
|
| 399 |
TCGv tmp; |
|
| 400 |
|
|
| 401 |
if (unlikely(rc == 31)) |
|
| 402 |
return; |
|
| 403 |
|
|
| 404 |
l1 = gen_new_label(); |
|
| 405 |
tmp = tcg_temp_new(TCG_TYPE_I64); |
|
| 406 |
if (ra != 31) {
|
|
| 407 |
tmp = tcg_temp_new(TCG_TYPE_I64); |
|
| 408 |
tcg_gen_helper_1_1(func, tmp, cpu_fir[ra]); |
|
| 409 |
} else {
|
|
| 410 |
tmp = tcg_const_i64(0); |
|
| 411 |
tcg_gen_helper_1_1(func, tmp, tmp); |
|
| 412 |
} |
|
| 413 |
tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1); |
|
| 414 |
if (rb != 31) |
|
| 415 |
tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); |
|
| 416 |
else |
|
| 417 |
tcg_gen_movi_i64(cpu_fir[rc], 0); |
|
| 418 |
gen_set_label(l1); |
|
| 448 |
FARITH3(addf) |
|
| 449 |
FARITH3(subf) |
|
| 450 |
FARITH3(mulf) |
|
| 451 |
FARITH3(divf) |
|
| 452 |
FARITH3(addg) |
|
| 453 |
FARITH3(subg) |
|
| 454 |
FARITH3(mulg) |
|
| 455 |
FARITH3(divg) |
|
| 456 |
FARITH3(cmpgeq) |
|
| 457 |
FARITH3(cmpglt) |
|
| 458 |
FARITH3(cmpgle) |
|
| 459 |
FARITH3(adds) |
|
| 460 |
FARITH3(subs) |
|
| 461 |
FARITH3(muls) |
|
| 462 |
FARITH3(divs) |
|
| 463 |
FARITH3(addt) |
|
| 464 |
FARITH3(subt) |
|
| 465 |
FARITH3(mult) |
|
| 466 |
FARITH3(divt) |
|
| 467 |
FARITH3(cmptun) |
|
| 468 |
FARITH3(cmpteq) |
|
| 469 |
FARITH3(cmptlt) |
|
| 470 |
FARITH3(cmptle) |
|
| 471 |
FARITH3(cpys) |
|
| 472 |
FARITH3(cpysn) |
|
| 473 |
FARITH3(cpyse) |
|
| 474 |
|
|
| 475 |
#define FCMOV(name) \ |
|
| 476 |
static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \ |
|
| 477 |
{ \
|
|
| 478 |
int l1; \ |
|
| 479 |
TCGv tmp; \ |
|
| 480 |
\ |
|
| 481 |
if (unlikely(rc == 31)) \ |
|
| 482 |
return; \ |
|
| 483 |
\ |
|
| 484 |
l1 = gen_new_label(); \ |
|
| 485 |
tmp = tcg_temp_new(); \ |
|
| 486 |
if (ra != 31) { \
|
|
| 487 |
tmp = tcg_temp_new(); \ |
|
| 488 |
gen_helper_ ## name (tmp, cpu_fir[ra]); \ |
|
| 489 |
} else { \
|
|
| 490 |
tmp = tcg_const_i64(0); \ |
|
| 491 |
gen_helper_ ## name (tmp, tmp); \ |
|
| 492 |
} \ |
|
| 493 |
tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1); \ |
|
| 494 |
if (rb != 31) \ |
|
| 495 |
tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); \ |
|
| 496 |
else \ |
|
| 497 |
tcg_gen_movi_i64(cpu_fir[rc], 0); \ |
|
| 498 |
gen_set_label(l1); \ |
|
| 419 | 499 |
} |
| 500 |
FCMOV(cmpfeq) |
|
| 501 |
FCMOV(cmpfne) |
|
| 502 |
FCMOV(cmpflt) |
|
| 503 |
FCMOV(cmpfge) |
|
| 504 |
FCMOV(cmpfle) |
|
| 505 |
FCMOV(cmpfgt) |
|
| 420 | 506 |
|
| 421 | 507 |
/* EXTWH, EXTWH, EXTLH, EXTQH */ |
| 422 | 508 |
static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
| ... | ... | |
| 434 | 520 |
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]); |
| 435 | 521 |
} else {
|
| 436 | 522 |
TCGv tmp1, tmp2; |
| 437 |
tmp1 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 523 |
tmp1 = tcg_temp_new(); |
|
| 438 | 524 |
tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7); |
| 439 | 525 |
tcg_gen_shli_i64(tmp1, tmp1, 3); |
| 440 | 526 |
tmp2 = tcg_const_i64(64); |
| ... | ... | |
| 461 | 547 |
if (islit) {
|
| 462 | 548 |
tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8); |
| 463 | 549 |
} else {
|
| 464 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 550 |
TCGv tmp = tcg_temp_new(); |
|
| 465 | 551 |
tcg_gen_andi_i64(tmp, cpu_ir[rb], 7); |
| 466 | 552 |
tcg_gen_shli_i64(tmp, tmp, 3); |
| 467 | 553 |
tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp); |
| ... | ... | |
| 474 | 560 |
} |
| 475 | 561 |
|
| 476 | 562 |
/* Code to call arith3 helpers */ |
| 477 |
static always_inline void gen_arith3 (void *helper,
|
|
| 478 |
int ra, int rb, int rc,
|
|
| 479 |
int islit, uint8_t lit)
|
|
| 480 |
{
|
|
| 481 |
if (unlikely(rc == 31)) |
|
| 482 |
return; |
|
| 483 |
|
|
| 484 |
if (ra != 31) {
|
|
| 485 |
if (islit) {
|
|
| 486 |
TCGv tmp = tcg_const_i64(lit); |
|
| 487 |
tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], tmp);
|
|
| 488 |
tcg_temp_free(tmp); |
|
| 489 |
} else |
|
| 490 |
tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
|
|
| 491 |
} else {
|
|
| 492 |
TCGv tmp1 = tcg_const_i64(0); |
|
| 493 |
if (islit) {
|
|
| 494 |
TCGv tmp2 = tcg_const_i64(lit); |
|
| 495 |
tcg_gen_helper_1_2(helper, cpu_ir[rc], tmp1, tmp2);
|
|
| 496 |
tcg_temp_free(tmp2); |
|
| 497 |
} else |
|
| 498 |
tcg_gen_helper_1_2(helper, cpu_ir[rc], tmp1, cpu_ir[rb]);
|
|
| 499 |
tcg_temp_free(tmp1); |
|
| 500 |
} |
|
| 563 |
#define ARITH3(name) \
|
|
| 564 |
static always_inline void glue(gen_, name) (int ra, int rb, int rc, \
|
|
| 565 |
int islit, uint8_t lit) \
|
|
| 566 |
{ \
|
|
| 567 |
if (unlikely(rc == 31)) \
|
|
| 568 |
return; \
|
|
| 569 |
\ |
|
| 570 |
if (ra != 31) { \
|
|
| 571 |
if (islit) { \
|
|
| 572 |
TCGv tmp = tcg_const_i64(lit); \
|
|
| 573 |
gen_helper_ ## name(cpu_ir[rc], cpu_ir[ra], tmp); \
|
|
| 574 |
tcg_temp_free(tmp); \
|
|
| 575 |
} else \
|
|
| 576 |
gen_helper_ ## name (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); \
|
|
| 577 |
} else { \
|
|
| 578 |
TCGv tmp1 = tcg_const_i64(0); \
|
|
| 579 |
if (islit) { \
|
|
| 580 |
TCGv tmp2 = tcg_const_i64(lit); \
|
|
| 581 |
gen_helper_ ## name (cpu_ir[rc], tmp1, tmp2); \
|
|
| 582 |
tcg_temp_free(tmp2); \
|
|
| 583 |
} else \
|
|
| 584 |
gen_helper_ ## name (cpu_ir[rc], tmp1, cpu_ir[rb]); \
|
|
| 585 |
tcg_temp_free(tmp1); \
|
|
| 586 |
} \
|
|
| 501 | 587 |
} |
| 588 |
ARITH3(cmpbge) |
|
| 589 |
ARITH3(addlv) |
|
| 590 |
ARITH3(sublv) |
|
| 591 |
ARITH3(addqv) |
|
| 592 |
ARITH3(subqv) |
|
| 593 |
ARITH3(mskbl) |
|
| 594 |
ARITH3(insbl) |
|
| 595 |
ARITH3(mskwl) |
|
| 596 |
ARITH3(inswl) |
|
| 597 |
ARITH3(mskll) |
|
| 598 |
ARITH3(insll) |
|
| 599 |
ARITH3(zap) |
|
| 600 |
ARITH3(zapnot) |
|
| 601 |
ARITH3(mskql) |
|
| 602 |
ARITH3(insql) |
|
| 603 |
ARITH3(mskwh) |
|
| 604 |
ARITH3(inswh) |
|
| 605 |
ARITH3(msklh) |
|
| 606 |
ARITH3(inslh) |
|
| 607 |
ARITH3(mskqh) |
|
| 608 |
ARITH3(insqh) |
|
| 609 |
ARITH3(umulh) |
|
| 610 |
ARITH3(mullv) |
|
| 611 |
ARITH3(mulqv) |
|
| 502 | 612 |
|
| 503 | 613 |
static always_inline void gen_cmp(TCGCond cond, |
| 504 | 614 |
int ra, int rb, int rc, |
| ... | ... | |
| 514 | 624 |
l2 = gen_new_label(); |
| 515 | 625 |
|
| 516 | 626 |
if (ra != 31) {
|
| 517 |
tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 627 |
tmp = tcg_temp_new(); |
|
| 518 | 628 |
tcg_gen_mov_i64(tmp, cpu_ir[ra]); |
| 519 | 629 |
} else |
| 520 | 630 |
tmp = tcg_const_i64(0); |
| ... | ... | |
| 679 | 789 |
/* S4ADDL */ |
| 680 | 790 |
if (likely(rc != 31)) {
|
| 681 | 791 |
if (ra != 31) {
|
| 682 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 792 |
TCGv tmp = tcg_temp_new(); |
|
| 683 | 793 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 2); |
| 684 | 794 |
if (islit) |
| 685 | 795 |
tcg_gen_addi_i64(tmp, tmp, lit); |
| ... | ... | |
| 717 | 827 |
/* S4SUBL */ |
| 718 | 828 |
if (likely(rc != 31)) {
|
| 719 | 829 |
if (ra != 31) {
|
| 720 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 830 |
TCGv tmp = tcg_temp_new(); |
|
| 721 | 831 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 2); |
| 722 | 832 |
if (islit) |
| 723 | 833 |
tcg_gen_subi_i64(tmp, tmp, lit); |
| ... | ... | |
| 737 | 847 |
break; |
| 738 | 848 |
case 0x0F: |
| 739 | 849 |
/* CMPBGE */ |
| 740 |
gen_arith3(helper_cmpbge, ra, rb, rc, islit, lit);
|
|
| 850 |
gen_cmpbge(ra, rb, rc, islit, lit);
|
|
| 741 | 851 |
break; |
| 742 | 852 |
case 0x12: |
| 743 | 853 |
/* S8ADDL */ |
| 744 | 854 |
if (likely(rc != 31)) {
|
| 745 | 855 |
if (ra != 31) {
|
| 746 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 856 |
TCGv tmp = tcg_temp_new(); |
|
| 747 | 857 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 3); |
| 748 | 858 |
if (islit) |
| 749 | 859 |
tcg_gen_addi_i64(tmp, tmp, lit); |
| ... | ... | |
| 763 | 873 |
/* S8SUBL */ |
| 764 | 874 |
if (likely(rc != 31)) {
|
| 765 | 875 |
if (ra != 31) {
|
| 766 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 876 |
TCGv tmp = tcg_temp_new(); |
|
| 767 | 877 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 3); |
| 768 | 878 |
if (islit) |
| 769 | 879 |
tcg_gen_subi_i64(tmp, tmp, lit); |
| ... | ... | |
| 805 | 915 |
/* S4ADDQ */ |
| 806 | 916 |
if (likely(rc != 31)) {
|
| 807 | 917 |
if (ra != 31) {
|
| 808 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 918 |
TCGv tmp = tcg_temp_new(); |
|
| 809 | 919 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 2); |
| 810 | 920 |
if (islit) |
| 811 | 921 |
tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
| ... | ... | |
| 840 | 950 |
/* S4SUBQ */ |
| 841 | 951 |
if (likely(rc != 31)) {
|
| 842 | 952 |
if (ra != 31) {
|
| 843 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 953 |
TCGv tmp = tcg_temp_new(); |
|
| 844 | 954 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 2); |
| 845 | 955 |
if (islit) |
| 846 | 956 |
tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
| ... | ... | |
| 863 | 973 |
/* S8ADDQ */ |
| 864 | 974 |
if (likely(rc != 31)) {
|
| 865 | 975 |
if (ra != 31) {
|
| 866 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 976 |
TCGv tmp = tcg_temp_new(); |
|
| 867 | 977 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 3); |
| 868 | 978 |
if (islit) |
| 869 | 979 |
tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
| ... | ... | |
| 882 | 992 |
/* S8SUBQ */ |
| 883 | 993 |
if (likely(rc != 31)) {
|
| 884 | 994 |
if (ra != 31) {
|
| 885 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 995 |
TCGv tmp = tcg_temp_new(); |
|
| 886 | 996 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 3); |
| 887 | 997 |
if (islit) |
| 888 | 998 |
tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
| ... | ... | |
| 903 | 1013 |
break; |
| 904 | 1014 |
case 0x40: |
| 905 | 1015 |
/* ADDL/V */ |
| 906 |
gen_arith3(helper_addlv, ra, rb, rc, islit, lit);
|
|
| 1016 |
gen_addlv(ra, rb, rc, islit, lit);
|
|
| 907 | 1017 |
break; |
| 908 | 1018 |
case 0x49: |
| 909 | 1019 |
/* SUBL/V */ |
| 910 |
gen_arith3(helper_sublv, ra, rb, rc, islit, lit);
|
|
| 1020 |
gen_sublv(ra, rb, rc, islit, lit);
|
|
| 911 | 1021 |
break; |
| 912 | 1022 |
case 0x4D: |
| 913 | 1023 |
/* CMPLT */ |
| ... | ... | |
| 915 | 1025 |
break; |
| 916 | 1026 |
case 0x60: |
| 917 | 1027 |
/* ADDQ/V */ |
| 918 |
gen_arith3(helper_addqv, ra, rb, rc, islit, lit);
|
|
| 1028 |
gen_addqv(ra, rb, rc, islit, lit);
|
|
| 919 | 1029 |
break; |
| 920 | 1030 |
case 0x69: |
| 921 | 1031 |
/* SUBQ/V */ |
| 922 |
gen_arith3(helper_subqv, ra, rb, rc, islit, lit);
|
|
| 1032 |
gen_subqv(ra, rb, rc, islit, lit);
|
|
| 923 | 1033 |
break; |
| 924 | 1034 |
case 0x6D: |
| 925 | 1035 |
/* CMPLE */ |
| ... | ... | |
| 1048 | 1158 |
if (islit) |
| 1049 | 1159 |
tcg_gen_movi_i64(cpu_ir[rc], helper_amask(lit)); |
| 1050 | 1160 |
else |
| 1051 |
tcg_gen_helper_1_1(helper_amask, cpu_ir[rc], cpu_ir[rb]);
|
|
| 1161 |
gen_helper_amask(cpu_ir[rc], cpu_ir[rb]);
|
|
| 1052 | 1162 |
} |
| 1053 | 1163 |
break; |
| 1054 | 1164 |
case 0x64: |
| ... | ... | |
| 1062 | 1172 |
case 0x6C: |
| 1063 | 1173 |
/* IMPLVER */ |
| 1064 | 1174 |
if (rc != 31) |
| 1065 |
tcg_gen_helper_1_0(helper_load_implver, cpu_ir[rc]);
|
|
| 1175 |
gen_helper_load_implver(cpu_ir[rc]);
|
|
| 1066 | 1176 |
break; |
| 1067 | 1177 |
default: |
| 1068 | 1178 |
goto invalid_opc; |
| ... | ... | |
| 1072 | 1182 |
switch (fn7) {
|
| 1073 | 1183 |
case 0x02: |
| 1074 | 1184 |
/* MSKBL */ |
| 1075 |
gen_arith3(helper_mskbl, ra, rb, rc, islit, lit);
|
|
| 1185 |
gen_mskbl(ra, rb, rc, islit, lit);
|
|
| 1076 | 1186 |
break; |
| 1077 | 1187 |
case 0x06: |
| 1078 | 1188 |
/* EXTBL */ |
| ... | ... | |
| 1080 | 1190 |
break; |
| 1081 | 1191 |
case 0x0B: |
| 1082 | 1192 |
/* INSBL */ |
| 1083 |
gen_arith3(helper_insbl, ra, rb, rc, islit, lit);
|
|
| 1193 |
gen_insbl(ra, rb, rc, islit, lit);
|
|
| 1084 | 1194 |
break; |
| 1085 | 1195 |
case 0x12: |
| 1086 | 1196 |
/* MSKWL */ |
| 1087 |
gen_arith3(helper_mskwl, ra, rb, rc, islit, lit);
|
|
| 1197 |
gen_mskwl(ra, rb, rc, islit, lit);
|
|
| 1088 | 1198 |
break; |
| 1089 | 1199 |
case 0x16: |
| 1090 | 1200 |
/* EXTWL */ |
| ... | ... | |
| 1092 | 1202 |
break; |
| 1093 | 1203 |
case 0x1B: |
| 1094 | 1204 |
/* INSWL */ |
| 1095 |
gen_arith3(helper_inswl, ra, rb, rc, islit, lit);
|
|
| 1205 |
gen_inswl(ra, rb, rc, islit, lit);
|
|
| 1096 | 1206 |
break; |
| 1097 | 1207 |
case 0x22: |
| 1098 | 1208 |
/* MSKLL */ |
| 1099 |
gen_arith3(helper_mskll, ra, rb, rc, islit, lit);
|
|
| 1209 |
gen_mskll(ra, rb, rc, islit, lit);
|
|
| 1100 | 1210 |
break; |
| 1101 | 1211 |
case 0x26: |
| 1102 | 1212 |
/* EXTLL */ |
| ... | ... | |
| 1104 | 1214 |
break; |
| 1105 | 1215 |
case 0x2B: |
| 1106 | 1216 |
/* INSLL */ |
| 1107 |
gen_arith3(helper_insll, ra, rb, rc, islit, lit);
|
|
| 1217 |
gen_insll(ra, rb, rc, islit, lit);
|
|
| 1108 | 1218 |
break; |
| 1109 | 1219 |
case 0x30: |
| 1110 | 1220 |
/* ZAP */ |
| 1111 |
gen_arith3(helper_zap, ra, rb, rc, islit, lit);
|
|
| 1221 |
gen_zap(ra, rb, rc, islit, lit);
|
|
| 1112 | 1222 |
break; |
| 1113 | 1223 |
case 0x31: |
| 1114 | 1224 |
/* ZAPNOT */ |
| 1115 |
gen_arith3(helper_zapnot, ra, rb, rc, islit, lit);
|
|
| 1225 |
gen_zapnot(ra, rb, rc, islit, lit);
|
|
| 1116 | 1226 |
break; |
| 1117 | 1227 |
case 0x32: |
| 1118 | 1228 |
/* MSKQL */ |
| 1119 |
gen_arith3(helper_mskql, ra, rb, rc, islit, lit);
|
|
| 1229 |
gen_mskql(ra, rb, rc, islit, lit);
|
|
| 1120 | 1230 |
break; |
| 1121 | 1231 |
case 0x34: |
| 1122 | 1232 |
/* SRL */ |
| ... | ... | |
| 1125 | 1235 |
if (islit) |
| 1126 | 1236 |
tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f); |
| 1127 | 1237 |
else {
|
| 1128 |
TCGv shift = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1238 |
TCGv shift = tcg_temp_new(); |
|
| 1129 | 1239 |
tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f); |
| 1130 | 1240 |
tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift); |
| 1131 | 1241 |
tcg_temp_free(shift); |
| ... | ... | |
| 1145 | 1255 |
if (islit) |
| 1146 | 1256 |
tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f); |
| 1147 | 1257 |
else {
|
| 1148 |
TCGv shift = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1258 |
TCGv shift = tcg_temp_new(); |
|
| 1149 | 1259 |
tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f); |
| 1150 | 1260 |
tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift); |
| 1151 | 1261 |
tcg_temp_free(shift); |
| ... | ... | |
| 1156 | 1266 |
break; |
| 1157 | 1267 |
case 0x3B: |
| 1158 | 1268 |
/* INSQL */ |
| 1159 |
gen_arith3(helper_insql, ra, rb, rc, islit, lit);
|
|
| 1269 |
gen_insql(ra, rb, rc, islit, lit);
|
|
| 1160 | 1270 |
break; |
| 1161 | 1271 |
case 0x3C: |
| 1162 | 1272 |
/* SRA */ |
| ... | ... | |
| 1165 | 1275 |
if (islit) |
| 1166 | 1276 |
tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f); |
| 1167 | 1277 |
else {
|
| 1168 |
TCGv shift = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1278 |
TCGv shift = tcg_temp_new(); |
|
| 1169 | 1279 |
tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f); |
| 1170 | 1280 |
tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift); |
| 1171 | 1281 |
tcg_temp_free(shift); |
| ... | ... | |
| 1176 | 1286 |
break; |
| 1177 | 1287 |
case 0x52: |
| 1178 | 1288 |
/* MSKWH */ |
| 1179 |
gen_arith3(helper_mskwh, ra, rb, rc, islit, lit);
|
|
| 1289 |
gen_mskwh(ra, rb, rc, islit, lit);
|
|
| 1180 | 1290 |
break; |
| 1181 | 1291 |
case 0x57: |
| 1182 | 1292 |
/* INSWH */ |
| 1183 |
gen_arith3(helper_inswh, ra, rb, rc, islit, lit);
|
|
| 1293 |
gen_inswh(ra, rb, rc, islit, lit);
|
|
| 1184 | 1294 |
break; |
| 1185 | 1295 |
case 0x5A: |
| 1186 | 1296 |
/* EXTWH */ |
| ... | ... | |
| 1188 | 1298 |
break; |
| 1189 | 1299 |
case 0x62: |
| 1190 | 1300 |
/* MSKLH */ |
| 1191 |
gen_arith3(helper_msklh, ra, rb, rc, islit, lit);
|
|
| 1301 |
gen_msklh(ra, rb, rc, islit, lit);
|
|
| 1192 | 1302 |
break; |
| 1193 | 1303 |
case 0x67: |
| 1194 | 1304 |
/* INSLH */ |
| 1195 |
gen_arith3(helper_inslh, ra, rb, rc, islit, lit);
|
|
| 1305 |
gen_inslh(ra, rb, rc, islit, lit);
|
|
| 1196 | 1306 |
break; |
| 1197 | 1307 |
case 0x6A: |
| 1198 | 1308 |
/* EXTLH */ |
| ... | ... | |
| 1200 | 1310 |
break; |
| 1201 | 1311 |
case 0x72: |
| 1202 | 1312 |
/* MSKQH */ |
| 1203 |
gen_arith3(helper_mskqh, ra, rb, rc, islit, lit);
|
|
| 1313 |
gen_mskqh(ra, rb, rc, islit, lit);
|
|
| 1204 | 1314 |
break; |
| 1205 | 1315 |
case 0x77: |
| 1206 | 1316 |
/* INSQH */ |
| 1207 |
gen_arith3(helper_insqh, ra, rb, rc, islit, lit);
|
|
| 1317 |
gen_insqh(ra, rb, rc, islit, lit);
|
|
| 1208 | 1318 |
break; |
| 1209 | 1319 |
case 0x7A: |
| 1210 | 1320 |
/* EXTQH */ |
| ... | ... | |
| 1243 | 1353 |
break; |
| 1244 | 1354 |
case 0x30: |
| 1245 | 1355 |
/* UMULH */ |
| 1246 |
gen_arith3(helper_umulh, ra, rb, rc, islit, lit);
|
|
| 1356 |
gen_umulh(ra, rb, rc, islit, lit);
|
|
| 1247 | 1357 |
break; |
| 1248 | 1358 |
case 0x40: |
| 1249 | 1359 |
/* MULL/V */ |
| 1250 |
gen_arith3(helper_mullv, ra, rb, rc, islit, lit);
|
|
| 1360 |
gen_mullv(ra, rb, rc, islit, lit);
|
|
| 1251 | 1361 |
break; |
| 1252 | 1362 |
case 0x60: |
| 1253 | 1363 |
/* MULQ/V */ |
| 1254 |
gen_arith3(helper_mulqv, ra, rb, rc, islit, lit);
|
|
| 1364 |
gen_mulqv(ra, rb, rc, islit, lit);
|
|
| 1255 | 1365 |
break; |
| 1256 | 1366 |
default: |
| 1257 | 1367 |
goto invalid_opc; |
| ... | ... | |
| 1265 | 1375 |
goto invalid_opc; |
| 1266 | 1376 |
if (likely(rc != 31)) {
|
| 1267 | 1377 |
if (ra != 31) {
|
| 1268 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1378 |
TCGv_i32 tmp = tcg_temp_new_i32();
|
|
| 1269 | 1379 |
tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
| 1270 |
tcg_gen_helper_1_1(helper_memory_to_s, cpu_fir[rc], tmp);
|
|
| 1271 |
tcg_temp_free(tmp); |
|
| 1380 |
gen_helper_memory_to_s(cpu_fir[rc], tmp);
|
|
| 1381 |
tcg_temp_free_i32(tmp);
|
|
| 1272 | 1382 |
} else |
| 1273 | 1383 |
tcg_gen_movi_i64(cpu_fir[rc], 0); |
| 1274 | 1384 |
} |
| ... | ... | |
| 1277 | 1387 |
/* SQRTF */ |
| 1278 | 1388 |
if (!(ctx->amask & AMASK_FIX)) |
| 1279 | 1389 |
goto invalid_opc; |
| 1280 |
gen_farith2(&helper_sqrtf, rb, rc);
|
|
| 1390 |
gen_fsqrtf(rb, rc);
|
|
| 1281 | 1391 |
break; |
| 1282 | 1392 |
case 0x0B: |
| 1283 | 1393 |
/* SQRTS */ |
| 1284 | 1394 |
if (!(ctx->amask & AMASK_FIX)) |
| 1285 | 1395 |
goto invalid_opc; |
| 1286 |
gen_farith2(&helper_sqrts, rb, rc);
|
|
| 1396 |
gen_fsqrts(rb, rc);
|
|
| 1287 | 1397 |
break; |
| 1288 | 1398 |
case 0x14: |
| 1289 | 1399 |
/* ITOFF */ |
| ... | ... | |
| 1291 | 1401 |
goto invalid_opc; |
| 1292 | 1402 |
if (likely(rc != 31)) {
|
| 1293 | 1403 |
if (ra != 31) {
|
| 1294 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1404 |
TCGv_i32 tmp = tcg_temp_new_i32();
|
|
| 1295 | 1405 |
tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
| 1296 |
tcg_gen_helper_1_1(helper_memory_to_f, cpu_fir[rc], tmp);
|
|
| 1297 |
tcg_temp_free(tmp); |
|
| 1406 |
gen_helper_memory_to_f(cpu_fir[rc], tmp);
|
|
| 1407 |
tcg_temp_free_i32(tmp);
|
|
| 1298 | 1408 |
} else |
| 1299 | 1409 |
tcg_gen_movi_i64(cpu_fir[rc], 0); |
| 1300 | 1410 |
} |
| ... | ... | |
| 1314 | 1424 |
/* SQRTG */ |
| 1315 | 1425 |
if (!(ctx->amask & AMASK_FIX)) |
| 1316 | 1426 |
goto invalid_opc; |
| 1317 |
gen_farith2(&helper_sqrtg, rb, rc);
|
|
| 1427 |
gen_fsqrtg(rb, rc);
|
|
| 1318 | 1428 |
break; |
| 1319 | 1429 |
case 0x02B: |
| 1320 | 1430 |
/* SQRTT */ |
| 1321 | 1431 |
if (!(ctx->amask & AMASK_FIX)) |
| 1322 | 1432 |
goto invalid_opc; |
| 1323 |
gen_farith2(&helper_sqrtt, rb, rc);
|
|
| 1433 |
gen_fsqrtt(rb, rc);
|
|
| 1324 | 1434 |
break; |
| 1325 | 1435 |
default: |
| 1326 | 1436 |
goto invalid_opc; |
| ... | ... | |
| 1332 | 1442 |
switch (fpfn) { /* f11 & 0x3F */
|
| 1333 | 1443 |
case 0x00: |
| 1334 | 1444 |
/* ADDF */ |
| 1335 |
gen_farith3(&helper_addf, ra, rb, rc);
|
|
| 1445 |
gen_faddf(ra, rb, rc);
|
|
| 1336 | 1446 |
break; |
| 1337 | 1447 |
case 0x01: |
| 1338 | 1448 |
/* SUBF */ |
| 1339 |
gen_farith3(&helper_subf, ra, rb, rc);
|
|
| 1449 |
gen_fsubf(ra, rb, rc);
|
|
| 1340 | 1450 |
break; |
| 1341 | 1451 |
case 0x02: |
| 1342 | 1452 |
/* MULF */ |
| 1343 |
gen_farith3(&helper_mulf, ra, rb, rc);
|
|
| 1453 |
gen_fmulf(ra, rb, rc);
|
|
| 1344 | 1454 |
break; |
| 1345 | 1455 |
case 0x03: |
| 1346 | 1456 |
/* DIVF */ |
| 1347 |
gen_farith3(&helper_divf, ra, rb, rc);
|
|
| 1457 |
gen_fdivf(ra, rb, rc);
|
|
| 1348 | 1458 |
break; |
| 1349 | 1459 |
case 0x1E: |
| 1350 | 1460 |
/* CVTDG */ |
| 1351 | 1461 |
#if 0 // TODO |
| 1352 |
gen_farith2(&helper_cvtdg, rb, rc);
|
|
| 1462 |
gen_fcvtdg(rb, rc);
|
|
| 1353 | 1463 |
#else |
| 1354 | 1464 |
goto invalid_opc; |
| 1355 | 1465 |
#endif |
| 1356 | 1466 |
break; |
| 1357 | 1467 |
case 0x20: |
| 1358 | 1468 |
/* ADDG */ |
| 1359 |
gen_farith3(&helper_addg, ra, rb, rc);
|
|
| 1469 |
gen_faddg(ra, rb, rc);
|
|
| 1360 | 1470 |
break; |
| 1361 | 1471 |
case 0x21: |
| 1362 | 1472 |
/* SUBG */ |
| 1363 |
gen_farith3(&helper_subg, ra, rb, rc);
|
|
| 1473 |
gen_fsubg(ra, rb, rc);
|
|
| 1364 | 1474 |
break; |
| 1365 | 1475 |
case 0x22: |
| 1366 | 1476 |
/* MULG */ |
| 1367 |
gen_farith3(&helper_mulg, ra, rb, rc);
|
|
| 1477 |
gen_fmulg(ra, rb, rc);
|
|
| 1368 | 1478 |
break; |
| 1369 | 1479 |
case 0x23: |
| 1370 | 1480 |
/* DIVG */ |
| 1371 |
gen_farith3(&helper_divg, ra, rb, rc);
|
|
| 1481 |
gen_fdivg(ra, rb, rc);
|
|
| 1372 | 1482 |
break; |
| 1373 | 1483 |
case 0x25: |
| 1374 | 1484 |
/* CMPGEQ */ |
| 1375 |
gen_farith3(&helper_cmpgeq, ra, rb, rc);
|
|
| 1485 |
gen_fcmpgeq(ra, rb, rc);
|
|
| 1376 | 1486 |
break; |
| 1377 | 1487 |
case 0x26: |
| 1378 | 1488 |
/* CMPGLT */ |
| 1379 |
gen_farith3(&helper_cmpglt, ra, rb, rc);
|
|
| 1489 |
gen_fcmpglt(ra, rb, rc);
|
|
| 1380 | 1490 |
break; |
| 1381 | 1491 |
case 0x27: |
| 1382 | 1492 |
/* CMPGLE */ |
| 1383 |
gen_farith3(&helper_cmpgle, ra, rb, rc);
|
|
| 1493 |
gen_fcmpgle(ra, rb, rc);
|
|
| 1384 | 1494 |
break; |
| 1385 | 1495 |
case 0x2C: |
| 1386 | 1496 |
/* CVTGF */ |
| 1387 |
gen_farith2(&helper_cvtgf, rb, rc);
|
|
| 1497 |
gen_fcvtgf(rb, rc);
|
|
| 1388 | 1498 |
break; |
| 1389 | 1499 |
case 0x2D: |
| 1390 | 1500 |
/* CVTGD */ |
| 1391 | 1501 |
#if 0 // TODO |
| 1392 |
gen_farith2(ctx, &helper_cvtgd, rb, rc);
|
|
| 1502 |
gen_fcvtgd(rb, rc);
|
|
| 1393 | 1503 |
#else |
| 1394 | 1504 |
goto invalid_opc; |
| 1395 | 1505 |
#endif |
| 1396 | 1506 |
break; |
| 1397 | 1507 |
case 0x2F: |
| 1398 | 1508 |
/* CVTGQ */ |
| 1399 |
gen_farith2(&helper_cvtgq, rb, rc);
|
|
| 1509 |
gen_fcvtgq(rb, rc);
|
|
| 1400 | 1510 |
break; |
| 1401 | 1511 |
case 0x3C: |
| 1402 | 1512 |
/* CVTQF */ |
| 1403 |
gen_farith2(&helper_cvtqf, rb, rc);
|
|
| 1513 |
gen_fcvtqf(rb, rc);
|
|
| 1404 | 1514 |
break; |
| 1405 | 1515 |
case 0x3E: |
| 1406 | 1516 |
/* CVTQG */ |
| 1407 |
gen_farith2(&helper_cvtqg, rb, rc);
|
|
| 1517 |
gen_fcvtqg(rb, rc);
|
|
| 1408 | 1518 |
break; |
| 1409 | 1519 |
default: |
| 1410 | 1520 |
goto invalid_opc; |
| ... | ... | |
| 1416 | 1526 |
switch (fpfn) { /* f11 & 0x3F */
|
| 1417 | 1527 |
case 0x00: |
| 1418 | 1528 |
/* ADDS */ |
| 1419 |
gen_farith3(&helper_adds, ra, rb, rc);
|
|
| 1529 |
gen_fadds(ra, rb, rc);
|
|
| 1420 | 1530 |
break; |
| 1421 | 1531 |
case 0x01: |
| 1422 | 1532 |
/* SUBS */ |
| 1423 |
gen_farith3(&helper_subs, ra, rb, rc);
|
|
| 1533 |
gen_fsubs(ra, rb, rc);
|
|
| 1424 | 1534 |
break; |
| 1425 | 1535 |
case 0x02: |
| 1426 | 1536 |
/* MULS */ |
| 1427 |
gen_farith3(&helper_muls, ra, rb, rc);
|
|
| 1537 |
gen_fmuls(ra, rb, rc);
|
|
| 1428 | 1538 |
break; |
| 1429 | 1539 |
case 0x03: |
| 1430 | 1540 |
/* DIVS */ |
| 1431 |
gen_farith3(&helper_divs, ra, rb, rc);
|
|
| 1541 |
gen_fdivs(ra, rb, rc);
|
|
| 1432 | 1542 |
break; |
| 1433 | 1543 |
case 0x20: |
| 1434 | 1544 |
/* ADDT */ |
| 1435 |
gen_farith3(&helper_addt, ra, rb, rc);
|
|
| 1545 |
gen_faddt(ra, rb, rc);
|
|
| 1436 | 1546 |
break; |
| 1437 | 1547 |
case 0x21: |
| 1438 | 1548 |
/* SUBT */ |
| 1439 |
gen_farith3(&helper_subt, ra, rb, rc);
|
|
| 1549 |
gen_fsubt(ra, rb, rc);
|
|
| 1440 | 1550 |
break; |
| 1441 | 1551 |
case 0x22: |
| 1442 | 1552 |
/* MULT */ |
| 1443 |
gen_farith3(&helper_mult, ra, rb, rc);
|
|
| 1553 |
gen_fmult(ra, rb, rc);
|
|
| 1444 | 1554 |
break; |
| 1445 | 1555 |
case 0x23: |
| 1446 | 1556 |
/* DIVT */ |
| 1447 |
gen_farith3(&helper_divt, ra, rb, rc);
|
|
| 1557 |
gen_fdivt(ra, rb, rc);
|
|
| 1448 | 1558 |
break; |
| 1449 | 1559 |
case 0x24: |
| 1450 | 1560 |
/* CMPTUN */ |
| 1451 |
gen_farith3(&helper_cmptun, ra, rb, rc);
|
|
| 1561 |
gen_fcmptun(ra, rb, rc);
|
|
| 1452 | 1562 |
break; |
| 1453 | 1563 |
case 0x25: |
| 1454 | 1564 |
/* CMPTEQ */ |
| 1455 |
gen_farith3(&helper_cmpteq, ra, rb, rc);
|
|
| 1565 |
gen_fcmpteq(ra, rb, rc);
|
|
| 1456 | 1566 |
break; |
| 1457 | 1567 |
case 0x26: |
| 1458 | 1568 |
/* CMPTLT */ |
| 1459 |
gen_farith3(&helper_cmptlt, ra, rb, rc);
|
|
| 1569 |
gen_fcmptlt(ra, rb, rc);
|
|
| 1460 | 1570 |
break; |
| 1461 | 1571 |
case 0x27: |
| 1462 | 1572 |
/* CMPTLE */ |
| 1463 |
gen_farith3(&helper_cmptle, ra, rb, rc);
|
|
| 1573 |
gen_fcmptle(ra, rb, rc);
|
|
| 1464 | 1574 |
break; |
| 1465 | 1575 |
case 0x2C: |
| 1466 | 1576 |
/* XXX: incorrect */ |
| 1467 | 1577 |
if (fn11 == 0x2AC || fn11 == 0x6AC) {
|
| 1468 | 1578 |
/* CVTST */ |
| 1469 |
gen_farith2(&helper_cvtst, rb, rc);
|
|
| 1579 |
gen_fcvtst(rb, rc);
|
|
| 1470 | 1580 |
} else {
|
| 1471 | 1581 |
/* CVTTS */ |
| 1472 |
gen_farith2(&helper_cvtts, rb, rc);
|
|
| 1582 |
gen_fcvtts(rb, rc);
|
|
| 1473 | 1583 |
} |
| 1474 | 1584 |
break; |
| 1475 | 1585 |
case 0x2F: |
| 1476 | 1586 |
/* CVTTQ */ |
| 1477 |
gen_farith2(&helper_cvttq, rb, rc);
|
|
| 1587 |
gen_fcvttq(rb, rc);
|
|
| 1478 | 1588 |
break; |
| 1479 | 1589 |
case 0x3C: |
| 1480 | 1590 |
/* CVTQS */ |
| 1481 |
gen_farith2(&helper_cvtqs, rb, rc);
|
|
| 1591 |
gen_fcvtqs(rb, rc);
|
|
| 1482 | 1592 |
break; |
| 1483 | 1593 |
case 0x3E: |
| 1484 | 1594 |
/* CVTQT */ |
| 1485 |
gen_farith2(&helper_cvtqt, rb, rc);
|
|
| 1595 |
gen_fcvtqt(rb, rc);
|
|
| 1486 | 1596 |
break; |
| 1487 | 1597 |
default: |
| 1488 | 1598 |
goto invalid_opc; |
| ... | ... | |
| 1492 | 1602 |
switch (fn11) {
|
| 1493 | 1603 |
case 0x010: |
| 1494 | 1604 |
/* CVTLQ */ |
| 1495 |
gen_farith2(&helper_cvtlq, rb, rc);
|
|
| 1605 |
gen_fcvtlq(rb, rc);
|
|
| 1496 | 1606 |
break; |
| 1497 | 1607 |
case 0x020: |
| 1498 | 1608 |
if (likely(rc != 31)) {
|
| ... | ... | |
| 1501 | 1611 |
tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); |
| 1502 | 1612 |
else |
| 1503 | 1613 |
/* CPYS */ |
| 1504 |
gen_farith3(&helper_cpys, ra, rb, rc);
|
|
| 1614 |
gen_fcpys(ra, rb, rc);
|
|
| 1505 | 1615 |
} |
| 1506 | 1616 |
break; |
| 1507 | 1617 |
case 0x021: |
| 1508 | 1618 |
/* CPYSN */ |
| 1509 |
gen_farith3(&helper_cpysn, ra, rb, rc);
|
|
| 1619 |
gen_fcpysn(ra, rb, rc);
|
|
| 1510 | 1620 |
break; |
| 1511 | 1621 |
case 0x022: |
| 1512 | 1622 |
/* CPYSE */ |
| 1513 |
gen_farith3(&helper_cpyse, ra, rb, rc);
|
|
| 1623 |
gen_fcpyse(ra, rb, rc);
|
|
| 1514 | 1624 |
break; |
| 1515 | 1625 |
case 0x024: |
| 1516 | 1626 |
/* MT_FPCR */ |
| 1517 | 1627 |
if (likely(ra != 31)) |
| 1518 |
tcg_gen_helper_0_1(helper_store_fpcr, cpu_fir[ra]);
|
|
| 1628 |
gen_helper_store_fpcr(cpu_fir[ra]);
|
|
| 1519 | 1629 |
else {
|
| 1520 | 1630 |
TCGv tmp = tcg_const_i64(0); |
| 1521 |
tcg_gen_helper_0_1(helper_store_fpcr, tmp);
|
|
| 1631 |
gen_helper_store_fpcr(tmp);
|
|
| 1522 | 1632 |
tcg_temp_free(tmp); |
| 1523 | 1633 |
} |
| 1524 | 1634 |
break; |
| 1525 | 1635 |
case 0x025: |
| 1526 | 1636 |
/* MF_FPCR */ |
| 1527 | 1637 |
if (likely(ra != 31)) |
| 1528 |
tcg_gen_helper_1_0(helper_load_fpcr, cpu_fir[ra]);
|
|
| 1638 |
gen_helper_load_fpcr(cpu_fir[ra]);
|
|
| 1529 | 1639 |
break; |
| 1530 | 1640 |
case 0x02A: |
| 1531 | 1641 |
/* FCMOVEQ */ |
| 1532 |
gen_fcmov(&helper_cmpfeq, ra, rb, rc);
|
|
| 1642 |
gen_fcmpfeq(ra, rb, rc);
|
|
| 1533 | 1643 |
break; |
| 1534 | 1644 |
case 0x02B: |
| 1535 | 1645 |
/* FCMOVNE */ |
| 1536 |
gen_fcmov(&helper_cmpfne, ra, rb, rc);
|
|
| 1646 |
gen_fcmpfne(ra, rb, rc);
|
|
| 1537 | 1647 |
break; |
| 1538 | 1648 |
case 0x02C: |
| 1539 | 1649 |
/* FCMOVLT */ |
| 1540 |
gen_fcmov(&helper_cmpflt, ra, rb, rc);
|
|
| 1650 |
gen_fcmpflt(ra, rb, rc);
|
|
| 1541 | 1651 |
break; |
| 1542 | 1652 |
case 0x02D: |
| 1543 | 1653 |
/* FCMOVGE */ |
| 1544 |
gen_fcmov(&helper_cmpfge, ra, rb, rc);
|
|
| 1654 |
gen_fcmpfge(ra, rb, rc);
|
|
| 1545 | 1655 |
break; |
| 1546 | 1656 |
case 0x02E: |
| 1547 | 1657 |
/* FCMOVLE */ |
| 1548 |
gen_fcmov(&helper_cmpfle, ra, rb, rc);
|
|
| 1658 |
gen_fcmpfle(ra, rb, rc);
|
|
| 1549 | 1659 |
break; |
| 1550 | 1660 |
case 0x02F: |
| 1551 | 1661 |
/* FCMOVGT */ |
| 1552 |
gen_fcmov(&helper_cmpfgt, ra, rb, rc);
|
|
| 1662 |
gen_fcmpfgt(ra, rb, rc);
|
|
| 1553 | 1663 |
break; |
| 1554 | 1664 |
case 0x030: |
| 1555 | 1665 |
/* CVTQL */ |
| 1556 |
gen_farith2(&helper_cvtql, rb, rc);
|
|
| 1666 |
gen_fcvtql(rb, rc);
|
|
| 1557 | 1667 |
break; |
| 1558 | 1668 |
case 0x130: |
| 1559 | 1669 |
/* CVTQL/V */ |
| 1560 |
gen_farith2(&helper_cvtqlv, rb, rc);
|
|
| 1670 |
gen_fcvtqlv(rb, rc);
|
|
| 1561 | 1671 |
break; |
| 1562 | 1672 |
case 0x530: |
| 1563 | 1673 |
/* CVTQL/SV */ |
| 1564 |
gen_farith2(&helper_cvtqlsv, rb, rc);
|
|
| 1674 |
gen_fcvtqlsv(rb, rc);
|
|
| 1565 | 1675 |
break; |
| 1566 | 1676 |
default: |
| 1567 | 1677 |
goto invalid_opc; |
| ... | ... | |
| 1598 | 1708 |
case 0xC000: |
| 1599 | 1709 |
/* RPCC */ |
| 1600 | 1710 |
if (ra != 31) |
| 1601 |
tcg_gen_helper_1_0(helper_load_pcc, cpu_ir[ra]);
|
|
| 1711 |
gen_helper_load_pcc(cpu_ir[ra]);
|
|
| 1602 | 1712 |
break; |
| 1603 | 1713 |
case 0xE000: |
| 1604 | 1714 |
/* RC */ |
| 1605 | 1715 |
if (ra != 31) |
| 1606 |
tcg_gen_helper_1_0(helper_rc, cpu_ir[ra]);
|
|
| 1716 |
gen_helper_rc(cpu_ir[ra]);
|
|
| 1607 | 1717 |
break; |
| 1608 | 1718 |
case 0xE800: |
| 1609 | 1719 |
/* ECB */ |
| ... | ... | |
| 1617 | 1727 |
case 0xF000: |
| 1618 | 1728 |
/* RS */ |
| 1619 | 1729 |
if (ra != 31) |
| 1620 |
tcg_gen_helper_1_0(helper_rs, cpu_ir[ra]);
|
|
| 1730 |
gen_helper_rs(cpu_ir[ra]);
|
|
| 1621 | 1731 |
break; |
| 1622 | 1732 |
case 0xF800: |
| 1623 | 1733 |
/* WH64 */ |
| ... | ... | |
| 1636 | 1746 |
goto invalid_opc; |
| 1637 | 1747 |
if (ra != 31) {
|
| 1638 | 1748 |
TCGv tmp = tcg_const_i32(insn & 0xFF); |
| 1639 |
tcg_gen_helper_1_2(helper_mfpr, cpu_ir[ra], tmp, cpu_ir[ra]);
|
|
| 1749 |
gen_helper_mfpr(cpu_ir[ra], tmp, cpu_ir[ra]);
|
|
| 1640 | 1750 |
tcg_temp_free(tmp); |
| 1641 | 1751 |
} |
| 1642 | 1752 |
break; |
| ... | ... | |
| 1673 | 1783 |
if (!ctx->pal_mode) |
| 1674 | 1784 |
goto invalid_opc; |
| 1675 | 1785 |
if (ra != 31) {
|
| 1676 |
TCGv addr = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1786 |
TCGv addr = tcg_temp_new(); |
|
| 1677 | 1787 |
if (rb != 31) |
| 1678 | 1788 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
| 1679 | 1789 |
else |
| ... | ... | |
| 1681 | 1791 |
switch ((insn >> 12) & 0xF) {
|
| 1682 | 1792 |
case 0x0: |
| 1683 | 1793 |
/* Longword physical access */ |
| 1684 |
tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr);
|
|
| 1794 |
gen_helper_ldl_raw(cpu_ir[ra], addr);
|
|
| 1685 | 1795 |
break; |
| 1686 | 1796 |
case 0x1: |
| 1687 | 1797 |
/* Quadword physical access */ |
| 1688 |
tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr);
|
|
| 1798 |
gen_helper_ldq_raw(cpu_ir[ra], addr);
|
|
| 1689 | 1799 |
break; |
| 1690 | 1800 |
case 0x2: |
| 1691 | 1801 |
/* Longword physical access with lock */ |
| 1692 |
tcg_gen_helper_0_2(helper_ldl_l_raw, cpu_ir[ra], addr);
|
|
| 1802 |
gen_helper_ldl_l_raw(cpu_ir[ra], addr);
|
|
| 1693 | 1803 |
break; |
| 1694 | 1804 |
case 0x3: |
| 1695 | 1805 |
/* Quadword physical access with lock */ |
| 1696 |
tcg_gen_helper_0_2(helper_ldq_l_raw, cpu_ir[ra], addr);
|
|
| 1806 |
gen_helper_ldq_l_raw(cpu_ir[ra], addr);
|
|
| 1697 | 1807 |
break; |
| 1698 | 1808 |
case 0x4: |
| 1699 | 1809 |
/* Longword virtual PTE fetch */ |
| 1700 |
tcg_gen_helper_0_2(helper_ldl_kernel, cpu_ir[ra], addr);
|
|
| 1810 |
gen_helper_ldl_kernel(cpu_ir[ra], addr);
|
|
| 1701 | 1811 |
break; |
| 1702 | 1812 |
case 0x5: |
| 1703 | 1813 |
/* Quadword virtual PTE fetch */ |
| 1704 |
tcg_gen_helper_0_2(helper_ldq_kernel, cpu_ir[ra], addr);
|
|
| 1814 |
gen_helper_ldq_kernel(cpu_ir[ra], addr);
|
|
| 1705 | 1815 |
break; |
| 1706 | 1816 |
case 0x6: |
| 1707 | 1817 |
/* Incpu_ir[ra]id */ |
| ... | ... | |
| 1711 | 1821 |
goto incpu_ir[ra]id_opc; |
| 1712 | 1822 |
case 0x8: |
| 1713 | 1823 |
/* Longword virtual access */ |
| 1714 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
|
|
| 1715 |
tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr);
|
|
| 1824 |
gen_helper_st_virt_to_phys(addr, addr);
|
|
| 1825 |
gen_helper_ldl_raw(cpu_ir[ra], addr);
|
|
| 1716 | 1826 |
break; |
| 1717 | 1827 |
case 0x9: |
| 1718 | 1828 |
/* Quadword virtual access */ |
| 1719 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
|
|
| 1720 |
tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr);
|
|
| 1829 |
gen_helper_st_virt_to_phys(addr, addr);
|
|
| 1830 |
gen_helper_ldq_raw(cpu_ir[ra], addr);
|
|
| 1721 | 1831 |
break; |
| 1722 | 1832 |
case 0xA: |
| 1723 | 1833 |
/* Longword virtual access with protection check */ |
| ... | ... | |
| 1729 | 1839 |
break; |
| 1730 | 1840 |
case 0xC: |
| 1731 | 1841 |
/* Longword virtual access with altenate access mode */ |
| 1732 |
tcg_gen_helper_0_0(helper_set_alt_mode);
|
|
| 1733 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
|
|
| 1734 |
tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr);
|
|
| 1735 |
tcg_gen_helper_0_0(helper_restore_mode);
|
|
| 1842 |
gen_helper_set_alt_mode();
|
|
| 1843 |
gen_helper_st_virt_to_phys(addr, addr);
|
|
| 1844 |
gen_helper_ldl_raw(cpu_ir[ra], addr);
|
|
| 1845 |
gen_helper_restore_mode();
|
|
| 1736 | 1846 |
break; |
| 1737 | 1847 |
case 0xD: |
| 1738 | 1848 |
/* Quadword virtual access with altenate access mode */ |
| 1739 |
tcg_gen_helper_0_0(helper_set_alt_mode);
|
|
| 1740 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
|
|
| 1741 |
tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr);
|
|
| 1742 |
tcg_gen_helper_0_0(helper_restore_mode);
|
|
| 1849 |
gen_helper_set_alt_mode();
|
|
| 1850 |
gen_helper_st_virt_to_phys(addr, addr);
|
|
| 1851 |
gen_helper_ldq_raw(cpu_ir[ra], addr);
|
|
| 1852 |
gen_helper_restore_mode();
|
|
| 1743 | 1853 |
break; |
| 1744 | 1854 |
case 0xE: |
| 1745 | 1855 |
/* Longword virtual access with alternate access mode and |
| 1746 | 1856 |
* protection checks |
| 1747 | 1857 |
*/ |
| 1748 |
tcg_gen_helper_0_0(helper_set_alt_mode);
|
|
| 1749 |
tcg_gen_helper_0_2(helper_ldl_data, cpu_ir[ra], addr);
|
|
| 1750 |
tcg_gen_helper_0_0(helper_restore_mode);
|
|
| 1858 |
gen_helper_set_alt_mode();
|
|
| 1859 |
gen_helper_ldl_data(cpu_ir[ra], addr);
|
|
| 1860 |
gen_helper_restore_mode();
|
|
| 1751 | 1861 |
break; |
| 1752 | 1862 |
case 0xF: |
| 1753 | 1863 |
/* Quadword virtual access with alternate access mode and |
| 1754 | 1864 |
* protection checks |
| 1755 | 1865 |
*/ |
| 1756 |
tcg_gen_helper_0_0(helper_set_alt_mode);
|
|
| 1757 |
tcg_gen_helper_0_2(helper_ldq_data, cpu_ir[ra], addr);
|
|
| 1758 |
tcg_gen_helper_0_0(helper_restore_mode);
|
|
| 1866 |
gen_helper_set_alt_mode();
|
|
| 1867 |
gen_helper_ldq_data(cpu_ir[ra], addr);
|
|
| 1868 |
gen_helper_restore_mode();
|
|
| 1759 | 1869 |
break; |
| 1760 | 1870 |
} |
| 1761 | 1871 |
tcg_temp_free(addr); |
| ... | ... | |
| 1794 | 1904 |
if (islit) |
| 1795 | 1905 |
tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit)); |
| 1796 | 1906 |
else |
| 1797 |
tcg_gen_helper_1_1(helper_ctpop, cpu_ir[rc], cpu_ir[rb]);
|
|
| 1907 |
gen_helper_ctpop(cpu_ir[rc], cpu_ir[rb]);
|
|
| 1798 | 1908 |
} |
| 1799 | 1909 |
break; |
| 1800 | 1910 |
case 0x31: |
| ... | ... | |
| 1812 | 1922 |
if (islit) |
| 1813 | 1923 |
tcg_gen_movi_i64(cpu_ir[rc], clz64(lit)); |
| 1814 | 1924 |
else |
| 1815 |
tcg_gen_helper_1_1(helper_ctlz, cpu_ir[rc], cpu_ir[rb]);
|
|
| 1925 |
gen_helper_ctlz(cpu_ir[rc], cpu_ir[rb]);
|
|
| 1816 | 1926 |
} |
| 1817 | 1927 |
break; |
| 1818 | 1928 |
case 0x33: |
| ... | ... | |
| 1823 | 1933 |
if (islit) |
| 1824 | 1934 |
tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit)); |
| 1825 | 1935 |
else |
| 1826 |
tcg_gen_helper_1_1(helper_cttz, cpu_ir[rc], cpu_ir[rb]);
|
|
| 1936 |
gen_helper_cttz(cpu_ir[rc], cpu_ir[rb]);
|
|
| 1827 | 1937 |
} |
| 1828 | 1938 |
break; |
| 1829 | 1939 |
case 0x34: |
| ... | ... | |
| 1926 | 2036 |
if (!(ctx->amask & AMASK_FIX)) |
| 1927 | 2037 |
goto invalid_opc; |
| 1928 | 2038 |
if (rc != 31) {
|
| 1929 |
TCGv tmp1 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 2039 |
TCGv_i32 tmp1 = tcg_temp_new_i32();
|
|
| 1930 | 2040 |
if (ra != 31) |
| 1931 |
tcg_gen_helper_1_1(helper_s_to_memory, tmp1, cpu_fir[ra]);
|
|
| 2041 |
gen_helper_s_to_memory(tmp1, cpu_fir[ra]);
|
|
| 1932 | 2042 |
else {
|
| 1933 | 2043 |
TCGv tmp2 = tcg_const_i64(0); |
| 1934 |
tcg_gen_helper_1_1(helper_s_to_memory, tmp1, tmp2);
|
|
| 2044 |
gen_helper_s_to_memory(tmp1, tmp2);
|
|
| 1935 | 2045 |
tcg_temp_free(tmp2); |
| 1936 | 2046 |
} |
| 1937 | 2047 |
tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1); |
| 1938 |
tcg_temp_free(tmp1); |
|
| 2048 |
tcg_temp_free_i32(tmp1);
|
|
| 1939 | 2049 |
} |
| 1940 | 2050 |
break; |
| 1941 | 2051 |
default: |
| ... | ... | |
| 1952 | 2062 |
else {
|
| 1953 | 2063 |
TCGv tmp1 = tcg_const_i32(insn & 0xFF); |
| 1954 | 2064 |
if (ra != 31) |
| 1955 |
tcg_gen_helper(helper_mtpr, tmp1, cpu_ir[ra]);
|
|
| 2065 |
gen_helper_mtpr(tmp1, cpu_ir[ra]);
|
|
| 1956 | 2066 |
else {
|
| 1957 | 2067 |
TCGv tmp2 = tcg_const_i64(0); |
| 1958 |
tcg_gen_helper(helper_mtpr, tmp1, tmp2);
|
|
| 2068 |
gen_helper_mtpr(tmp1, tmp2);
|
|
| 1959 | 2069 |
tcg_temp_free(tmp2); |
| 1960 | 2070 |
} |
| 1961 | 2071 |
tcg_temp_free(tmp1); |
| ... | ... | |
| 1972 | 2082 |
goto invalid_opc; |
| 1973 | 2083 |
if (rb == 31) {
|
| 1974 | 2084 |
/* "Old" alpha */ |
| 1975 |
tcg_gen_helper_0_0(helper_hw_rei);
|
|
| 2085 |
gen_helper_hw_rei();
|
|
| 1976 | 2086 |
} else {
|
| 1977 | 2087 |
TCGv tmp; |
| 1978 | 2088 |
|
| 1979 | 2089 |
if (ra != 31) {
|
| 1980 |
tmp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 2090 |
tmp = tcg_temp_new(); |
|
| 1981 | 2091 |
tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51)); |
| 1982 | 2092 |
} else |
| 1983 | 2093 |
tmp = tcg_const_i64(((int64_t)insn << 51) >> 51); |
| 1984 |
tcg_gen_helper_0_1(helper_hw_ret, tmp);
|
|
| 2094 |
gen_helper_hw_ret(tmp);
|
|
| 1985 | 2095 |
tcg_temp_free(tmp); |
| 1986 | 2096 |
} |
| 1987 | 2097 |
ret = 2; |
| ... | ... | |
| 1996 | 2106 |
goto invalid_opc; |
| 1997 | 2107 |
else {
|
| 1998 | 2108 |
TCGv addr, val; |
| 1999 |
addr = tcg_temp_new(TCG_TYPE_I64);
|
|
| 2109 |
addr = tcg_temp_new(); |
|
| 2000 | 2110 |
if (rb != 31) |
| 2001 | 2111 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
| 2002 | 2112 |
else |
| ... | ... | |
| 2004 | 2114 |
if (ra != 31) |
| 2005 | 2115 |
val = cpu_ir[ra]; |
| 2006 | 2116 |
else {
|
| 2007 |
val = tcg_temp_new(TCG_TYPE_I64);
|
|
| 2117 |
val = tcg_temp_new(); |
|
| 2008 | 2118 |
tcg_gen_movi_i64(val, 0); |
| 2009 | 2119 |
} |
| 2010 | 2120 |
switch ((insn >> 12) & 0xF) {
|
| 2011 | 2121 |
case 0x0: |
| 2012 | 2122 |
/* Longword physical access */ |
| 2013 |
tcg_gen_helper_0_2(helper_stl_raw, val, addr);
|
|
| 2123 |
gen_helper_stl_raw(val, addr);
|
|
| 2014 | 2124 |
break; |
| 2015 | 2125 |
case 0x1: |
| 2016 | 2126 |
/* Quadword physical access */ |
| 2017 |
tcg_gen_helper_0_2(helper_stq_raw, val, addr);
|
|
| 2127 |
gen_helper_stq_raw(val, addr);
|
|
| 2018 | 2128 |
break; |
| 2019 | 2129 |
case 0x2: |
| 2020 | 2130 |
/* Longword physical access with lock */ |
| 2021 |
tcg_gen_helper_1_2(helper_stl_c_raw, val, val, addr);
|
|
| 2131 |
gen_helper_stl_c_raw(val, val, addr);
|
|
| 2022 | 2132 |
break; |
| 2023 | 2133 |
case 0x3: |
| 2024 | 2134 |
/* Quadword physical access with lock */ |
| 2025 |
tcg_gen_helper_1_2(helper_stq_c_raw, val, val, addr);
|
|
| 2135 |
gen_helper_stq_c_raw(val, val, addr);
|
|
| 2026 | 2136 |
break; |
| 2027 | 2137 |
case 0x4: |
| 2028 | 2138 |
/* Longword virtual access */ |
| 2029 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
|
|
| 2030 |
tcg_gen_helper_0_2(helper_stl_raw, val, addr);
|
|
| 2139 |
gen_helper_st_virt_to_phys(addr, addr);
|
|
| 2140 |
gen_helper_stl_raw(val, addr);
|
|
| 2031 | 2141 |
break; |
| 2032 | 2142 |
case 0x5: |
| 2033 | 2143 |
/* Quadword virtual access */ |
| 2034 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
|
|
| 2035 |
tcg_gen_helper_0_2(helper_stq_raw, val, addr);
|
|
| 2144 |
gen_helper_st_virt_to_phys(addr, addr);
|
|
| 2145 |
gen_helper_stq_raw(val, addr);
|
|
| 2036 | 2146 |
break; |
| 2037 | 2147 |
case 0x6: |
| 2038 | 2148 |
/* Invalid */ |
| ... | ... | |
| 2054 | 2164 |
goto invalid_opc; |
| 2055 | 2165 |
case 0xC: |
| 2056 | 2166 |
/* Longword virtual access with alternate access mode */ |
| 2057 |
tcg_gen_helper_0_0(helper_set_alt_mode);
|
|
| 2058 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
|
|
| 2059 |
tcg_gen_helper_0_2(helper_stl_raw, val, addr);
|
|
| 2060 |
tcg_gen_helper_0_0(helper_restore_mode);
|
|
| 2167 |
gen_helper_set_alt_mode();
|
|
| 2168 |
gen_helper_st_virt_to_phys(addr, addr);
|
|
| 2169 |
gen_helper_stl_raw(val, addr);
|
|
| 2170 |
gen_helper_restore_mode();
|
|
| 2061 | 2171 |
break; |
| 2062 | 2172 |
case 0xD: |
| 2063 | 2173 |
/* Quadword virtual access with alternate access mode */ |
| 2064 |
tcg_gen_helper_0_0(helper_set_alt_mode);
|
|
| 2065 |
tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr);
|
|
| 2066 |
tcg_gen_helper_0_2(helper_stl_raw, val, addr);
|
|
| 2067 |
tcg_gen_helper_0_0(helper_restore_mode);
|
|
| 2174 |
gen_helper_set_alt_mode();
|
|
| 2175 |
gen_helper_st_virt_to_phys(addr, addr);
|
|
| 2176 |
gen_helper_stl_raw(val, addr);
|
|
| 2177 |
gen_helper_restore_mode();
|
|
| 2068 | 2178 |
break; |
| 2069 | 2179 |
case 0xE: |
| 2070 | 2180 |
/* Invalid */ |
| ... | ... | |
| 2151 | 2261 |
tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2)); |
| 2152 | 2262 |
ret = 1; |
| 2153 | 2263 |
break; |
| 2154 |
case 0x31: |
|
| 2155 |
/* FBEQ */ |
|
| 2156 |
gen_fbcond(ctx, &helper_cmpfeq, ra, disp16); |
|
| 2157 |
ret = 1; |
|
| 2158 |
break; |
|
| 2159 |
case 0x32: |
|
| 2160 |
/* FBLT */ |
|
| 2161 |
gen_fbcond(ctx, &helper_cmpflt, ra, disp16); |
|
| 2162 |
ret = 1; |
|
| 2163 |
break; |
|
| 2164 |
case 0x33: |
|
| 2165 |
/* FBLE */ |
|
| 2166 |
gen_fbcond(ctx, &helper_cmpfle, ra, disp16); |
|
| 2264 |
case 0x31: /* FBEQ */ |
|
| 2265 |
case 0x32: /* FBLT */ |
|
| 2266 |
case 0x33: /* FBLE */ |
|
| 2267 |
gen_fbcond(ctx, opc, ra, disp16); |
|
| 2167 | 2268 |
ret = 1; |
| 2168 | 2269 |
break; |
Also available in: Unified diff