Revision a7812ae4 target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 29 | 29 |
#include "cpu.h" |
| 30 | 30 |
#include "exec-all.h" |
| 31 | 31 |
#include "disas.h" |
| 32 |
#include "helper.h" |
|
| 33 | 32 |
#include "tcg-op.h" |
| 34 | 33 |
#include "qemu-common.h" |
| 35 | 34 |
|
| 35 |
#include "helper.h" |
|
| 36 |
#define GEN_HELPER 1 |
|
| 37 |
#include "helper.h" |
|
| 38 |
|
|
| 36 | 39 |
//#define MIPS_DEBUG_DISAS |
| 37 | 40 |
//#define MIPS_DEBUG_SIGN_EXTENSIONS |
| 38 | 41 |
//#define MIPS_SINGLE_STEP |
| ... | ... | |
| 423 | 426 |
}; |
| 424 | 427 |
|
| 425 | 428 |
/* global register indices */ |
| 426 |
static TCGv cpu_env, cpu_gpr[32], cpu_PC; |
|
| 429 |
static TCGv_ptr cpu_env; |
|
| 430 |
static TCGv cpu_gpr[32], cpu_PC; |
|
| 427 | 431 |
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC]; |
| 428 |
static TCGv cpu_dspctrl, bcond, btarget; |
|
| 429 |
static TCGv fpu_fpr32[32], fpu_fpr32h[32], fpu_fpr64[32], fpu_fcr0, fpu_fcr31; |
|
| 432 |
static TCGv cpu_dspctrl, btarget; |
|
| 433 |
static TCGv_i32 bcond; |
|
| 434 |
static TCGv_i32 fpu_fpr32[32], fpu_fpr32h[32]; |
|
| 435 |
static TCGv_i64 fpu_fpr64[32]; |
|
| 436 |
static TCGv_i32 fpu_fcr0, fpu_fcr31; |
|
| 430 | 437 |
|
| 431 | 438 |
#include "gen-icount.h" |
| 432 | 439 |
|
| 433 |
static inline void tcg_gen_helper_0_i(void *func, uint32_t arg) |
|
| 434 |
|
|
| 435 |
{
|
|
| 436 |
TCGv tmp = tcg_const_i32(arg); |
|
| 437 |
|
|
| 438 |
tcg_gen_helper_0_1(func, tmp); |
|
| 439 |
tcg_temp_free(tmp); |
|
| 440 |
} |
|
| 441 |
|
|
| 442 |
static inline void tcg_gen_helper_0_ii(void *func, uint32_t arg1, uint32_t arg2) |
|
| 443 |
{
|
|
| 444 |
TCGv tmp1 = tcg_const_i32(arg1); |
|
| 445 |
TCGv tmp2 = tcg_const_i32(arg2); |
|
| 446 |
|
|
| 447 |
tcg_gen_helper_0_2(func, tmp1, tmp2); |
|
| 448 |
tcg_temp_free(tmp1); |
|
| 449 |
tcg_temp_free(tmp2); |
|
| 450 |
} |
|
| 451 |
|
|
| 452 |
static inline void tcg_gen_helper_0_1i(void *func, TCGv arg1, uint32_t arg2) |
|
| 453 |
{
|
|
| 454 |
TCGv tmp = tcg_const_i32(arg2); |
|
| 455 |
|
|
| 456 |
tcg_gen_helper_0_2(func, arg1, tmp); |
|
| 457 |
tcg_temp_free(tmp); |
|
| 458 |
} |
|
| 459 |
|
|
| 460 |
static inline void tcg_gen_helper_0_2i(void *func, TCGv arg1, TCGv arg2, uint32_t arg3) |
|
| 461 |
{
|
|
| 462 |
TCGv tmp = tcg_const_i32(arg3); |
|
| 463 |
|
|
| 464 |
tcg_gen_helper_0_3(func, arg1, arg2, tmp); |
|
| 465 |
tcg_temp_free(tmp); |
|
| 466 |
} |
|
| 467 |
|
|
| 468 |
static inline void tcg_gen_helper_0_1ii(void *func, TCGv arg1, uint32_t arg2, uint32_t arg3) |
|
| 469 |
{
|
|
| 470 |
TCGv tmp1 = tcg_const_i32(arg2); |
|
| 471 |
TCGv tmp2 = tcg_const_i32(arg3); |
|
| 472 |
|
|
| 473 |
tcg_gen_helper_0_3(func, arg1, tmp1, tmp2); |
|
| 474 |
tcg_temp_free(tmp1); |
|
| 475 |
tcg_temp_free(tmp2); |
|
| 476 |
} |
|
| 477 |
|
|
| 478 |
static inline void tcg_gen_helper_1_i(void *func, TCGv ret, uint32_t arg) |
|
| 479 |
{
|
|
| 480 |
TCGv tmp = tcg_const_i32(arg); |
|
| 481 |
|
|
| 482 |
tcg_gen_helper_1_1(func, ret, tmp); |
|
| 483 |
tcg_temp_free(tmp); |
|
| 484 |
} |
|
| 485 |
|
|
| 486 |
static inline void tcg_gen_helper_1_1i(void *func, TCGv ret, TCGv arg1, uint32_t arg2) |
|
| 487 |
{
|
|
| 488 |
TCGv tmp = tcg_const_i32(arg2); |
|
| 489 |
|
|
| 490 |
tcg_gen_helper_1_2(func, ret, arg1, tmp); |
|
| 491 |
tcg_temp_free(tmp); |
|
| 492 |
} |
|
| 493 |
|
|
| 494 |
static inline void tcg_gen_helper_1_1ii(void *func, TCGv ret, TCGv arg1, uint32_t arg2, uint32_t arg3) |
|
| 495 |
{
|
|
| 496 |
TCGv tmp1 = tcg_const_i32(arg2); |
|
| 497 |
TCGv tmp2 = tcg_const_i32(arg3); |
|
| 498 |
|
|
| 499 |
tcg_gen_helper_1_3(func, ret, arg1, tmp1, tmp2); |
|
| 500 |
tcg_temp_free(tmp1); |
|
| 501 |
tcg_temp_free(tmp2); |
|
| 502 |
} |
|
| 503 |
|
|
| 504 |
static inline void tcg_gen_helper_1_2i(void *func, TCGv ret, TCGv arg1, TCGv arg2, uint32_t arg3) |
|
| 505 |
{
|
|
| 506 |
TCGv tmp = tcg_const_i32(arg3); |
|
| 440 |
#define gen_helper_0i(name, arg) do { \
|
|
| 441 |
TCGv_i32 helper_tmp = tcg_const_i32(arg); \ |
|
| 442 |
gen_helper_##name(helper_tmp); \ |
|
| 443 |
tcg_temp_free_i32(helper_tmp); \ |
|
| 444 |
} while(0) |
|
| 507 | 445 |
|
| 508 |
tcg_gen_helper_1_3(func, ret, arg1, arg2, tmp); |
|
| 509 |
tcg_temp_free(tmp); |
|
| 510 |
} |
|
| 446 |
#define gen_helper_1i(name, arg1, arg2) do { \
|
|
| 447 |
TCGv_i32 helper_tmp = tcg_const_i32(arg2); \ |
|
| 448 |
gen_helper_##name(arg1, helper_tmp); \ |
|
| 449 |
tcg_temp_free_i32(helper_tmp); \ |
|
| 450 |
} while(0) |
|
| 511 | 451 |
|
| 512 |
static inline void tcg_gen_helper_1_2ii(void *func, TCGv ret, TCGv arg1, TCGv arg2, uint32_t arg3, uint32_t arg4) |
|
| 513 |
{
|
|
| 514 |
TCGv tmp1 = tcg_const_i32(arg3); |
|
| 515 |
TCGv tmp2 = tcg_const_i32(arg4); |
|
| 452 |
#define gen_helper_2i(name, arg1, arg2, arg3) do { \
|
|
| 453 |
TCGv_i32 helper_tmp = tcg_const_i32(arg3); \ |
|
| 454 |
gen_helper_##name(arg1, arg2, helper_tmp); \ |
|
| 455 |
tcg_temp_free_i32(helper_tmp); \ |
|
| 456 |
} while(0) |
|
| 516 | 457 |
|
| 517 |
tcg_gen_helper_1_4(func, ret, arg1, arg2, tmp1, tmp2); |
|
| 518 |
tcg_temp_free(tmp1); |
|
| 519 |
tcg_temp_free(tmp2); |
|
| 520 |
} |
|
| 458 |
#define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
|
|
| 459 |
TCGv_i32 helper_tmp = tcg_const_i32(arg4); \ |
|
| 460 |
gen_helper_##name(arg1, arg2, arg3, helper_tmp); \ |
|
| 461 |
tcg_temp_free_i32(helper_tmp); \ |
|
| 462 |
} while(0) |
|
| 521 | 463 |
|
| 522 | 464 |
typedef struct DisasContext {
|
| 523 | 465 |
struct TranslationBlock *tb; |
| ... | ... | |
| 618 | 560 |
/* Moves to/from shadow registers. */ |
| 619 | 561 |
static inline void gen_load_srsgpr (int from, int to) |
| 620 | 562 |
{
|
| 621 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 563 |
TCGv r_tmp1 = tcg_temp_new(); |
|
| 622 | 564 |
|
| 623 | 565 |
if (from == 0) |
| 624 | 566 |
tcg_gen_movi_tl(r_tmp1, 0); |
| 625 | 567 |
else {
|
| 626 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32); |
|
| 568 |
TCGv_i32 r_tmp2 = tcg_temp_new_i32(); |
|
| 569 |
TCGv_ptr addr = tcg_temp_new_ptr(); |
|
| 627 | 570 |
|
| 628 | 571 |
tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); |
| 629 | 572 |
tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS); |
| 630 | 573 |
tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf); |
| 631 | 574 |
tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32); |
| 632 |
tcg_gen_add_i32(r_tmp2, cpu_env, r_tmp2); |
|
| 575 |
tcg_gen_ext_i32_ptr(addr, r_tmp2); |
|
| 576 |
tcg_gen_add_ptr(addr, cpu_env, addr); |
|
| 633 | 577 |
|
| 634 |
tcg_gen_ld_tl(r_tmp1, r_tmp2, sizeof(target_ulong) * from); |
|
| 635 |
tcg_temp_free(r_tmp2); |
|
| 578 |
tcg_gen_ld_tl(r_tmp1, addr, sizeof(target_ulong) * from); |
|
| 579 |
tcg_temp_free_ptr(addr); |
|
| 580 |
tcg_temp_free_i32(r_tmp2); |
|
| 636 | 581 |
} |
| 637 | 582 |
gen_store_gpr(r_tmp1, to); |
| 638 | 583 |
tcg_temp_free(r_tmp1); |
| ... | ... | |
| 641 | 586 |
static inline void gen_store_srsgpr (int from, int to) |
| 642 | 587 |
{
|
| 643 | 588 |
if (to != 0) {
|
| 644 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL); |
|
| 645 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32); |
|
| 589 |
TCGv r_tmp1 = tcg_temp_new(); |
|
| 590 |
TCGv_i32 r_tmp2 = tcg_temp_new_i32(); |
|
| 591 |
TCGv_ptr addr = tcg_temp_new_ptr(); |
|
| 646 | 592 |
|
| 647 | 593 |
gen_load_gpr(r_tmp1, from); |
| 648 | 594 |
tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); |
| 649 | 595 |
tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS); |
| 650 | 596 |
tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf); |
| 651 | 597 |
tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32); |
| 652 |
tcg_gen_add_i32(r_tmp2, cpu_env, r_tmp2); |
|
| 598 |
tcg_gen_ext_i32_ptr(addr, r_tmp2); |
|
| 599 |
tcg_gen_add_ptr(addr, cpu_env, addr); |
|
| 653 | 600 |
|
| 654 |
tcg_gen_st_tl(r_tmp1, r_tmp2, sizeof(target_ulong) * to); |
|
| 601 |
tcg_gen_st_tl(r_tmp1, addr, sizeof(target_ulong) * to); |
|
| 602 |
tcg_temp_free_ptr(addr); |
|
| 603 |
tcg_temp_free_i32(r_tmp2); |
|
| 655 | 604 |
tcg_temp_free(r_tmp1); |
| 656 |
tcg_temp_free(r_tmp2); |
|
| 657 | 605 |
} |
| 658 | 606 |
} |
| 659 | 607 |
|
| 660 | 608 |
/* Floating point register moves. */ |
| 661 |
static inline void gen_load_fpr32 (TCGv t, int reg) |
|
| 609 |
static inline void gen_load_fpr32 (TCGv_i32 t, int reg)
|
|
| 662 | 610 |
{
|
| 663 | 611 |
tcg_gen_mov_i32(t, fpu_fpr32[reg]); |
| 664 | 612 |
} |
| 665 | 613 |
|
| 666 |
static inline void gen_store_fpr32 (TCGv t, int reg) |
|
| 614 |
static inline void gen_store_fpr32 (TCGv_i32 t, int reg)
|
|
| 667 | 615 |
{
|
| 668 | 616 |
tcg_gen_mov_i32(fpu_fpr32[reg], t); |
| 669 | 617 |
} |
| 670 | 618 |
|
| 671 |
static inline void gen_load_fpr64 (DisasContext *ctx, TCGv t, int reg) |
|
| 619 |
static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
|
|
| 672 | 620 |
{
|
| 673 | 621 |
if (ctx->hflags & MIPS_HFLAG_F64) |
| 674 | 622 |
tcg_gen_mov_i64(t, fpu_fpr64[reg]); |
| ... | ... | |
| 677 | 625 |
} |
| 678 | 626 |
} |
| 679 | 627 |
|
| 680 |
static inline void gen_store_fpr64 (DisasContext *ctx, TCGv t, int reg) |
|
| 628 |
static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
|
|
| 681 | 629 |
{
|
| 682 | 630 |
if (ctx->hflags & MIPS_HFLAG_F64) |
| 683 | 631 |
tcg_gen_mov_i64(fpu_fpr64[reg], t); |
| ... | ... | |
| 688 | 636 |
} |
| 689 | 637 |
} |
| 690 | 638 |
|
| 691 |
static inline void gen_load_fpr32h (TCGv t, int reg) |
|
| 639 |
static inline void gen_load_fpr32h (TCGv_i32 t, int reg)
|
|
| 692 | 640 |
{
|
| 693 | 641 |
tcg_gen_mov_i32(t, fpu_fpr32h[reg]); |
| 694 | 642 |
} |
| 695 | 643 |
|
| 696 |
static inline void gen_store_fpr32h (TCGv t, int reg) |
|
| 644 |
static inline void gen_store_fpr32h (TCGv_i32 t, int reg)
|
|
| 697 | 645 |
{
|
| 698 | 646 |
tcg_gen_mov_i32(fpu_fpr32h[reg], t); |
| 699 | 647 |
} |
| 700 | 648 |
|
| 701 |
static inline void get_fp_cond (TCGv t) |
|
| 649 |
static inline void get_fp_cond (TCGv_i32 t)
|
|
| 702 | 650 |
{
|
| 703 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 704 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 651 |
TCGv_i32 r_tmp1 = tcg_temp_new_i32();
|
|
| 652 |
TCGv_i32 r_tmp2 = tcg_temp_new_i32();
|
|
| 705 | 653 |
|
| 706 | 654 |
tcg_gen_shri_i32(r_tmp2, fpu_fcr31, 24); |
| 707 | 655 |
tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xfe); |
| 708 | 656 |
tcg_gen_shri_i32(r_tmp1, fpu_fcr31, 23); |
| 709 | 657 |
tcg_gen_andi_i32(r_tmp1, r_tmp1, 0x1); |
| 710 | 658 |
tcg_gen_or_i32(t, r_tmp1, r_tmp2); |
| 711 |
tcg_temp_free(r_tmp1); |
|
| 712 |
tcg_temp_free(r_tmp2); |
|
| 659 |
tcg_temp_free_i32(r_tmp1);
|
|
| 660 |
tcg_temp_free_i32(r_tmp2);
|
|
| 713 | 661 |
} |
| 714 | 662 |
|
| 715 |
typedef void (fcmp_fun32)(uint32_t, uint32_t, int); |
|
| 716 |
typedef void (fcmp_fun64)(uint64_t, uint64_t, int); |
|
| 717 |
|
|
| 718 |
#define FOP_CONDS(fcmp_fun, type, fmt) \ |
|
| 719 |
static fcmp_fun * fcmp ## type ## _ ## fmt ## _table[16] = { \
|
|
| 720 |
do_cmp ## type ## _ ## fmt ## _f, \ |
|
| 721 |
do_cmp ## type ## _ ## fmt ## _un, \ |
|
| 722 |
do_cmp ## type ## _ ## fmt ## _eq, \ |
|
| 723 |
do_cmp ## type ## _ ## fmt ## _ueq, \ |
|
| 724 |
do_cmp ## type ## _ ## fmt ## _olt, \ |
|
| 725 |
do_cmp ## type ## _ ## fmt ## _ult, \ |
|
| 726 |
do_cmp ## type ## _ ## fmt ## _ole, \ |
|
| 727 |
do_cmp ## type ## _ ## fmt ## _ule, \ |
|
| 728 |
do_cmp ## type ## _ ## fmt ## _sf, \ |
|
| 729 |
do_cmp ## type ## _ ## fmt ## _ngle, \ |
|
| 730 |
do_cmp ## type ## _ ## fmt ## _seq, \ |
|
| 731 |
do_cmp ## type ## _ ## fmt ## _ngl, \ |
|
| 732 |
do_cmp ## type ## _ ## fmt ## _lt, \ |
|
| 733 |
do_cmp ## type ## _ ## fmt ## _nge, \ |
|
| 734 |
do_cmp ## type ## _ ## fmt ## _le, \ |
|
| 735 |
do_cmp ## type ## _ ## fmt ## _ngt, \ |
|
| 736 |
}; \ |
|
| 737 |
static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv a, TCGv b, int cc) \ |
|
| 663 |
#define FOP_CONDS(type, fmt, bits) \ |
|
| 664 |
static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv_i##bits a, \ |
|
| 665 |
TCGv_i##bits b, int cc) \ |
|
| 738 | 666 |
{ \
|
| 739 |
tcg_gen_helper_0_2i(fcmp ## type ## _ ## fmt ## _table[n], a, b, cc); \ |
|
| 667 |
switch (n) { \
|
|
| 668 |
case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, a, b, cc); break;\ |
|
| 669 |
case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, a, b, cc); break;\ |
|
| 670 |
case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, a, b, cc); break;\ |
|
| 671 |
case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, a, b, cc); break;\ |
|
| 672 |
case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, a, b, cc); break;\ |
|
| 673 |
case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, a, b, cc); break;\ |
|
| 674 |
case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, a, b, cc); break;\ |
|
| 675 |
case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, a, b, cc); break;\ |
|
| 676 |
case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, a, b, cc); break;\ |
|
| 677 |
case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, a, b, cc); break;\ |
|
| 678 |
case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, a, b, cc); break;\ |
|
| 679 |
case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, a, b, cc); break;\ |
|
| 680 |
case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, a, b, cc); break;\ |
|
| 681 |
case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, a, b, cc); break;\ |
|
| 682 |
case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, a, b, cc); break;\ |
|
| 683 |
case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, a, b, cc); break;\ |
|
| 684 |
default: abort(); \ |
|
| 685 |
} \ |
|
| 740 | 686 |
} |
| 741 | 687 |
|
| 742 |
FOP_CONDS(fcmp_fun64, , d)
|
|
| 743 |
FOP_CONDS(fcmp_fun64, abs, d)
|
|
| 744 |
FOP_CONDS(fcmp_fun32, , s)
|
|
| 745 |
FOP_CONDS(fcmp_fun32, abs, s)
|
|
| 746 |
FOP_CONDS(fcmp_fun64, , ps)
|
|
| 747 |
FOP_CONDS(fcmp_fun64, abs, ps)
|
|
| 688 |
FOP_CONDS(, d, 64)
|
|
| 689 |
FOP_CONDS(abs, d, 64)
|
|
| 690 |
FOP_CONDS(, s, 32)
|
|
| 691 |
FOP_CONDS(abs, s, 32)
|
|
| 692 |
FOP_CONDS(, ps, 64)
|
|
| 693 |
FOP_CONDS(abs, ps, 64)
|
|
| 748 | 694 |
#undef FOP_CONDS |
| 749 | 695 |
|
| 750 | 696 |
/* Tests */ |
| ... | ... | |
| 823 | 769 |
ctx->saved_pc = ctx->pc; |
| 824 | 770 |
} |
| 825 | 771 |
if (ctx->hflags != ctx->saved_hflags) {
|
| 826 |
TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 772 |
TCGv_i32 r_tmp = tcg_temp_new_i32();
|
|
| 827 | 773 |
|
| 828 | 774 |
tcg_gen_movi_i32(r_tmp, ctx->hflags); |
| 829 | 775 |
tcg_gen_st_i32(r_tmp, cpu_env, offsetof(CPUState, hflags)); |
| 830 |
tcg_temp_free(r_tmp); |
|
| 776 |
tcg_temp_free_i32(r_tmp);
|
|
| 831 | 777 |
ctx->saved_hflags = ctx->hflags; |
| 832 | 778 |
switch (ctx->hflags & MIPS_HFLAG_BMASK) {
|
| 833 | 779 |
case MIPS_HFLAG_BR: |
| ... | ... | |
| 858 | 804 |
static inline void |
| 859 | 805 |
generate_exception_err (DisasContext *ctx, int excp, int err) |
| 860 | 806 |
{
|
| 807 |
TCGv_i32 texcp = tcg_const_i32(excp); |
|
| 808 |
TCGv_i32 terr = tcg_const_i32(err); |
|
| 861 | 809 |
save_cpu_state(ctx, 1); |
| 862 |
tcg_gen_helper_0_ii(do_raise_exception_err, excp, err); |
|
| 863 |
tcg_gen_helper_0_0(do_interrupt_restart); |
|
| 810 |
gen_helper_raise_exception_err(texcp, terr); |
|
| 811 |
tcg_temp_free_i32(terr); |
|
| 812 |
tcg_temp_free_i32(texcp); |
|
| 813 |
gen_helper_interrupt_restart(); |
|
| 864 | 814 |
tcg_gen_exit_tb(0); |
| 865 | 815 |
} |
| 866 | 816 |
|
| ... | ... | |
| 868 | 818 |
generate_exception (DisasContext *ctx, int excp) |
| 869 | 819 |
{
|
| 870 | 820 |
save_cpu_state(ctx, 1); |
| 871 |
tcg_gen_helper_0_i(do_raise_exception, excp);
|
|
| 872 |
tcg_gen_helper_0_0(do_interrupt_restart);
|
|
| 821 |
gen_helper_0i(raise_exception, excp);
|
|
| 822 |
gen_helper_interrupt_restart();
|
|
| 873 | 823 |
tcg_gen_exit_tb(0); |
| 874 | 824 |
} |
| 875 | 825 |
|
| ... | ... | |
| 999 | 949 |
#define OP_ST_ATOMIC(insn,fname,almask) \ |
| 1000 | 950 |
static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \ |
| 1001 | 951 |
{ \
|
| 1002 |
TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL); \
|
|
| 952 |
TCGv r_tmp = tcg_temp_local_new(); \ |
|
| 1003 | 953 |
int l1 = gen_new_label(); \ |
| 1004 | 954 |
int l2 = gen_new_label(); \ |
| 1005 | 955 |
int l3 = gen_new_label(); \ |
| ... | ... | |
| 1030 | 980 |
int base, int16_t offset) |
| 1031 | 981 |
{
|
| 1032 | 982 |
const char *opn = "ldst"; |
| 1033 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 1034 |
TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 983 |
TCGv t0 = tcg_temp_local_new(); |
|
| 984 |
TCGv t1 = tcg_temp_local_new(); |
|
| 1035 | 985 |
|
| 1036 | 986 |
if (base == 0) {
|
| 1037 | 987 |
tcg_gen_movi_tl(t0, offset); |
| ... | ... | |
| 1076 | 1026 |
case OPC_LDL: |
| 1077 | 1027 |
save_cpu_state(ctx, 1); |
| 1078 | 1028 |
gen_load_gpr(t1, rt); |
| 1079 |
tcg_gen_helper_1_2i(do_ldl, t1, t0, t1, ctx->mem_idx);
|
|
| 1029 |
gen_helper_3i(ldl, t1, t0, t1, ctx->mem_idx);
|
|
| 1080 | 1030 |
gen_store_gpr(t1, rt); |
| 1081 | 1031 |
opn = "ldl"; |
| 1082 | 1032 |
break; |
| 1083 | 1033 |
case OPC_SDL: |
| 1084 | 1034 |
save_cpu_state(ctx, 1); |
| 1085 | 1035 |
gen_load_gpr(t1, rt); |
| 1086 |
tcg_gen_helper_0_2i(do_sdl, t0, t1, ctx->mem_idx);
|
|
| 1036 |
gen_helper_2i(sdl, t0, t1, ctx->mem_idx);
|
|
| 1087 | 1037 |
opn = "sdl"; |
| 1088 | 1038 |
break; |
| 1089 | 1039 |
case OPC_LDR: |
| 1090 | 1040 |
save_cpu_state(ctx, 1); |
| 1091 | 1041 |
gen_load_gpr(t1, rt); |
| 1092 |
tcg_gen_helper_1_2i(do_ldr, t1, t0, t1, ctx->mem_idx);
|
|
| 1042 |
gen_helper_3i(ldr, t1, t0, t1, ctx->mem_idx);
|
|
| 1093 | 1043 |
gen_store_gpr(t1, rt); |
| 1094 | 1044 |
opn = "ldr"; |
| 1095 | 1045 |
break; |
| 1096 | 1046 |
case OPC_SDR: |
| 1097 | 1047 |
save_cpu_state(ctx, 1); |
| 1098 | 1048 |
gen_load_gpr(t1, rt); |
| 1099 |
tcg_gen_helper_0_2i(do_sdr, t0, t1, ctx->mem_idx);
|
|
| 1049 |
gen_helper_2i(sdr, t0, t1, ctx->mem_idx);
|
|
| 1100 | 1050 |
opn = "sdr"; |
| 1101 | 1051 |
break; |
| 1102 | 1052 |
#endif |
| ... | ... | |
| 1143 | 1093 |
case OPC_LWL: |
| 1144 | 1094 |
save_cpu_state(ctx, 1); |
| 1145 | 1095 |
gen_load_gpr(t1, rt); |
| 1146 |
tcg_gen_helper_1_2i(do_lwl, t1, t0, t1, ctx->mem_idx);
|
|
| 1096 |
gen_helper_3i(lwl, t1, t0, t1, ctx->mem_idx);
|
|
| 1147 | 1097 |
gen_store_gpr(t1, rt); |
| 1148 | 1098 |
opn = "lwl"; |
| 1149 | 1099 |
break; |
| 1150 | 1100 |
case OPC_SWL: |
| 1151 | 1101 |
save_cpu_state(ctx, 1); |
| 1152 | 1102 |
gen_load_gpr(t1, rt); |
| 1153 |
tcg_gen_helper_0_2i(do_swl, t0, t1, ctx->mem_idx);
|
|
| 1103 |
gen_helper_2i(swl, t0, t1, ctx->mem_idx);
|
|
| 1154 | 1104 |
opn = "swr"; |
| 1155 | 1105 |
break; |
| 1156 | 1106 |
case OPC_LWR: |
| 1157 | 1107 |
save_cpu_state(ctx, 1); |
| 1158 | 1108 |
gen_load_gpr(t1, rt); |
| 1159 |
tcg_gen_helper_1_2i(do_lwr, t1, t0, t1, ctx->mem_idx);
|
|
| 1109 |
gen_helper_3i(lwr, t1, t0, t1, ctx->mem_idx);
|
|
| 1160 | 1110 |
gen_store_gpr(t1, rt); |
| 1161 | 1111 |
opn = "lwr"; |
| 1162 | 1112 |
break; |
| 1163 | 1113 |
case OPC_SWR: |
| 1164 | 1114 |
save_cpu_state(ctx, 1); |
| 1165 | 1115 |
gen_load_gpr(t1, rt); |
| 1166 |
tcg_gen_helper_0_2i(do_swr, t0, t1, ctx->mem_idx);
|
|
| 1116 |
gen_helper_2i(swr, t0, t1, ctx->mem_idx);
|
|
| 1167 | 1117 |
opn = "swr"; |
| 1168 | 1118 |
break; |
| 1169 | 1119 |
case OPC_LL: |
| ... | ... | |
| 1194 | 1144 |
int base, int16_t offset) |
| 1195 | 1145 |
{
|
| 1196 | 1146 |
const char *opn = "flt_ldst"; |
| 1197 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 1147 |
TCGv t0 = tcg_temp_local_new(); |
|
| 1198 | 1148 |
|
| 1199 | 1149 |
if (base == 0) {
|
| 1200 | 1150 |
tcg_gen_movi_tl(t0, offset); |
| 1201 | 1151 |
} else if (offset == 0) {
|
| 1202 | 1152 |
gen_load_gpr(t0, base); |
| 1203 | 1153 |
} else {
|
| 1204 |
TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 1154 |
TCGv t1 = tcg_temp_local_new(); |
|
| 1205 | 1155 |
|
| 1206 | 1156 |
gen_load_gpr(t0, base); |
| 1207 | 1157 |
tcg_gen_movi_tl(t1, offset); |
| ... | ... | |
| 1213 | 1163 |
switch (opc) {
|
| 1214 | 1164 |
case OPC_LWC1: |
| 1215 | 1165 |
{
|
| 1216 |
TCGv fp0 = tcg_temp_new(TCG_TYPE_I32); |
|
| 1166 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
|
| 1167 |
TCGv t1 = tcg_temp_new(); |
|
| 1217 | 1168 |
|
| 1218 |
tcg_gen_qemu_ld32s(fp0, t0, ctx->mem_idx); |
|
| 1169 |
tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx); |
|
| 1170 |
tcg_gen_trunc_tl_i32(fp0, t1); |
|
| 1219 | 1171 |
gen_store_fpr32(fp0, ft); |
| 1220 |
tcg_temp_free(fp0); |
|
| 1172 |
tcg_temp_free(t1); |
|
| 1173 |
tcg_temp_free_i32(fp0); |
|
| 1221 | 1174 |
} |
| 1222 | 1175 |
opn = "lwc1"; |
| 1223 | 1176 |
break; |
| 1224 | 1177 |
case OPC_SWC1: |
| 1225 | 1178 |
{
|
| 1226 |
TCGv fp0 = tcg_temp_new(TCG_TYPE_I32); |
|
| 1179 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
|
| 1180 |
TCGv t1 = tcg_temp_new(); |
|
| 1227 | 1181 |
|
| 1228 | 1182 |
gen_load_fpr32(fp0, ft); |
| 1229 |
tcg_gen_qemu_st32(fp0, t0, ctx->mem_idx); |
|
| 1230 |
tcg_temp_free(fp0); |
|
| 1183 |
tcg_gen_extu_i32_tl(t1, fp0); |
|
| 1184 |
tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); |
|
| 1185 |
tcg_temp_free(t1); |
|
| 1186 |
tcg_temp_free_i32(fp0); |
|
| 1231 | 1187 |
} |
| 1232 | 1188 |
opn = "swc1"; |
| 1233 | 1189 |
break; |
| 1234 | 1190 |
case OPC_LDC1: |
| 1235 | 1191 |
{
|
| 1236 |
TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1192 |
TCGv_i64 fp0 = tcg_temp_new_i64();
|
|
| 1237 | 1193 |
|
| 1238 | 1194 |
tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx); |
| 1239 | 1195 |
gen_store_fpr64(ctx, fp0, ft); |
| 1240 |
tcg_temp_free(fp0); |
|
| 1196 |
tcg_temp_free_i64(fp0);
|
|
| 1241 | 1197 |
} |
| 1242 | 1198 |
opn = "ldc1"; |
| 1243 | 1199 |
break; |
| 1244 | 1200 |
case OPC_SDC1: |
| 1245 | 1201 |
{
|
| 1246 |
TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1202 |
TCGv_i64 fp0 = tcg_temp_new_i64();
|
|
| 1247 | 1203 |
|
| 1248 | 1204 |
gen_load_fpr64(ctx, fp0, ft); |
| 1249 | 1205 |
tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx); |
| 1250 |
tcg_temp_free(fp0); |
|
| 1206 |
tcg_temp_free_i64(fp0);
|
|
| 1251 | 1207 |
} |
| 1252 | 1208 |
opn = "sdc1"; |
| 1253 | 1209 |
break; |
| ... | ... | |
| 1267 | 1223 |
{
|
| 1268 | 1224 |
target_ulong uimm; |
| 1269 | 1225 |
const char *opn = "imm arith"; |
| 1270 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 1226 |
TCGv t0 = tcg_temp_local_new(); |
|
| 1271 | 1227 |
|
| 1272 | 1228 |
if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
|
| 1273 | 1229 |
/* If no destination, treat it as a NOP. |
| ... | ... | |
| 1313 | 1269 |
switch (opc) {
|
| 1314 | 1270 |
case OPC_ADDI: |
| 1315 | 1271 |
{
|
| 1316 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 1317 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 1272 |
TCGv r_tmp1 = tcg_temp_new(); |
|
| 1273 |
TCGv r_tmp2 = tcg_temp_new(); |
|
| 1318 | 1274 |
int l1 = gen_new_label(); |
| 1319 | 1275 |
|
| 1320 | 1276 |
save_cpu_state(ctx, 1); |
| ... | ... | |
| 1343 | 1299 |
#if defined(TARGET_MIPS64) |
| 1344 | 1300 |
case OPC_DADDI: |
| 1345 | 1301 |
{
|
| 1346 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 1347 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 1302 |
TCGv r_tmp1 = tcg_temp_new(); |
|
| 1303 |
TCGv r_tmp2 = tcg_temp_new(); |
|
| 1348 | 1304 |
int l1 = gen_new_label(); |
| 1349 | 1305 |
|
| 1350 | 1306 |
save_cpu_state(ctx, 1); |
| ... | ... | |
| 1416 | 1372 |
/* rotr is decoded as srl on non-R2 CPUs */ |
| 1417 | 1373 |
if (env->insn_flags & ISA_MIPS32R2) {
|
| 1418 | 1374 |
if (uimm != 0) {
|
| 1419 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1375 |
TCGv_i32 r_tmp1 = tcg_temp_new_i32();
|
|
| 1420 | 1376 |
|
| 1421 | 1377 |
tcg_gen_trunc_tl_i32(r_tmp1, t0); |
| 1422 | 1378 |
tcg_gen_rotri_i32(r_tmp1, r_tmp1, uimm); |
| 1423 | 1379 |
tcg_gen_ext_i32_tl(t0, r_tmp1); |
| 1424 |
tcg_temp_free(r_tmp1); |
|
| 1380 |
tcg_temp_free_i32(r_tmp1);
|
|
| 1425 | 1381 |
} |
| 1426 | 1382 |
opn = "rotr"; |
| 1427 | 1383 |
} else {
|
| ... | ... | |
| 1520 | 1476 |
int rd, int rs, int rt) |
| 1521 | 1477 |
{
|
| 1522 | 1478 |
const char *opn = "arith"; |
| 1523 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 1524 |
TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 1479 |
TCGv t0 = tcg_temp_local_new(); |
|
| 1480 |
TCGv t1 = tcg_temp_local_new(); |
|
| 1525 | 1481 |
|
| 1526 | 1482 |
if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB |
| 1527 | 1483 |
&& opc != OPC_DADD && opc != OPC_DSUB) {
|
| ... | ... | |
| 1541 | 1497 |
switch (opc) {
|
| 1542 | 1498 |
case OPC_ADD: |
| 1543 | 1499 |
{
|
| 1544 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 1545 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 1500 |
TCGv r_tmp1 = tcg_temp_new(); |
|
| 1501 |
TCGv r_tmp2 = tcg_temp_new(); |
|
| 1546 | 1502 |
int l1 = gen_new_label(); |
| 1547 | 1503 |
|
| 1548 | 1504 |
save_cpu_state(ctx, 1); |
| ... | ... | |
| 1572 | 1528 |
break; |
| 1573 | 1529 |
case OPC_SUB: |
| 1574 | 1530 |
{
|
| 1575 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 1576 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 1531 |
TCGv r_tmp1 = tcg_temp_new(); |
|
| 1532 |
TCGv r_tmp2 = tcg_temp_new(); |
|
| 1577 | 1533 |
int l1 = gen_new_label(); |
| 1578 | 1534 |
|
| 1579 | 1535 |
save_cpu_state(ctx, 1); |
| ... | ... | |
| 1603 | 1559 |
#if defined(TARGET_MIPS64) |
| 1604 | 1560 |
case OPC_DADD: |
| 1605 | 1561 |
{
|
| 1606 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 1607 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 1562 |
TCGv r_tmp1 = tcg_temp_new(); |
|
| 1563 |
TCGv r_tmp2 = tcg_temp_new(); |
|
| 1608 | 1564 |
int l1 = gen_new_label(); |
| 1609 | 1565 |
|
| 1610 | 1566 |
save_cpu_state(ctx, 1); |
| ... | ... | |
| 1630 | 1586 |
break; |
| 1631 | 1587 |
case OPC_DSUB: |
| 1632 | 1588 |
{
|
| 1633 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 1634 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 1589 |
TCGv r_tmp1 = tcg_temp_new(); |
|
| 1590 |
TCGv r_tmp2 = tcg_temp_new(); |
|
| 1635 | 1591 |
int l1 = gen_new_label(); |
| 1636 | 1592 |
|
| 1637 | 1593 |
save_cpu_state(ctx, 1); |
| ... | ... | |
| 1735 | 1691 |
tcg_gen_andi_tl(t0, t0, 0x1f); |
| 1736 | 1692 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); |
| 1737 | 1693 |
{
|
| 1738 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1739 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1694 |
TCGv_i32 r_tmp1 = tcg_temp_new_i32();
|
|
| 1695 |
TCGv_i32 r_tmp2 = tcg_temp_new_i32();
|
|
| 1740 | 1696 |
|
| 1741 | 1697 |
tcg_gen_trunc_tl_i32(r_tmp1, t0); |
| 1742 | 1698 |
tcg_gen_trunc_tl_i32(r_tmp2, t1); |
| 1743 | 1699 |
tcg_gen_rotr_i32(r_tmp1, r_tmp1, r_tmp2); |
| 1744 |
tcg_temp_free(r_tmp1); |
|
| 1745 |
tcg_temp_free(r_tmp2); |
|
| 1700 |
tcg_temp_free_i32(r_tmp1);
|
|
| 1701 |
tcg_temp_free_i32(r_tmp2);
|
|
| 1746 | 1702 |
tcg_gen_br(l2); |
| 1747 | 1703 |
} |
| 1748 | 1704 |
gen_set_label(l1); |
| ... | ... | |
| 1827 | 1783 |
static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg) |
| 1828 | 1784 |
{
|
| 1829 | 1785 |
const char *opn = "hilo"; |
| 1830 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 1786 |
TCGv t0 = tcg_temp_local_new(); |
|
| 1831 | 1787 |
|
| 1832 | 1788 |
if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
|
| 1833 | 1789 |
/* Treat as NOP. */ |
| ... | ... | |
| 1869 | 1825 |
int rs, int rt) |
| 1870 | 1826 |
{
|
| 1871 | 1827 |
const char *opn = "mul/div"; |
| 1872 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 1873 |
TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 1828 |
TCGv t0 = tcg_temp_local_new(); |
|
| 1829 |
TCGv t1 = tcg_temp_local_new(); |
|
| 1874 | 1830 |
|
| 1875 | 1831 |
gen_load_gpr(t0, rs); |
| 1876 | 1832 |
gen_load_gpr(t1, rt); |
| ... | ... | |
| 1882 | 1838 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
| 1883 | 1839 |
{
|
| 1884 | 1840 |
int l2 = gen_new_label(); |
| 1885 |
TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_I32);
|
|
| 1886 |
TCGv r_tmp2 = tcg_temp_local_new(TCG_TYPE_I32);
|
|
| 1887 |
TCGv r_tmp3 = tcg_temp_local_new(TCG_TYPE_I32);
|
|
| 1841 |
TCGv_i32 r_tmp1 = tcg_temp_local_new_i32();
|
|
| 1842 |
TCGv_i32 r_tmp2 = tcg_temp_local_new_i32();
|
|
| 1843 |
TCGv_i32 r_tmp3 = tcg_temp_local_new_i32();
|
|
| 1888 | 1844 |
|
| 1889 | 1845 |
tcg_gen_trunc_tl_i32(r_tmp1, t0); |
| 1890 | 1846 |
tcg_gen_trunc_tl_i32(r_tmp2, t1); |
| ... | ... | |
| 1898 | 1854 |
tcg_gen_rem_i32(r_tmp2, r_tmp1, r_tmp2); |
| 1899 | 1855 |
tcg_gen_ext_i32_tl(cpu_LO[0], r_tmp3); |
| 1900 | 1856 |
tcg_gen_ext_i32_tl(cpu_HI[0], r_tmp2); |
| 1901 |
tcg_temp_free(r_tmp1); |
|
| 1902 |
tcg_temp_free(r_tmp2); |
|
| 1903 |
tcg_temp_free(r_tmp3); |
|
| 1857 |
tcg_temp_free_i32(r_tmp1);
|
|
| 1858 |
tcg_temp_free_i32(r_tmp2);
|
|
| 1859 |
tcg_temp_free_i32(r_tmp3);
|
|
| 1904 | 1860 |
} |
| 1905 | 1861 |
gen_set_label(l1); |
| 1906 | 1862 |
} |
| ... | ... | |
| 1913 | 1869 |
tcg_gen_ext32s_tl(t1, t1); |
| 1914 | 1870 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
| 1915 | 1871 |
{
|
| 1916 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1917 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1918 |
TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1872 |
TCGv_i32 r_tmp1 = tcg_temp_new_i32();
|
|
| 1873 |
TCGv_i32 r_tmp2 = tcg_temp_new_i32();
|
|
| 1874 |
TCGv_i32 r_tmp3 = tcg_temp_new_i32();
|
|
| 1919 | 1875 |
|
| 1920 | 1876 |
tcg_gen_trunc_tl_i32(r_tmp1, t0); |
| 1921 | 1877 |
tcg_gen_trunc_tl_i32(r_tmp2, t1); |
| ... | ... | |
| 1923 | 1879 |
tcg_gen_remu_i32(r_tmp1, r_tmp1, r_tmp2); |
| 1924 | 1880 |
tcg_gen_ext_i32_tl(cpu_LO[0], r_tmp3); |
| 1925 | 1881 |
tcg_gen_ext_i32_tl(cpu_HI[0], r_tmp1); |
| 1926 |
tcg_temp_free(r_tmp1); |
|
| 1927 |
tcg_temp_free(r_tmp2); |
|
| 1928 |
tcg_temp_free(r_tmp3); |
|
| 1882 |
tcg_temp_free_i32(r_tmp1);
|
|
| 1883 |
tcg_temp_free_i32(r_tmp2);
|
|
| 1884 |
tcg_temp_free_i32(r_tmp3);
|
|
| 1929 | 1885 |
} |
| 1930 | 1886 |
gen_set_label(l1); |
| 1931 | 1887 |
} |
| ... | ... | |
| 1933 | 1889 |
break; |
| 1934 | 1890 |
case OPC_MULT: |
| 1935 | 1891 |
{
|
| 1936 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1937 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1892 |
TCGv_i64 r_tmp1 = tcg_temp_new_i64();
|
|
| 1893 |
TCGv_i64 r_tmp2 = tcg_temp_new_i64();
|
|
| 1938 | 1894 |
|
| 1939 | 1895 |
tcg_gen_ext_tl_i64(r_tmp1, t0); |
| 1940 | 1896 |
tcg_gen_ext_tl_i64(r_tmp2, t1); |
| 1941 | 1897 |
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2); |
| 1942 |
tcg_temp_free(r_tmp2); |
|
| 1898 |
tcg_temp_free_i64(r_tmp2);
|
|
| 1943 | 1899 |
tcg_gen_trunc_i64_tl(t0, r_tmp1); |
| 1944 | 1900 |
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32); |
| 1945 | 1901 |
tcg_gen_trunc_i64_tl(t1, r_tmp1); |
| 1946 |
tcg_temp_free(r_tmp1); |
|
| 1902 |
tcg_temp_free_i64(r_tmp1);
|
|
| 1947 | 1903 |
tcg_gen_ext32s_tl(cpu_LO[0], t0); |
| 1948 | 1904 |
tcg_gen_ext32s_tl(cpu_HI[0], t1); |
| 1949 | 1905 |
} |
| ... | ... | |
| 1951 | 1907 |
break; |
| 1952 | 1908 |
case OPC_MULTU: |
| 1953 | 1909 |
{
|
| 1954 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1955 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1910 |
TCGv_i64 r_tmp1 = tcg_temp_new_i64();
|
|
| 1911 |
TCGv_i64 r_tmp2 = tcg_temp_new_i64();
|
|
| 1956 | 1912 |
|
| 1957 | 1913 |
tcg_gen_ext32u_tl(t0, t0); |
| 1958 | 1914 |
tcg_gen_ext32u_tl(t1, t1); |
| 1959 | 1915 |
tcg_gen_extu_tl_i64(r_tmp1, t0); |
| 1960 | 1916 |
tcg_gen_extu_tl_i64(r_tmp2, t1); |
| 1961 | 1917 |
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2); |
| 1962 |
tcg_temp_free(r_tmp2); |
|
| 1918 |
tcg_temp_free_i64(r_tmp2);
|
|
| 1963 | 1919 |
tcg_gen_trunc_i64_tl(t0, r_tmp1); |
| 1964 | 1920 |
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32); |
| 1965 | 1921 |
tcg_gen_trunc_i64_tl(t1, r_tmp1); |
| 1966 |
tcg_temp_free(r_tmp1); |
|
| 1922 |
tcg_temp_free_i64(r_tmp1);
|
|
| 1967 | 1923 |
tcg_gen_ext32s_tl(cpu_LO[0], t0); |
| 1968 | 1924 |
tcg_gen_ext32s_tl(cpu_HI[0], t1); |
| 1969 | 1925 |
} |
| ... | ... | |
| 2003 | 1959 |
opn = "ddivu"; |
| 2004 | 1960 |
break; |
| 2005 | 1961 |
case OPC_DMULT: |
| 2006 |
tcg_gen_helper_0_2(do_dmult, t0, t1);
|
|
| 1962 |
gen_helper_dmult(t0, t1);
|
|
| 2007 | 1963 |
opn = "dmult"; |
| 2008 | 1964 |
break; |
| 2009 | 1965 |
case OPC_DMULTU: |
| 2010 |
tcg_gen_helper_0_2(do_dmultu, t0, t1);
|
|
| 1966 |
gen_helper_dmultu(t0, t1);
|
|
| 2011 | 1967 |
opn = "dmultu"; |
| 2012 | 1968 |
break; |
| 2013 | 1969 |
#endif |
| 2014 | 1970 |
case OPC_MADD: |
| 2015 | 1971 |
{
|
| 2016 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 2017 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1972 |
TCGv_i64 r_tmp1 = tcg_temp_new_i64();
|
|
| 1973 |
TCGv_i64 r_tmp2 = tcg_temp_new_i64();
|
|
| 2018 | 1974 |
|
| 2019 | 1975 |
tcg_gen_ext_tl_i64(r_tmp1, t0); |
| 2020 | 1976 |
tcg_gen_ext_tl_i64(r_tmp2, t1); |
| 2021 | 1977 |
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2022 | 1978 |
tcg_gen_concat_tl_i64(r_tmp2, cpu_LO[0], cpu_HI[0]); |
| 2023 | 1979 |
tcg_gen_add_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2024 |
tcg_temp_free(r_tmp2); |
|
| 1980 |
tcg_temp_free_i64(r_tmp2);
|
|
| 2025 | 1981 |
tcg_gen_trunc_i64_tl(t0, r_tmp1); |
| 2026 | 1982 |
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32); |
| 2027 | 1983 |
tcg_gen_trunc_i64_tl(t1, r_tmp1); |
| 2028 |
tcg_temp_free(r_tmp1); |
|
| 1984 |
tcg_temp_free_i64(r_tmp1);
|
|
| 2029 | 1985 |
tcg_gen_ext32s_tl(cpu_LO[0], t0); |
| 2030 | 1986 |
tcg_gen_ext32s_tl(cpu_LO[1], t1); |
| 2031 | 1987 |
} |
| ... | ... | |
| 2033 | 1989 |
break; |
| 2034 | 1990 |
case OPC_MADDU: |
| 2035 | 1991 |
{
|
| 2036 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 2037 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1992 |
TCGv_i64 r_tmp1 = tcg_temp_new_i64();
|
|
| 1993 |
TCGv_i64 r_tmp2 = tcg_temp_new_i64();
|
|
| 2038 | 1994 |
|
| 2039 | 1995 |
tcg_gen_ext32u_tl(t0, t0); |
| 2040 | 1996 |
tcg_gen_ext32u_tl(t1, t1); |
| ... | ... | |
| 2043 | 1999 |
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2044 | 2000 |
tcg_gen_concat_tl_i64(r_tmp2, cpu_LO[0], cpu_HI[0]); |
| 2045 | 2001 |
tcg_gen_add_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2046 |
tcg_temp_free(r_tmp2); |
|
| 2002 |
tcg_temp_free_i64(r_tmp2);
|
|
| 2047 | 2003 |
tcg_gen_trunc_i64_tl(t0, r_tmp1); |
| 2048 | 2004 |
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32); |
| 2049 | 2005 |
tcg_gen_trunc_i64_tl(t1, r_tmp1); |
| 2050 |
tcg_temp_free(r_tmp1); |
|
| 2006 |
tcg_temp_free_i64(r_tmp1);
|
|
| 2051 | 2007 |
tcg_gen_ext32s_tl(cpu_LO[0], t0); |
| 2052 | 2008 |
tcg_gen_ext32s_tl(cpu_HI[0], t1); |
| 2053 | 2009 |
} |
| ... | ... | |
| 2055 | 2011 |
break; |
| 2056 | 2012 |
case OPC_MSUB: |
| 2057 | 2013 |
{
|
| 2058 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 2059 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 2014 |
TCGv_i64 r_tmp1 = tcg_temp_new_i64();
|
|
| 2015 |
TCGv_i64 r_tmp2 = tcg_temp_new_i64();
|
|
| 2060 | 2016 |
|
| 2061 | 2017 |
tcg_gen_ext_tl_i64(r_tmp1, t0); |
| 2062 | 2018 |
tcg_gen_ext_tl_i64(r_tmp2, t1); |
| 2063 | 2019 |
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2064 | 2020 |
tcg_gen_concat_tl_i64(r_tmp2, cpu_LO[0], cpu_HI[0]); |
| 2065 | 2021 |
tcg_gen_sub_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2066 |
tcg_temp_free(r_tmp2); |
|
| 2022 |
tcg_temp_free_i64(r_tmp2);
|
|
| 2067 | 2023 |
tcg_gen_trunc_i64_tl(t0, r_tmp1); |
| 2068 | 2024 |
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32); |
| 2069 | 2025 |
tcg_gen_trunc_i64_tl(t1, r_tmp1); |
| 2070 |
tcg_temp_free(r_tmp1); |
|
| 2026 |
tcg_temp_free_i64(r_tmp1);
|
|
| 2071 | 2027 |
tcg_gen_ext32s_tl(cpu_LO[0], t0); |
| 2072 | 2028 |
tcg_gen_ext32s_tl(cpu_HI[0], t1); |
| 2073 | 2029 |
} |
| ... | ... | |
| 2075 | 2031 |
break; |
| 2076 | 2032 |
case OPC_MSUBU: |
| 2077 | 2033 |
{
|
| 2078 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 2079 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 2034 |
TCGv_i64 r_tmp1 = tcg_temp_new_i64();
|
|
| 2035 |
TCGv_i64 r_tmp2 = tcg_temp_new_i64();
|
|
| 2080 | 2036 |
|
| 2081 | 2037 |
tcg_gen_ext32u_tl(t0, t0); |
| 2082 | 2038 |
tcg_gen_ext32u_tl(t1, t1); |
| ... | ... | |
| 2085 | 2041 |
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2086 | 2042 |
tcg_gen_concat_tl_i64(r_tmp2, cpu_LO[0], cpu_HI[0]); |
| 2087 | 2043 |
tcg_gen_sub_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2088 |
tcg_temp_free(r_tmp2); |
|
| 2044 |
tcg_temp_free_i64(r_tmp2);
|
|
| 2089 | 2045 |
tcg_gen_trunc_i64_tl(t0, r_tmp1); |
| 2090 | 2046 |
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32); |
| 2091 | 2047 |
tcg_gen_trunc_i64_tl(t1, r_tmp1); |
| 2092 |
tcg_temp_free(r_tmp1); |
|
| 2048 |
tcg_temp_free_i64(r_tmp1);
|
|
| 2093 | 2049 |
tcg_gen_ext32s_tl(cpu_LO[0], t0); |
| 2094 | 2050 |
tcg_gen_ext32s_tl(cpu_HI[0], t1); |
| 2095 | 2051 |
} |
| ... | ... | |
| 2110 | 2066 |
int rd, int rs, int rt) |
| 2111 | 2067 |
{
|
| 2112 | 2068 |
const char *opn = "mul vr54xx"; |
| 2113 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 2114 |
TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 2069 |
TCGv t0 = tcg_temp_local_new(); |
|
| 2070 |
TCGv t1 = tcg_temp_local_new(); |
|
| 2115 | 2071 |
|
| 2116 | 2072 |
gen_load_gpr(t0, rs); |
| 2117 | 2073 |
gen_load_gpr(t1, rt); |
| 2118 | 2074 |
|
| 2119 | 2075 |
switch (opc) {
|
| 2120 | 2076 |
case OPC_VR54XX_MULS: |
| 2121 |
tcg_gen_helper_1_2(do_muls, t0, t0, t1);
|
|
| 2077 |
gen_helper_muls(t0, t0, t1);
|
|
| 2122 | 2078 |
opn = "muls"; |
| 2123 | 2079 |
break; |
| 2124 | 2080 |
case OPC_VR54XX_MULSU: |
| 2125 |
tcg_gen_helper_1_2(do_mulsu, t0, t0, t1);
|
|
| 2081 |
gen_helper_mulsu(t0, t0, t1);
|
|
| 2126 | 2082 |
opn = "mulsu"; |
| 2127 | 2083 |
break; |
| 2128 | 2084 |
case OPC_VR54XX_MACC: |
| 2129 |
tcg_gen_helper_1_2(do_macc, t0, t0, t1);
|
|
| 2085 |
gen_helper_macc(t0, t0, t1);
|
|
| 2130 | 2086 |
opn = "macc"; |
| 2131 | 2087 |
break; |
| 2132 | 2088 |
case OPC_VR54XX_MACCU: |
| 2133 |
tcg_gen_helper_1_2(do_maccu, t0, t0, t1);
|
|
| 2089 |
gen_helper_maccu(t0, t0, t1);
|
|
| 2134 | 2090 |
opn = "maccu"; |
| 2135 | 2091 |
break; |
| 2136 | 2092 |
case OPC_VR54XX_MSAC: |
| 2137 |
tcg_gen_helper_1_2(do_msac, t0, t0, t1);
|
|
| 2093 |
gen_helper_msac(t0, t0, t1);
|
|
| 2138 | 2094 |
opn = "msac"; |
| 2139 | 2095 |
break; |
| 2140 | 2096 |
case OPC_VR54XX_MSACU: |
| 2141 |
tcg_gen_helper_1_2(do_msacu, t0, t0, t1);
|
|
| 2097 |
gen_helper_msacu(t0, t0, t1);
|
|
| 2142 | 2098 |
opn = "msacu"; |
| 2143 | 2099 |
break; |
| 2144 | 2100 |
case OPC_VR54XX_MULHI: |
| 2145 |
tcg_gen_helper_1_2(do_mulhi, t0, t0, t1);
|
|
| 2101 |
gen_helper_mulhi(t0, t0, t1);
|
|
| 2146 | 2102 |
opn = "mulhi"; |
| 2147 | 2103 |
break; |
| 2148 | 2104 |
case OPC_VR54XX_MULHIU: |
| 2149 |
tcg_gen_helper_1_2(do_mulhiu, t0, t0, t1);
|
|
| 2105 |
gen_helper_mulhiu(t0, t0, t1);
|
|
| 2150 | 2106 |
opn = "mulhiu"; |
| 2151 | 2107 |
break; |
| 2152 | 2108 |
case OPC_VR54XX_MULSHI: |
| 2153 |
tcg_gen_helper_1_2(do_mulshi, t0, t0, t1);
|
|
| 2109 |
gen_helper_mulshi(t0, t0, t1);
|
|
| 2154 | 2110 |
opn = "mulshi"; |
| 2155 | 2111 |
break; |
| 2156 | 2112 |
case OPC_VR54XX_MULSHIU: |
| 2157 |
tcg_gen_helper_1_2(do_mulshiu, t0, t0, t1);
|
|
| 2113 |
gen_helper_mulshiu(t0, t0, t1);
|
|
| 2158 | 2114 |
opn = "mulshiu"; |
| 2159 | 2115 |
break; |
| 2160 | 2116 |
case OPC_VR54XX_MACCHI: |
| 2161 |
tcg_gen_helper_1_2(do_macchi, t0, t0, t1);
|
|
| 2117 |
gen_helper_macchi(t0, t0, t1);
|
|
| 2162 | 2118 |
opn = "macchi"; |
| 2163 | 2119 |
break; |
| 2164 | 2120 |
case OPC_VR54XX_MACCHIU: |
| 2165 |
tcg_gen_helper_1_2(do_macchiu, t0, t0, t1);
|
|
| 2121 |
gen_helper_macchiu(t0, t0, t1);
|
|
| 2166 | 2122 |
opn = "macchiu"; |
| 2167 | 2123 |
break; |
| 2168 | 2124 |
case OPC_VR54XX_MSACHI: |
| 2169 |
tcg_gen_helper_1_2(do_msachi, t0, t0, t1);
|
|
| 2125 |
gen_helper_msachi(t0, t0, t1);
|
|
| 2170 | 2126 |
opn = "msachi"; |
| 2171 | 2127 |
break; |
| 2172 | 2128 |
case OPC_VR54XX_MSACHIU: |
| 2173 |
tcg_gen_helper_1_2(do_msachiu, t0, t0, t1);
|
|
| 2129 |
gen_helper_msachiu(t0, t0, t1);
|
|
| 2174 | 2130 |
opn = "msachiu"; |
| 2175 | 2131 |
break; |
| 2176 | 2132 |
default: |
| ... | ... | |
| 2190 | 2146 |
int rd, int rs) |
| 2191 | 2147 |
{
|
| 2192 | 2148 |
const char *opn = "CLx"; |
| 2193 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 2149 |
TCGv t0 = tcg_temp_local_new(); |
|
| 2194 | 2150 |
|
| 2195 | 2151 |
if (rd == 0) {
|
| 2196 | 2152 |
/* Treat as NOP. */ |
| ... | ... | |
| 2200 | 2156 |
gen_load_gpr(t0, rs); |
| 2201 | 2157 |
switch (opc) {
|
| 2202 | 2158 |
case OPC_CLO: |
| 2203 |
tcg_gen_helper_1_1(do_clo, t0, t0);
|
|
| 2159 |
gen_helper_clo(t0, t0);
|
|
| 2204 | 2160 |
opn = "clo"; |
| 2205 | 2161 |
break; |
| 2206 | 2162 |
case OPC_CLZ: |
| 2207 |
tcg_gen_helper_1_1(do_clz, t0, t0);
|
|
| 2163 |
gen_helper_clz(t0, t0);
|
|
| 2208 | 2164 |
opn = "clz"; |
| 2209 | 2165 |
break; |
| 2210 | 2166 |
#if defined(TARGET_MIPS64) |
| 2211 | 2167 |
case OPC_DCLO: |
| 2212 |
tcg_gen_helper_1_1(do_dclo, t0, t0);
|
|
| 2168 |
gen_helper_dclo(t0, t0);
|
|
| 2213 | 2169 |
opn = "dclo"; |
| 2214 | 2170 |
break; |
| 2215 | 2171 |
case OPC_DCLZ: |
| 2216 |
tcg_gen_helper_1_1(do_dclz, t0, t0);
|
|
| 2172 |
gen_helper_dclz(t0, t0);
|
|
| 2217 | 2173 |
opn = "dclz"; |
| 2218 | 2174 |
break; |
| 2219 | 2175 |
#endif |
| ... | ... | |
| 2234 | 2190 |
int rs, int rt, int16_t imm) |
| 2235 | 2191 |
{
|
| 2236 | 2192 |
int cond; |
| 2237 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 2238 |
TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 2193 |
TCGv t0 = tcg_temp_local_new(); |
|
| 2194 |
TCGv t1 = tcg_temp_local_new(); |
|
| 2239 | 2195 |
|
| 2240 | 2196 |
cond = 0; |
| 2241 | 2197 |
/* Load needed operands */ |
| ... | ... | |
| 2328 | 2284 |
int l1 = gen_new_label(); |
| 2329 | 2285 |
|
| 2330 | 2286 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); |
| 2331 |
tcg_gen_helper_0_i(do_raise_exception, EXCP_TRAP);
|
|
| 2287 |
gen_helper_0i(raise_exception, EXCP_TRAP);
|
|
| 2332 | 2288 |
gen_set_label(l1); |
| 2333 | 2289 |
} |
| 2334 | 2290 |
ctx->bstate = BS_STOP; |
| ... | ... | |
| 2358 | 2314 |
target_ulong btgt = -1; |
| 2359 | 2315 |
int blink = 0; |
| 2360 | 2316 |
int bcond_compute = 0; |
| 2361 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 2362 |
TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
|
|
| 2317 |
TCGv t0 = tcg_temp_local_new(); |
|
| 2318 |
TCGv t1 = tcg_temp_local_new(); |
|
| 2363 | 2319 |
|
| 2364 | 2320 |
if (ctx->hflags & MIPS_HFLAG_BMASK) {
|
| 2365 | 2321 |
#ifdef MIPS_DEBUG_DISAS |
| ... | ... | |
| 2600 | 2556 |
static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, |
| 2601 | 2557 |
int rs, int lsb, int msb) |
| 2602 | 2558 |
{
|
| 2603 |
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 2604 |
TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 2559 |
TCGv t0 = tcg_temp_new(); |
|
| 2560 |
TCGv t1 = tcg_temp_new(); |
|
| 2605 | 2561 |
target_ulong mask; |
| 2606 | 2562 |
|
| 2607 | 2563 |
gen_load_gpr(t1, rs); |
| ... | ... | |
| 2691 | 2647 |
|
| 2692 | 2648 |
static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) |
| 2693 | 2649 |
{
|
| 2694 |
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 2695 |
TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 2650 |
TCGv t0 = tcg_temp_new(); |
|
| 2651 |
TCGv t1 = tcg_temp_new(); |
|
| 2696 | 2652 |
|
| 2697 | 2653 |
gen_load_gpr(t1, rt); |
| 2698 | 2654 |
switch (op2) {
|
| ... | ... | |
| 2747 | 2703 |
/* CP0 (MMU and control) */ |
| 2748 | 2704 |
static inline void gen_mfc0_load32 (TCGv t, target_ulong off) |
| 2749 | 2705 |
{
|
| 2750 |
TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 2706 |
TCGv_i32 r_tmp = tcg_temp_new_i32();
|
|
| 2751 | 2707 |
|
| 2752 | 2708 |
tcg_gen_ld_i32(r_tmp, cpu_env, off); |
| 2753 | 2709 |
tcg_gen_ext_i32_tl(t, r_tmp); |
| 2754 |
tcg_temp_free(r_tmp); |
|
| 2710 |
tcg_temp_free_i32(r_tmp);
|
|
| 2755 | 2711 |
} |
| 2756 | 2712 |
|
| 2757 | 2713 |
static inline void gen_mfc0_load64 (TCGv t, target_ulong off) |
| ... | ... | |
| 2762 | 2718 |
|
| 2763 | 2719 |
static inline void gen_mtc0_store32 (TCGv t, target_ulong off) |
| 2764 | 2720 |
{
|
| 2765 |
TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 2721 |
TCGv_i32 r_tmp = tcg_temp_new_i32();
|
|
| 2766 | 2722 |
|
| 2767 | 2723 |
tcg_gen_trunc_tl_i32(r_tmp, t); |
| 2768 | 2724 |
tcg_gen_st_i32(r_tmp, cpu_env, off); |
| 2769 |
tcg_temp_free(r_tmp); |
|
| 2725 |
tcg_temp_free_i32(r_tmp);
|
|
| 2770 | 2726 |
} |
| 2771 | 2727 |
|
| 2772 | 2728 |
static inline void gen_mtc0_store64 (TCGv t, target_ulong off) |
| ... | ... | |
| 2791 | 2747 |
break; |
| 2792 | 2748 |
case 1: |
| 2793 | 2749 |
check_insn(env, ctx, ASE_MT); |
| 2794 |
tcg_gen_helper_1_0(do_mfc0_mvpcontrol, t0);
|
|
| 2750 |
gen_helper_mfc0_mvpcontrol(t0);
|
|
| 2795 | 2751 |
rn = "MVPControl"; |
| 2796 | 2752 |
break; |
| 2797 | 2753 |
case 2: |
| 2798 | 2754 |
check_insn(env, ctx, ASE_MT); |
| 2799 |
tcg_gen_helper_1_0(do_mfc0_mvpconf0, t0);
|
|
| 2755 |
gen_helper_mfc0_mvpconf0(t0);
|
|
| 2800 | 2756 |
rn = "MVPConf0"; |
| 2801 | 2757 |
break; |
| 2802 | 2758 |
case 3: |
| 2803 | 2759 |
check_insn(env, ctx, ASE_MT); |
| 2804 |
tcg_gen_helper_1_0(do_mfc0_mvpconf1, t0);
|
|
| 2760 |
gen_helper_mfc0_mvpconf1(t0);
|
|
| 2805 | 2761 |
rn = "MVPConf1"; |
| 2806 | 2762 |
break; |
| 2807 | 2763 |
default: |
| ... | ... | |
| 2811 | 2767 |
case 1: |
| 2812 | 2768 |
switch (sel) {
|
| 2813 | 2769 |
case 0: |
| 2814 |
tcg_gen_helper_1_0(do_mfc0_random, t0);
|
|
| 2770 |
gen_helper_mfc0_random(t0);
|
|
| 2815 | 2771 |
rn = "Random"; |
| 2816 | 2772 |
break; |
| 2817 | 2773 |
case 1: |
| ... | ... | |
| 2862 | 2818 |
break; |
| 2863 | 2819 |
case 1: |
| 2864 | 2820 |
check_insn(env, ctx, ASE_MT); |
| 2865 |
tcg_gen_helper_1_0(do_mfc0_tcstatus, t0);
|
|
| 2821 |
gen_helper_mfc0_tcstatus(t0);
|
|
| 2866 | 2822 |
rn = "TCStatus"; |
| 2867 | 2823 |
break; |
| 2868 | 2824 |
case 2: |
| 2869 | 2825 |
check_insn(env, ctx, ASE_MT); |
| 2870 |
tcg_gen_helper_1_0(do_mfc0_tcbind, t0);
|
|
| 2826 |
gen_helper_mfc0_tcbind(t0);
|
|
| 2871 | 2827 |
rn = "TCBind"; |
| 2872 | 2828 |
break; |
| 2873 | 2829 |
case 3: |
| 2874 | 2830 |
check_insn(env, ctx, ASE_MT); |
| 2875 |
tcg_gen_helper_1_0(do_mfc0_tcrestart, t0);
|
|
| 2831 |
gen_helper_mfc0_tcrestart(t0);
|
|
| 2876 | 2832 |
rn = "TCRestart"; |
| 2877 | 2833 |
break; |
| 2878 | 2834 |
case 4: |
| 2879 | 2835 |
check_insn(env, ctx, ASE_MT); |
| 2880 |
tcg_gen_helper_1_0(do_mfc0_tchalt, t0);
|
|
| 2836 |
gen_helper_mfc0_tchalt(t0);
|
|
| 2881 | 2837 |
rn = "TCHalt"; |
| 2882 | 2838 |
break; |
| 2883 | 2839 |
case 5: |
| 2884 | 2840 |
check_insn(env, ctx, ASE_MT); |
| 2885 |
tcg_gen_helper_1_0(do_mfc0_tccontext, t0);
|
|
| 2841 |
gen_helper_mfc0_tccontext(t0);
|
|
| 2886 | 2842 |
rn = "TCContext"; |
| 2887 | 2843 |
break; |
| 2888 | 2844 |
case 6: |
| 2889 | 2845 |
check_insn(env, ctx, ASE_MT); |
| 2890 |
tcg_gen_helper_1_0(do_mfc0_tcschedule, t0);
|
|
| 2846 |
gen_helper_mfc0_tcschedule(t0);
|
|
| 2891 | 2847 |
rn = "TCSchedule"; |
| 2892 | 2848 |
break; |
| 2893 | 2849 |
case 7: |
| 2894 | 2850 |
check_insn(env, ctx, ASE_MT); |
| 2895 |
tcg_gen_helper_1_0(do_mfc0_tcschefback, t0);
|
|
| 2851 |
gen_helper_mfc0_tcschefback(t0);
|
|
| 2896 | 2852 |
rn = "TCScheFBack"; |
| 2897 | 2853 |
break; |
| 2898 | 2854 |
default: |
| ... | ... | |
| 2918 | 2874 |
rn = "Context"; |
| 2919 | 2875 |
break; |
| 2920 | 2876 |
case 1: |
| 2921 |
// tcg_gen_helper_1_0(do_mfc0_contextconfig, t0); /* SmartMIPS ASE */
|
|
| 2877 |
// gen_helper_mfc0_contextconfig(t0); /* SmartMIPS ASE */
|
|
| 2922 | 2878 |
rn = "ContextConfig"; |
| 2923 | 2879 |
// break; |
| 2924 | 2880 |
default: |
| ... | ... | |
| 3003 | 2959 |
/* Mark as an IO operation because we read the time. */ |
| 3004 | 2960 |
if (use_icount) |
| 3005 | 2961 |
gen_io_start(); |
| 3006 |
tcg_gen_helper_1_0(do_mfc0_count, t0);
|
|
| 2962 |
gen_helper_mfc0_count(t0);
|
|
| 3007 | 2963 |
if (use_icount) {
|
| 3008 | 2964 |
gen_io_end(); |
| 3009 | 2965 |
ctx->bstate = BS_STOP; |
| ... | ... | |
| 3133 | 3089 |
case 17: |
| 3134 | 3090 |
switch (sel) {
|
| 3135 | 3091 |
case 0: |
| 3136 |
tcg_gen_helper_1_0(do_mfc0_lladdr, t0);
|
|
| 3092 |
gen_helper_mfc0_lladdr(t0);
|
|
| 3137 | 3093 |
rn = "LLAddr"; |
| 3138 | 3094 |
break; |
| 3139 | 3095 |
default: |
| ... | ... | |
| 3143 | 3099 |
case 18: |
| 3144 | 3100 |
switch (sel) {
|
| 3145 | 3101 |
case 0 ... 7: |
| 3146 |
tcg_gen_helper_1_i(do_mfc0_watchlo, t0, sel);
|
|
| 3102 |
gen_helper_1i(mfc0_watchlo, t0, sel);
|
|
| 3147 | 3103 |
rn = "WatchLo"; |
| 3148 | 3104 |
break; |
| 3149 | 3105 |
default: |
| ... | ... | |
| 3153 | 3109 |
case 19: |
| 3154 | 3110 |
switch (sel) {
|
| 3155 | 3111 |
case 0 ...7: |
| 3156 |
tcg_gen_helper_1_i(do_mfc0_watchhi, t0, sel);
|
|
| 3112 |
gen_helper_1i(mfc0_watchhi, t0, sel);
|
|
| 3157 | 3113 |
rn = "WatchHi"; |
| 3158 | 3114 |
break; |
| 3159 | 3115 |
default: |
| ... | ... | |
| 3192 | 3148 |
case 23: |
| 3193 | 3149 |
switch (sel) {
|
| 3194 | 3150 |
case 0: |
| 3195 |
tcg_gen_helper_1_0(do_mfc0_debug, t0); /* EJTAG support */
|
|
| 3151 |
gen_helper_mfc0_debug(t0); /* EJTAG support */
|
|
| 3196 | 3152 |
rn = "Debug"; |
| 3197 | 3153 |
break; |
| 3198 | 3154 |
case 1: |
| 3199 |
// tcg_gen_helper_1_0(do_mfc0_tracecontrol, t0); /* PDtrace support */
|
|
| 3155 |
// gen_helper_mfc0_tracecontrol(t0); /* PDtrace support */
|
|
| 3200 | 3156 |
rn = "TraceControl"; |
| 3201 | 3157 |
// break; |
| 3202 | 3158 |
case 2: |
| 3203 |
// tcg_gen_helper_1_0(do_mfc0_tracecontrol2, t0); /* PDtrace support */
|
|
| 3159 |
// gen_helper_mfc0_tracecontrol2(t0); /* PDtrace support */
|
|
| 3204 | 3160 |
rn = "TraceControl2"; |
| 3205 | 3161 |
// break; |
| 3206 | 3162 |
case 3: |
| 3207 |
// tcg_gen_helper_1_0(do_mfc0_usertracedata, t0); /* PDtrace support */
|
|
| 3163 |
// gen_helper_mfc0_usertracedata(t0); /* PDtrace support */
|
|
| 3208 | 3164 |
rn = "UserTraceData"; |
| 3209 | 3165 |
// break; |
| 3210 | 3166 |
case 4: |
| 3211 |
// tcg_gen_helper_1_0(do_mfc0_tracebpc, t0); /* PDtrace support */
|
|
| 3167 |
// gen_helper_mfc0_tracebpc(t0); /* PDtrace support */
|
|
| 3212 | 3168 |
rn = "TraceBPC"; |
| 3213 | 3169 |
// break; |
| 3214 | 3170 |
default: |
| ... | ... | |
| 3234 | 3190 |
rn = "Performance0"; |
| 3235 | 3191 |
break; |
| 3236 | 3192 |
case 1: |
| 3237 |
// tcg_gen_helper_1_0(do_mfc0_performance1, t0);
|
|
| 3193 |
// gen_helper_mfc0_performance1(t0);
|
|
| 3238 | 3194 |
rn = "Performance1"; |
| 3239 | 3195 |
// break; |
| 3240 | 3196 |
case 2: |
| 3241 |
// tcg_gen_helper_1_0(do_mfc0_performance2, t0);
|
|
| 3197 |
// gen_helper_mfc0_performance2(t0);
|
|
| 3242 | 3198 |
rn = "Performance2"; |
| 3243 | 3199 |
// break; |
| 3244 | 3200 |
case 3: |
| 3245 |
// tcg_gen_helper_1_0(do_mfc0_performance3, t0);
|
|
| 3201 |
// gen_helper_mfc0_performance3(t0);
|
|
| 3246 | 3202 |
rn = "Performance3"; |
| 3247 | 3203 |
// break; |
| 3248 | 3204 |
case 4: |
| 3249 |
// tcg_gen_helper_1_0(do_mfc0_performance4, t0);
|
|
| 3205 |
// gen_helper_mfc0_performance4(t0);
|
|
| 3250 | 3206 |
rn = "Performance4"; |
| 3251 | 3207 |
// break; |
| 3252 | 3208 |
case 5: |
| 3253 |
// tcg_gen_helper_1_0(do_mfc0_performance5, t0);
|
|
| 3209 |
// gen_helper_mfc0_performance5(t0);
|
|
| 3254 | 3210 |
rn = "Performance5"; |
| 3255 | 3211 |
// break; |
| 3256 | 3212 |
case 6: |
| 3257 |
// tcg_gen_helper_1_0(do_mfc0_performance6, t0);
|
|
| 3213 |
// gen_helper_mfc0_performance6(t0);
|
|
| 3258 | 3214 |
rn = "Performance6"; |
| 3259 | 3215 |
// break; |
| 3260 | 3216 |
case 7: |
| 3261 |
// tcg_gen_helper_1_0(do_mfc0_performance7, t0);
|
|
| 3217 |
// gen_helper_mfc0_performance7(t0);
|
|
| 3262 | 3218 |
rn = "Performance7"; |
| 3263 | 3219 |
// break; |
| 3264 | 3220 |
default: |
| ... | ... | |
| 3376 | 3332 |
case 0: |
| 3377 | 3333 |
switch (sel) {
|
| 3378 | 3334 |
case 0: |
| 3379 |
tcg_gen_helper_0_1(do_mtc0_index, t0);
|
|
| 3335 |
gen_helper_mtc0_index(t0);
|
|
| 3380 | 3336 |
rn = "Index"; |
| 3381 | 3337 |
break; |
| 3382 | 3338 |
case 1: |
| 3383 | 3339 |
check_insn(env, ctx, ASE_MT); |
| 3384 |
tcg_gen_helper_0_1(do_mtc0_mvpcontrol, t0);
|
|
| 3340 |
gen_helper_mtc0_mvpcontrol(t0);
|
|
| 3385 | 3341 |
rn = "MVPControl"; |
| 3386 | 3342 |
break; |
| 3387 | 3343 |
case 2: |
| ... | ... | |
| 3406 | 3362 |
break; |
| 3407 | 3363 |
case 1: |
| 3408 | 3364 |
check_insn(env, ctx, ASE_MT); |
| 3409 |
tcg_gen_helper_0_1(do_mtc0_vpecontrol, t0);
|
|
| 3365 |
gen_helper_mtc0_vpecontrol(t0);
|
|
| 3410 | 3366 |
rn = "VPEControl"; |
| 3411 | 3367 |
break; |
| 3412 | 3368 |
case 2: |
| 3413 | 3369 |
check_insn(env, ctx, ASE_MT); |
| 3414 |
tcg_gen_helper_0_1(do_mtc0_vpeconf0, t0);
|
|
| 3370 |
gen_helper_mtc0_vpeconf0(t0);
|
|
| 3415 | 3371 |
rn = "VPEConf0"; |
| 3416 | 3372 |
break; |
| 3417 | 3373 |
case 3: |
| 3418 | 3374 |
check_insn(env, ctx, ASE_MT); |
| 3419 |
tcg_gen_helper_0_1(do_mtc0_vpeconf1, t0);
|
|
| 3375 |
gen_helper_mtc0_vpeconf1(t0);
|
|
| 3420 | 3376 |
rn = "VPEConf1"; |
| 3421 | 3377 |
break; |
| 3422 | 3378 |
case 4: |
| 3423 | 3379 |
check_insn(env, ctx, ASE_MT); |
| 3424 |
tcg_gen_helper_0_1(do_mtc0_yqmask, t0);
|
|
| 3380 |
gen_helper_mtc0_yqmask(t0);
|
|
| 3425 | 3381 |
rn = "YQMask"; |
| 3426 | 3382 |
break; |
| 3427 | 3383 |
case 5: |
| ... | ... | |
| 3436 | 3392 |
break; |
| 3437 | 3393 |
case 7: |
| 3438 | 3394 |
check_insn(env, ctx, ASE_MT); |
| 3439 |
tcg_gen_helper_0_1(do_mtc0_vpeopt, t0);
|
|
| 3395 |
gen_helper_mtc0_vpeopt(t0);
|
|
| 3440 | 3396 |
rn = "VPEOpt"; |
| 3441 | 3397 |
break; |
| 3442 | 3398 |
default: |
| ... | ... | |
| 3446 | 3402 |
case 2: |
| 3447 | 3403 |
switch (sel) {
|
| 3448 | 3404 |
case 0: |
| 3449 |
tcg_gen_helper_0_1(do_mtc0_entrylo0, t0);
|
|
| 3405 |
gen_helper_mtc0_entrylo0(t0);
|
|
| 3450 | 3406 |
rn = "EntryLo0"; |
| 3451 | 3407 |
break; |
| 3452 | 3408 |
case 1: |
| 3453 | 3409 |
check_insn(env, ctx, ASE_MT); |
| 3454 |
tcg_gen_helper_0_1(do_mtc0_tcstatus, t0);
|
|
| 3410 |
gen_helper_mtc0_tcstatus(t0);
|
|
| 3455 | 3411 |
rn = "TCStatus"; |
| 3456 | 3412 |
break; |
| 3457 | 3413 |
case 2: |
| 3458 | 3414 |
check_insn(env, ctx, ASE_MT); |
| 3459 |
tcg_gen_helper_0_1(do_mtc0_tcbind, t0);
|
|
| 3415 |
gen_helper_mtc0_tcbind(t0);
|
|
| 3460 | 3416 |
rn = "TCBind"; |
| 3461 | 3417 |
break; |
| 3462 | 3418 |
case 3: |
| 3463 | 3419 |
check_insn(env, ctx, ASE_MT); |
| 3464 |
tcg_gen_helper_0_1(do_mtc0_tcrestart, t0);
|
|
| 3420 |
gen_helper_mtc0_tcrestart(t0);
|
|
| 3465 | 3421 |
rn = "TCRestart"; |
| 3466 | 3422 |
break; |
| 3467 | 3423 |
case 4: |
| 3468 | 3424 |
check_insn(env, ctx, ASE_MT); |
| 3469 |
tcg_gen_helper_0_1(do_mtc0_tchalt, t0);
|
|
| 3425 |
gen_helper_mtc0_tchalt(t0);
|
|
| 3470 | 3426 |
rn = "TCHalt"; |
| 3471 | 3427 |
break; |
| 3472 | 3428 |
case 5: |
| 3473 | 3429 |
check_insn(env, ctx, ASE_MT); |
| 3474 |
tcg_gen_helper_0_1(do_mtc0_tccontext, t0);
|
|
| 3430 |
gen_helper_mtc0_tccontext(t0);
|
|
| 3475 | 3431 |
rn = "TCContext"; |
| 3476 | 3432 |
break; |
| 3477 | 3433 |
case 6: |
| 3478 | 3434 |
check_insn(env, ctx, ASE_MT); |
| 3479 |
tcg_gen_helper_0_1(do_mtc0_tcschedule, t0);
|
|
| 3435 |
gen_helper_mtc0_tcschedule(t0);
|
|
| 3480 | 3436 |
rn = "TCSchedule"; |
| 3481 | 3437 |
break; |
| 3482 | 3438 |
case 7: |
| 3483 | 3439 |
check_insn(env, ctx, ASE_MT); |
| 3484 |
tcg_gen_helper_0_1(do_mtc0_tcschefback, t0);
|
|
| 3440 |
gen_helper_mtc0_tcschefback(t0);
|
|
| 3485 | 3441 |
rn = "TCScheFBack"; |
| 3486 | 3442 |
break; |
| 3487 | 3443 |
default: |
| ... | ... | |
| 3491 | 3447 |
case 3: |
| 3492 | 3448 |
switch (sel) {
|
| 3493 | 3449 |
case 0: |
| 3494 |
tcg_gen_helper_0_1(do_mtc0_entrylo1, t0);
|
|
| 3450 |
gen_helper_mtc0_entrylo1(t0);
|
|
| 3495 | 3451 |
rn = "EntryLo1"; |
| 3496 | 3452 |
break; |
| 3497 | 3453 |
default: |
| ... | ... | |
| 3501 | 3457 |
case 4: |
| 3502 | 3458 |
switch (sel) {
|
| 3503 | 3459 |
case 0: |
| 3504 |
tcg_gen_helper_0_1(do_mtc0_context, t0);
|
|
| 3460 |
gen_helper_mtc0_context(t0);
|
|
| 3505 | 3461 |
rn = "Context"; |
| 3506 | 3462 |
break; |
| 3507 | 3463 |
case 1: |
| 3508 |
// tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
|
|
| 3464 |
// gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
|
|
| 3509 | 3465 |
rn = "ContextConfig"; |
| 3510 | 3466 |
// break; |
| 3511 | 3467 |
default: |
| ... | ... | |
| 3515 | 3471 |
case 5: |
| 3516 | 3472 |
switch (sel) {
|
| 3517 | 3473 |
case 0: |
| 3518 |
tcg_gen_helper_0_1(do_mtc0_pagemask, t0);
|
|
| 3474 |
gen_helper_mtc0_pagemask(t0);
|
|
| 3519 | 3475 |
rn = "PageMask"; |
| 3520 | 3476 |
break; |
| 3521 | 3477 |
case 1: |
| 3522 | 3478 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3523 |
tcg_gen_helper_0_1(do_mtc0_pagegrain, t0);
|
|
| 3479 |
gen_helper_mtc0_pagegrain(t0);
|
|
| 3524 | 3480 |
rn = "PageGrain"; |
| 3525 | 3481 |
break; |
| 3526 | 3482 |
default: |
| ... | ... | |
| 3530 | 3486 |
case 6: |
| 3531 | 3487 |
switch (sel) {
|
| 3532 | 3488 |
case 0: |
| 3533 |
tcg_gen_helper_0_1(do_mtc0_wired, t0);
|
|
| 3489 |
gen_helper_mtc0_wired(t0);
|
|
| 3534 | 3490 |
rn = "Wired"; |
| 3535 | 3491 |
break; |
| 3536 | 3492 |
case 1: |
| 3537 | 3493 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3538 |
tcg_gen_helper_0_1(do_mtc0_srsconf0, t0);
|
|
| 3494 |
gen_helper_mtc0_srsconf0(t0);
|
|
| 3539 | 3495 |
rn = "SRSConf0"; |
| 3540 | 3496 |
break; |
| 3541 | 3497 |
case 2: |
| 3542 | 3498 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3543 |
tcg_gen_helper_0_1(do_mtc0_srsconf1, t0);
|
|
| 3499 |
gen_helper_mtc0_srsconf1(t0);
|
|
| 3544 | 3500 |
rn = "SRSConf1"; |
| 3545 | 3501 |
break; |
| 3546 | 3502 |
case 3: |
| 3547 | 3503 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3548 |
tcg_gen_helper_0_1(do_mtc0_srsconf2, t0);
|
|
| 3504 |
gen_helper_mtc0_srsconf2(t0);
|
|
| 3549 | 3505 |
rn = "SRSConf2"; |
| 3550 | 3506 |
break; |
| 3551 | 3507 |
case 4: |
| 3552 | 3508 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3553 |
tcg_gen_helper_0_1(do_mtc0_srsconf3, t0);
|
|
| 3509 |
gen_helper_mtc0_srsconf3(t0);
|
|
| 3554 | 3510 |
rn = "SRSConf3"; |
| 3555 | 3511 |
break; |
| 3556 | 3512 |
case 5: |
| 3557 | 3513 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3558 |
tcg_gen_helper_0_1(do_mtc0_srsconf4, t0);
|
|
| 3514 |
gen_helper_mtc0_srsconf4(t0);
|
|
| 3559 | 3515 |
rn = "SRSConf4"; |
| 3560 | 3516 |
break; |
| 3561 | 3517 |
default: |
| ... | ... | |
| 3566 | 3522 |
switch (sel) {
|
| 3567 | 3523 |
case 0: |
| 3568 | 3524 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3569 |
tcg_gen_helper_0_1(do_mtc0_hwrena, t0);
|
|
| 3525 |
gen_helper_mtc0_hwrena(t0);
|
|
| 3570 | 3526 |
rn = "HWREna"; |
| 3571 | 3527 |
break; |
| 3572 | 3528 |
default: |
| ... | ... | |
| 3580 | 3536 |
case 9: |
| 3581 | 3537 |
switch (sel) {
|
| 3582 | 3538 |
case 0: |
| 3583 |
tcg_gen_helper_0_1(do_mtc0_count, t0);
|
|
| 3539 |
gen_helper_mtc0_count(t0);
|
|
| 3584 | 3540 |
rn = "Count"; |
| 3585 | 3541 |
break; |
| 3586 | 3542 |
/* 6,7 are implementation dependent */ |
| ... | ... | |
| 3593 | 3549 |
case 10: |
| 3594 | 3550 |
switch (sel) {
|
| 3595 | 3551 |
case 0: |
| 3596 |
tcg_gen_helper_0_1(do_mtc0_entryhi, t0);
|
|
| 3552 |
gen_helper_mtc0_entryhi(t0);
|
|
| 3597 | 3553 |
rn = "EntryHi"; |
| 3598 | 3554 |
break; |
| 3599 | 3555 |
default: |
| ... | ... | |
| 3603 | 3559 |
case 11: |
| 3604 | 3560 |
switch (sel) {
|
| 3605 | 3561 |
case 0: |
| 3606 |
tcg_gen_helper_0_1(do_mtc0_compare, t0);
|
|
| 3562 |
gen_helper_mtc0_compare(t0);
|
|
| 3607 | 3563 |
rn = "Compare"; |
| 3608 | 3564 |
break; |
| 3609 | 3565 |
/* 6,7 are implementation dependent */ |
| ... | ... | |
| 3616 | 3572 |
case 12: |
| 3617 | 3573 |
switch (sel) {
|
| 3618 | 3574 |
case 0: |
| 3619 |
tcg_gen_helper_0_1(do_mtc0_status, t0);
|
|
| 3575 |
gen_helper_mtc0_status(t0);
|
|
| 3620 | 3576 |
/* BS_STOP isn't good enough here, hflags may have changed. */ |
| 3621 | 3577 |
gen_save_pc(ctx->pc + 4); |
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