Revision a7812ae4 target-sh4/translate.c
| b/target-sh4/translate.c | ||
|---|---|---|
| 31 | 31 |
#include "cpu.h" |
| 32 | 32 |
#include "exec-all.h" |
| 33 | 33 |
#include "disas.h" |
| 34 |
#include "helper.h" |
|
| 35 | 34 |
#include "tcg-op.h" |
| 36 | 35 |
#include "qemu-common.h" |
| 37 | 36 |
|
| 37 |
#include "helper.h" |
|
| 38 |
#define GEN_HELPER 1 |
|
| 39 |
#include "helper.h" |
|
| 40 |
|
|
| 38 | 41 |
typedef struct DisasContext {
|
| 39 | 42 |
struct TranslationBlock *tb; |
| 40 | 43 |
target_ulong pc; |
| ... | ... | |
| 64 | 67 |
}; |
| 65 | 68 |
|
| 66 | 69 |
/* global register indexes */ |
| 67 |
static TCGv cpu_env; |
|
| 70 |
static TCGv_ptr cpu_env;
|
|
| 68 | 71 |
static TCGv cpu_gregs[24]; |
| 69 | 72 |
static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr; |
| 70 | 73 |
static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; |
| ... | ... | |
| 90 | 93 |
if (done_init) |
| 91 | 94 |
return; |
| 92 | 95 |
|
| 93 |
cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
|
|
| 96 |
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
|
| 94 | 97 |
|
| 95 | 98 |
for (i = 0; i < 24; i++) |
| 96 |
cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 99 |
cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 97 | 100 |
offsetof(CPUState, gregs[i]), |
| 98 | 101 |
gregnames[i]); |
| 99 | 102 |
|
| 100 |
cpu_pc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 101 |
offsetof(CPUState, pc), "PC"); |
|
| 102 |
cpu_sr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 103 |
offsetof(CPUState, sr), "SR"); |
|
| 104 |
cpu_ssr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 105 |
offsetof(CPUState, ssr), "SSR"); |
|
| 106 |
cpu_spc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 107 |
offsetof(CPUState, spc), "SPC"); |
|
| 108 |
cpu_gbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 109 |
offsetof(CPUState, gbr), "GBR"); |
|
| 110 |
cpu_vbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 111 |
offsetof(CPUState, vbr), "VBR"); |
|
| 112 |
cpu_sgr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 113 |
offsetof(CPUState, sgr), "SGR"); |
|
| 114 |
cpu_dbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 115 |
offsetof(CPUState, dbr), "DBR"); |
|
| 116 |
cpu_mach = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 117 |
offsetof(CPUState, mach), "MACH"); |
|
| 118 |
cpu_macl = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 119 |
offsetof(CPUState, macl), "MACL"); |
|
| 120 |
cpu_pr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 121 |
offsetof(CPUState, pr), "PR"); |
|
| 122 |
cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 123 |
offsetof(CPUState, fpscr), "FPSCR"); |
|
| 124 |
cpu_fpul = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 125 |
offsetof(CPUState, fpul), "FPUL"); |
|
| 126 |
|
|
| 127 |
cpu_flags = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 128 |
offsetof(CPUState, flags), "_flags_"); |
|
| 129 |
cpu_delayed_pc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
|
|
| 130 |
offsetof(CPUState, delayed_pc), |
|
| 131 |
"_delayed_pc_"); |
|
| 103 |
cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 104 |
offsetof(CPUState, pc), "PC");
|
|
| 105 |
cpu_sr = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 106 |
offsetof(CPUState, sr), "SR");
|
|
| 107 |
cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 108 |
offsetof(CPUState, ssr), "SSR");
|
|
| 109 |
cpu_spc = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 110 |
offsetof(CPUState, spc), "SPC");
|
|
| 111 |
cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 112 |
offsetof(CPUState, gbr), "GBR");
|
|
| 113 |
cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 114 |
offsetof(CPUState, vbr), "VBR");
|
|
| 115 |
cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 116 |
offsetof(CPUState, sgr), "SGR");
|
|
| 117 |
cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 118 |
offsetof(CPUState, dbr), "DBR");
|
|
| 119 |
cpu_mach = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 120 |
offsetof(CPUState, mach), "MACH");
|
|
| 121 |
cpu_macl = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 122 |
offsetof(CPUState, macl), "MACL");
|
|
| 123 |
cpu_pr = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 124 |
offsetof(CPUState, pr), "PR");
|
|
| 125 |
cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 126 |
offsetof(CPUState, fpscr), "FPSCR");
|
|
| 127 |
cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 128 |
offsetof(CPUState, fpul), "FPUL");
|
|
| 129 |
|
|
| 130 |
cpu_flags = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 131 |
offsetof(CPUState, flags), "_flags_");
|
|
| 132 |
cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0,
|
|
| 133 |
offsetof(CPUState, delayed_pc),
|
|
| 134 |
"_delayed_pc_");
|
|
| 132 | 135 |
|
| 133 | 136 |
/* register helpers */ |
| 134 |
#undef DEF_HELPER |
|
| 135 |
#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); |
|
| 137 |
#define GEN_HELPER 2 |
|
| 136 | 138 |
#include "helper.h" |
| 137 | 139 |
|
| 138 | 140 |
done_init = 1; |
| ... | ... | |
| 270 | 272 |
} else {
|
| 271 | 273 |
tcg_gen_movi_i32(cpu_pc, dest); |
| 272 | 274 |
if (ctx->singlestep_enabled) |
| 273 |
tcg_gen_helper_0_0(helper_debug);
|
|
| 275 |
gen_helper_debug();
|
|
| 274 | 276 |
tcg_gen_exit_tb(0); |
| 275 | 277 |
} |
| 276 | 278 |
} |
| ... | ... | |
| 282 | 284 |
delayed jump as immediate jump are conditinal jumps */ |
| 283 | 285 |
tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); |
| 284 | 286 |
if (ctx->singlestep_enabled) |
| 285 |
tcg_gen_helper_0_0(helper_debug);
|
|
| 287 |
gen_helper_debug();
|
|
| 286 | 288 |
tcg_gen_exit_tb(0); |
| 287 | 289 |
} else {
|
| 288 | 290 |
gen_goto_tb(ctx, 0, ctx->delayed_pc); |
| ... | ... | |
| 294 | 296 |
TCGv sr; |
| 295 | 297 |
int label = gen_new_label(); |
| 296 | 298 |
tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc); |
| 297 |
sr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 299 |
sr = tcg_temp_new(); |
|
| 298 | 300 |
tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
| 299 | 301 |
tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label); |
| 300 | 302 |
tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); |
| ... | ... | |
| 309 | 311 |
TCGv sr; |
| 310 | 312 |
|
| 311 | 313 |
l1 = gen_new_label(); |
| 312 |
sr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 314 |
sr = tcg_temp_new(); |
|
| 313 | 315 |
tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
| 314 | 316 |
tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1); |
| 315 | 317 |
gen_goto_tb(ctx, 0, ifnott); |
| ... | ... | |
| 324 | 326 |
TCGv ds; |
| 325 | 327 |
|
| 326 | 328 |
l1 = gen_new_label(); |
| 327 |
ds = tcg_temp_new(TCG_TYPE_I32);
|
|
| 329 |
ds = tcg_temp_new(); |
|
| 328 | 330 |
tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE); |
| 329 | 331 |
tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1); |
| 330 | 332 |
gen_goto_tb(ctx, 1, ctx->pc + 2); |
| ... | ... | |
| 375 | 377 |
|
| 376 | 378 |
static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1) |
| 377 | 379 |
{
|
| 378 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 380 |
TCGv tmp = tcg_temp_new(); |
|
| 379 | 381 |
|
| 380 | 382 |
p0 &= 0x1f; |
| 381 | 383 |
p1 &= 0x1f; |
| ... | ... | |
| 392 | 394 |
} |
| 393 | 395 |
|
| 394 | 396 |
|
| 395 |
static inline void gen_load_fpr32(TCGv t, int reg) |
|
| 397 |
static inline void gen_load_fpr32(TCGv_i32 t, int reg)
|
|
| 396 | 398 |
{
|
| 397 | 399 |
tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, fregs[reg])); |
| 398 | 400 |
} |
| 399 | 401 |
|
| 400 |
static inline void gen_load_fpr64(TCGv t, int reg) |
|
| 402 |
static inline void gen_load_fpr64(TCGv_i64 t, int reg)
|
|
| 401 | 403 |
{
|
| 402 |
TCGv tmp1 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 403 |
TCGv tmp2 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 404 |
TCGv_i32 tmp1 = tcg_temp_new_i32();
|
|
| 405 |
TCGv_i32 tmp2 = tcg_temp_new_i32();
|
|
| 404 | 406 |
|
| 405 | 407 |
tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg])); |
| 406 | 408 |
tcg_gen_ld_i32(tmp2, cpu_env, offsetof(CPUState, fregs[reg + 1])); |
| 407 | 409 |
tcg_gen_concat_i32_i64(t, tmp2, tmp1); |
| 408 |
tcg_temp_free(tmp1); |
|
| 409 |
tcg_temp_free(tmp2); |
|
| 410 |
tcg_temp_free_i32(tmp1);
|
|
| 411 |
tcg_temp_free_i32(tmp2);
|
|
| 410 | 412 |
} |
| 411 | 413 |
|
| 412 |
static inline void gen_store_fpr32(TCGv t, int reg) |
|
| 414 |
static inline void gen_store_fpr32(TCGv_i32 t, int reg)
|
|
| 413 | 415 |
{
|
| 414 | 416 |
tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, fregs[reg])); |
| 415 | 417 |
} |
| 416 | 418 |
|
| 417 |
static inline void gen_store_fpr64 (TCGv t, int reg) |
|
| 419 |
static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
|
|
| 418 | 420 |
{
|
| 419 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 421 |
TCGv_i32 tmp = tcg_temp_new_i32();
|
|
| 420 | 422 |
|
| 421 | 423 |
tcg_gen_trunc_i64_i32(tmp, t); |
| 422 | 424 |
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg + 1])); |
| 423 | 425 |
tcg_gen_shri_i64(t, t, 32); |
| 424 | 426 |
tcg_gen_trunc_i64_i32(tmp, t); |
| 425 | 427 |
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg])); |
| 426 |
tcg_temp_free(tmp); |
|
| 428 |
tcg_temp_free_i32(tmp);
|
|
| 427 | 429 |
} |
| 428 | 430 |
|
| 429 | 431 |
#define B3_0 (ctx->opcode & 0xf) |
| ... | ... | |
| 449 | 451 |
|
| 450 | 452 |
#define CHECK_NOT_DELAY_SLOT \ |
| 451 | 453 |
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \ |
| 452 |
{tcg_gen_helper_0_0(helper_raise_slot_illegal_instruction); ctx->bstate = BS_EXCP; \
|
|
| 454 |
{gen_helper_raise_slot_illegal_instruction(); ctx->bstate = BS_EXCP; \
|
|
| 453 | 455 |
return;} |
| 454 | 456 |
|
| 455 | 457 |
#define CHECK_PRIVILEGED \ |
| 456 | 458 |
if (IS_USER(ctx)) { \
|
| 457 |
tcg_gen_helper_0_0(helper_raise_illegal_instruction); \
|
|
| 459 |
gen_helper_raise_illegal_instruction(); \
|
|
| 458 | 460 |
ctx->bstate = BS_EXCP; \ |
| 459 | 461 |
return; \ |
| 460 | 462 |
} |
| ... | ... | |
| 486 | 488 |
return; |
| 487 | 489 |
case 0x0038: /* ldtlb */ |
| 488 | 490 |
CHECK_PRIVILEGED |
| 489 |
tcg_gen_helper_0_0(helper_ldtlb);
|
|
| 491 |
gen_helper_ldtlb();
|
|
| 490 | 492 |
return; |
| 491 | 493 |
case 0x002b: /* rte */ |
| 492 | 494 |
CHECK_PRIVILEGED |
| ... | ... | |
| 514 | 516 |
return; |
| 515 | 517 |
case 0x001b: /* sleep */ |
| 516 | 518 |
CHECK_PRIVILEGED |
| 517 |
tcg_gen_helper_0_1(helper_sleep, tcg_const_i32(ctx->pc + 2));
|
|
| 519 |
gen_helper_sleep(tcg_const_i32(ctx->pc + 2));
|
|
| 518 | 520 |
return; |
| 519 | 521 |
} |
| 520 | 522 |
|
| 521 | 523 |
switch (ctx->opcode & 0xf000) {
|
| 522 | 524 |
case 0x1000: /* mov.l Rm,@(disp,Rn) */ |
| 523 | 525 |
{
|
| 524 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 526 |
TCGv addr = tcg_temp_new(); |
|
| 525 | 527 |
tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); |
| 526 | 528 |
tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); |
| 527 | 529 |
tcg_temp_free(addr); |
| ... | ... | |
| 529 | 531 |
return; |
| 530 | 532 |
case 0x5000: /* mov.l @(disp,Rm),Rn */ |
| 531 | 533 |
{
|
| 532 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 534 |
TCGv addr = tcg_temp_new(); |
|
| 533 | 535 |
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); |
| 534 | 536 |
tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); |
| 535 | 537 |
tcg_temp_free(addr); |
| ... | ... | |
| 594 | 596 |
return; |
| 595 | 597 |
case 0x2004: /* mov.b Rm,@-Rn */ |
| 596 | 598 |
{
|
| 597 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 599 |
TCGv addr = tcg_temp_new(); |
|
| 598 | 600 |
tcg_gen_subi_i32(addr, REG(B11_8), 1); |
| 599 | 601 |
tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */ |
| 600 | 602 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */ |
| ... | ... | |
| 603 | 605 |
return; |
| 604 | 606 |
case 0x2005: /* mov.w Rm,@-Rn */ |
| 605 | 607 |
{
|
| 606 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 608 |
TCGv addr = tcg_temp_new(); |
|
| 607 | 609 |
tcg_gen_subi_i32(addr, REG(B11_8), 2); |
| 608 | 610 |
tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); |
| 609 | 611 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2); |
| ... | ... | |
| 612 | 614 |
return; |
| 613 | 615 |
case 0x2006: /* mov.l Rm,@-Rn */ |
| 614 | 616 |
{
|
| 615 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 617 |
TCGv addr = tcg_temp_new(); |
|
| 616 | 618 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 617 | 619 |
tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); |
| 618 | 620 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); |
| ... | ... | |
| 635 | 637 |
return; |
| 636 | 638 |
case 0x0004: /* mov.b Rm,@(R0,Rn) */ |
| 637 | 639 |
{
|
| 638 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 640 |
TCGv addr = tcg_temp_new(); |
|
| 639 | 641 |
tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
| 640 | 642 |
tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); |
| 641 | 643 |
tcg_temp_free(addr); |
| ... | ... | |
| 643 | 645 |
return; |
| 644 | 646 |
case 0x0005: /* mov.w Rm,@(R0,Rn) */ |
| 645 | 647 |
{
|
| 646 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 648 |
TCGv addr = tcg_temp_new(); |
|
| 647 | 649 |
tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
| 648 | 650 |
tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); |
| 649 | 651 |
tcg_temp_free(addr); |
| ... | ... | |
| 651 | 653 |
return; |
| 652 | 654 |
case 0x0006: /* mov.l Rm,@(R0,Rn) */ |
| 653 | 655 |
{
|
| 654 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 656 |
TCGv addr = tcg_temp_new(); |
|
| 655 | 657 |
tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
| 656 | 658 |
tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); |
| 657 | 659 |
tcg_temp_free(addr); |
| ... | ... | |
| 659 | 661 |
return; |
| 660 | 662 |
case 0x000c: /* mov.b @(R0,Rm),Rn */ |
| 661 | 663 |
{
|
| 662 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 664 |
TCGv addr = tcg_temp_new(); |
|
| 663 | 665 |
tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
| 664 | 666 |
tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx); |
| 665 | 667 |
tcg_temp_free(addr); |
| ... | ... | |
| 667 | 669 |
return; |
| 668 | 670 |
case 0x000d: /* mov.w @(R0,Rm),Rn */ |
| 669 | 671 |
{
|
| 670 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 672 |
TCGv addr = tcg_temp_new(); |
|
| 671 | 673 |
tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
| 672 | 674 |
tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); |
| 673 | 675 |
tcg_temp_free(addr); |
| ... | ... | |
| 675 | 677 |
return; |
| 676 | 678 |
case 0x000e: /* mov.l @(R0,Rm),Rn */ |
| 677 | 679 |
{
|
| 678 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 680 |
TCGv addr = tcg_temp_new(); |
|
| 679 | 681 |
tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
| 680 | 682 |
tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); |
| 681 | 683 |
tcg_temp_free(addr); |
| ... | ... | |
| 684 | 686 |
case 0x6008: /* swap.b Rm,Rn */ |
| 685 | 687 |
{
|
| 686 | 688 |
TCGv highw, high, low; |
| 687 |
highw = tcg_temp_new(TCG_TYPE_I32);
|
|
| 689 |
highw = tcg_temp_new(); |
|
| 688 | 690 |
tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000); |
| 689 |
high = tcg_temp_new(TCG_TYPE_I32);
|
|
| 691 |
high = tcg_temp_new(); |
|
| 690 | 692 |
tcg_gen_ext8u_i32(high, REG(B7_4)); |
| 691 | 693 |
tcg_gen_shli_i32(high, high, 8); |
| 692 |
low = tcg_temp_new(TCG_TYPE_I32);
|
|
| 694 |
low = tcg_temp_new(); |
|
| 693 | 695 |
tcg_gen_shri_i32(low, REG(B7_4), 8); |
| 694 | 696 |
tcg_gen_ext8u_i32(low, low); |
| 695 | 697 |
tcg_gen_or_i32(REG(B11_8), high, low); |
| ... | ... | |
| 701 | 703 |
case 0x6009: /* swap.w Rm,Rn */ |
| 702 | 704 |
{
|
| 703 | 705 |
TCGv high, low; |
| 704 |
high = tcg_temp_new(TCG_TYPE_I32);
|
|
| 706 |
high = tcg_temp_new(); |
|
| 705 | 707 |
tcg_gen_ext16u_i32(high, REG(B7_4)); |
| 706 | 708 |
tcg_gen_shli_i32(high, high, 16); |
| 707 |
low = tcg_temp_new(TCG_TYPE_I32);
|
|
| 709 |
low = tcg_temp_new(); |
|
| 708 | 710 |
tcg_gen_shri_i32(low, REG(B7_4), 16); |
| 709 | 711 |
tcg_gen_ext16u_i32(low, low); |
| 710 | 712 |
tcg_gen_or_i32(REG(B11_8), high, low); |
| ... | ... | |
| 715 | 717 |
case 0x200d: /* xtrct Rm,Rn */ |
| 716 | 718 |
{
|
| 717 | 719 |
TCGv high, low; |
| 718 |
high = tcg_temp_new(TCG_TYPE_I32);
|
|
| 720 |
high = tcg_temp_new(); |
|
| 719 | 721 |
tcg_gen_ext16u_i32(high, REG(B7_4)); |
| 720 | 722 |
tcg_gen_shli_i32(high, high, 16); |
| 721 |
low = tcg_temp_new(TCG_TYPE_I32);
|
|
| 723 |
low = tcg_temp_new(); |
|
| 722 | 724 |
tcg_gen_shri_i32(low, REG(B11_8), 16); |
| 723 | 725 |
tcg_gen_ext16u_i32(low, low); |
| 724 | 726 |
tcg_gen_or_i32(REG(B11_8), high, low); |
| ... | ... | |
| 730 | 732 |
tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
| 731 | 733 |
return; |
| 732 | 734 |
case 0x300e: /* addc Rm,Rn */ |
| 733 |
tcg_gen_helper_1_2(helper_addc, REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 735 |
gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 734 | 736 |
return; |
| 735 | 737 |
case 0x300f: /* addv Rm,Rn */ |
| 736 |
tcg_gen_helper_1_2(helper_addv, REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 738 |
gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 737 | 739 |
return; |
| 738 | 740 |
case 0x2009: /* and Rm,Rn */ |
| 739 | 741 |
tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
| ... | ... | |
| 781 | 783 |
{
|
| 782 | 784 |
gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */ |
| 783 | 785 |
gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */ |
| 784 |
TCGv val = tcg_temp_new(TCG_TYPE_I32);
|
|
| 786 |
TCGv val = tcg_temp_new(); |
|
| 785 | 787 |
tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8)); |
| 786 | 788 |
gen_copy_bit_i32(cpu_sr, 0, val, 31); /* SR_T */ |
| 787 | 789 |
tcg_temp_free(val); |
| 788 | 790 |
} |
| 789 | 791 |
return; |
| 790 | 792 |
case 0x3004: /* div1 Rm,Rn */ |
| 791 |
tcg_gen_helper_1_2(helper_div1, REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 793 |
gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 792 | 794 |
return; |
| 793 | 795 |
case 0x300d: /* dmuls.l Rm,Rn */ |
| 794 | 796 |
{
|
| 795 |
TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 796 |
TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 797 |
TCGv_i64 tmp1 = tcg_temp_new_i64();
|
|
| 798 |
TCGv_i64 tmp2 = tcg_temp_new_i64();
|
|
| 797 | 799 |
|
| 798 | 800 |
tcg_gen_ext_i32_i64(tmp1, REG(B7_4)); |
| 799 | 801 |
tcg_gen_ext_i32_i64(tmp2, REG(B11_8)); |
| ... | ... | |
| 802 | 804 |
tcg_gen_shri_i64(tmp1, tmp1, 32); |
| 803 | 805 |
tcg_gen_trunc_i64_i32(cpu_mach, tmp1); |
| 804 | 806 |
|
| 805 |
tcg_temp_free(tmp2); |
|
| 806 |
tcg_temp_free(tmp1); |
|
| 807 |
tcg_temp_free_i64(tmp2);
|
|
| 808 |
tcg_temp_free_i64(tmp1);
|
|
| 807 | 809 |
} |
| 808 | 810 |
return; |
| 809 | 811 |
case 0x3005: /* dmulu.l Rm,Rn */ |
| 810 | 812 |
{
|
| 811 |
TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 812 |
TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 813 |
TCGv_i64 tmp1 = tcg_temp_new_i64();
|
|
| 814 |
TCGv_i64 tmp2 = tcg_temp_new_i64();
|
|
| 813 | 815 |
|
| 814 | 816 |
tcg_gen_extu_i32_i64(tmp1, REG(B7_4)); |
| 815 | 817 |
tcg_gen_extu_i32_i64(tmp2, REG(B11_8)); |
| ... | ... | |
| 818 | 820 |
tcg_gen_shri_i64(tmp1, tmp1, 32); |
| 819 | 821 |
tcg_gen_trunc_i64_i32(cpu_mach, tmp1); |
| 820 | 822 |
|
| 821 |
tcg_temp_free(tmp2); |
|
| 822 |
tcg_temp_free(tmp1); |
|
| 823 |
tcg_temp_free_i64(tmp2);
|
|
| 824 |
tcg_temp_free_i64(tmp1);
|
|
| 823 | 825 |
} |
| 824 | 826 |
return; |
| 825 | 827 |
case 0x600e: /* exts.b Rm,Rn */ |
| ... | ... | |
| 837 | 839 |
case 0x000f: /* mac.l @Rm+,@Rn+ */ |
| 838 | 840 |
{
|
| 839 | 841 |
TCGv arg0, arg1; |
| 840 |
arg0 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 842 |
arg0 = tcg_temp_new(); |
|
| 841 | 843 |
tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
| 842 |
arg1 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 844 |
arg1 = tcg_temp_new(); |
|
| 843 | 845 |
tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
| 844 |
tcg_gen_helper_0_2(helper_macl, arg0, arg1);
|
|
| 846 |
gen_helper_macl(arg0, arg1);
|
|
| 845 | 847 |
tcg_temp_free(arg1); |
| 846 | 848 |
tcg_temp_free(arg0); |
| 847 | 849 |
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); |
| ... | ... | |
| 851 | 853 |
case 0x400f: /* mac.w @Rm+,@Rn+ */ |
| 852 | 854 |
{
|
| 853 | 855 |
TCGv arg0, arg1; |
| 854 |
arg0 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 856 |
arg0 = tcg_temp_new(); |
|
| 855 | 857 |
tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
| 856 |
arg1 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 858 |
arg1 = tcg_temp_new(); |
|
| 857 | 859 |
tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
| 858 |
tcg_gen_helper_0_2(helper_macw, arg0, arg1);
|
|
| 860 |
gen_helper_macw(arg0, arg1);
|
|
| 859 | 861 |
tcg_temp_free(arg1); |
| 860 | 862 |
tcg_temp_free(arg0); |
| 861 | 863 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2); |
| ... | ... | |
| 868 | 870 |
case 0x200f: /* muls.w Rm,Rn */ |
| 869 | 871 |
{
|
| 870 | 872 |
TCGv arg0, arg1; |
| 871 |
arg0 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 873 |
arg0 = tcg_temp_new(); |
|
| 872 | 874 |
tcg_gen_ext16s_i32(arg0, REG(B7_4)); |
| 873 |
arg1 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 875 |
arg1 = tcg_temp_new(); |
|
| 874 | 876 |
tcg_gen_ext16s_i32(arg1, REG(B11_8)); |
| 875 | 877 |
tcg_gen_mul_i32(cpu_macl, arg0, arg1); |
| 876 | 878 |
tcg_temp_free(arg1); |
| ... | ... | |
| 880 | 882 |
case 0x200e: /* mulu.w Rm,Rn */ |
| 881 | 883 |
{
|
| 882 | 884 |
TCGv arg0, arg1; |
| 883 |
arg0 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 885 |
arg0 = tcg_temp_new(); |
|
| 884 | 886 |
tcg_gen_ext16u_i32(arg0, REG(B7_4)); |
| 885 |
arg1 = tcg_temp_new(TCG_TYPE_I32);
|
|
| 887 |
arg1 = tcg_temp_new(); |
|
| 886 | 888 |
tcg_gen_ext16u_i32(arg1, REG(B11_8)); |
| 887 | 889 |
tcg_gen_mul_i32(cpu_macl, arg0, arg1); |
| 888 | 890 |
tcg_temp_free(arg1); |
| ... | ... | |
| 893 | 895 |
tcg_gen_neg_i32(REG(B11_8), REG(B7_4)); |
| 894 | 896 |
return; |
| 895 | 897 |
case 0x600a: /* negc Rm,Rn */ |
| 896 |
tcg_gen_helper_1_1(helper_negc, REG(B11_8), REG(B7_4));
|
|
| 898 |
gen_helper_negc(REG(B11_8), REG(B7_4));
|
|
| 897 | 899 |
return; |
| 898 | 900 |
case 0x6007: /* not Rm,Rn */ |
| 899 | 901 |
tcg_gen_not_i32(REG(B11_8), REG(B7_4)); |
| ... | ... | |
| 964 | 966 |
tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
| 965 | 967 |
return; |
| 966 | 968 |
case 0x300a: /* subc Rm,Rn */ |
| 967 |
tcg_gen_helper_1_2(helper_subc, REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 969 |
gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 968 | 970 |
return; |
| 969 | 971 |
case 0x300b: /* subv Rm,Rn */ |
| 970 |
tcg_gen_helper_1_2(helper_subv, REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 972 |
gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8));
|
|
| 971 | 973 |
return; |
| 972 | 974 |
case 0x2008: /* tst Rm,Rn */ |
| 973 | 975 |
{
|
| 974 |
TCGv val = tcg_temp_new(TCG_TYPE_I32);
|
|
| 976 |
TCGv val = tcg_temp_new(); |
|
| 975 | 977 |
tcg_gen_and_i32(val, REG(B7_4), REG(B11_8)); |
| 976 | 978 |
gen_cmp_imm(TCG_COND_EQ, val, 0); |
| 977 | 979 |
tcg_temp_free(val); |
| ... | ... | |
| 982 | 984 |
return; |
| 983 | 985 |
case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
|
| 984 | 986 |
if (ctx->fpscr & FPSCR_SZ) {
|
| 985 |
TCGv fp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 987 |
TCGv_i64 fp = tcg_temp_new_i64();
|
|
| 986 | 988 |
gen_load_fpr64(fp, XREG(B7_4)); |
| 987 | 989 |
gen_store_fpr64(fp, XREG(B11_8)); |
| 988 |
tcg_temp_free(fp); |
|
| 990 |
tcg_temp_free_i64(fp);
|
|
| 989 | 991 |
} else {
|
| 990 |
TCGv fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 992 |
TCGv_i32 fp = tcg_temp_new_i32();
|
|
| 991 | 993 |
gen_load_fpr32(fp, FREG(B7_4)); |
| 992 | 994 |
gen_store_fpr32(fp, FREG(B11_8)); |
| 993 |
tcg_temp_free(fp); |
|
| 995 |
tcg_temp_free_i32(fp);
|
|
| 994 | 996 |
} |
| 995 | 997 |
return; |
| 996 | 998 |
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
|
| 997 | 999 |
if (ctx->fpscr & FPSCR_SZ) {
|
| 998 |
TCGv fp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1000 |
TCGv_i64 fp = tcg_temp_new_i64();
|
|
| 999 | 1001 |
gen_load_fpr64(fp, XREG(B7_4)); |
| 1000 | 1002 |
tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx); |
| 1001 |
tcg_temp_free(fp); |
|
| 1003 |
tcg_temp_free_i64(fp);
|
|
| 1002 | 1004 |
} else {
|
| 1003 |
TCGv fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1005 |
TCGv_i32 fp = tcg_temp_new_i32();
|
|
| 1004 | 1006 |
gen_load_fpr32(fp, FREG(B7_4)); |
| 1005 | 1007 |
tcg_gen_qemu_st32(fp, REG(B11_8), ctx->memidx); |
| 1006 |
tcg_temp_free(fp); |
|
| 1008 |
tcg_temp_free_i32(fp);
|
|
| 1007 | 1009 |
} |
| 1008 | 1010 |
return; |
| 1009 | 1011 |
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
|
| 1010 | 1012 |
if (ctx->fpscr & FPSCR_SZ) {
|
| 1011 |
TCGv fp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1013 |
TCGv_i64 fp = tcg_temp_new_i64();
|
|
| 1012 | 1014 |
tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx); |
| 1013 | 1015 |
gen_store_fpr64(fp, XREG(B11_8)); |
| 1014 |
tcg_temp_free(fp); |
|
| 1016 |
tcg_temp_free_i64(fp);
|
|
| 1015 | 1017 |
} else {
|
| 1016 |
TCGv fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1018 |
TCGv_i32 fp = tcg_temp_new_i32();
|
|
| 1017 | 1019 |
tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx); |
| 1018 | 1020 |
gen_store_fpr32(fp, FREG(B11_8)); |
| 1019 |
tcg_temp_free(fp); |
|
| 1021 |
tcg_temp_free_i32(fp);
|
|
| 1020 | 1022 |
} |
| 1021 | 1023 |
return; |
| 1022 | 1024 |
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
|
| 1023 | 1025 |
if (ctx->fpscr & FPSCR_SZ) {
|
| 1024 |
TCGv fp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1026 |
TCGv_i64 fp = tcg_temp_new_i64();
|
|
| 1025 | 1027 |
tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx); |
| 1026 | 1028 |
gen_store_fpr64(fp, XREG(B11_8)); |
| 1027 |
tcg_temp_free(fp); |
|
| 1029 |
tcg_temp_free_i64(fp);
|
|
| 1028 | 1030 |
tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8); |
| 1029 | 1031 |
} else {
|
| 1030 |
TCGv fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1032 |
TCGv_i32 fp = tcg_temp_new_i32();
|
|
| 1031 | 1033 |
tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx); |
| 1032 | 1034 |
gen_store_fpr32(fp, FREG(B11_8)); |
| 1033 |
tcg_temp_free(fp); |
|
| 1035 |
tcg_temp_free_i32(fp);
|
|
| 1034 | 1036 |
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); |
| 1035 | 1037 |
} |
| 1036 | 1038 |
return; |
| 1037 | 1039 |
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
|
| 1038 | 1040 |
if (ctx->fpscr & FPSCR_SZ) {
|
| 1039 |
TCGv addr, fp; |
|
| 1040 |
addr = tcg_temp_new(TCG_TYPE_I32); |
|
| 1041 |
TCGv addr; |
|
| 1042 |
TCGv_i64 fp; |
|
| 1043 |
addr = tcg_temp_new(); |
|
| 1041 | 1044 |
tcg_gen_subi_i32(addr, REG(B11_8), 8); |
| 1042 |
fp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1045 |
fp = tcg_temp_new_i64();
|
|
| 1043 | 1046 |
gen_load_fpr64(fp, XREG(B7_4)); |
| 1044 | 1047 |
tcg_gen_qemu_st64(fp, addr, ctx->memidx); |
| 1045 |
tcg_temp_free(fp); |
|
| 1048 |
tcg_temp_free_i64(fp);
|
|
| 1046 | 1049 |
tcg_temp_free(addr); |
| 1047 | 1050 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8); |
| 1048 | 1051 |
} else {
|
| 1049 |
TCGv addr, fp; |
|
| 1050 |
addr = tcg_temp_new(TCG_TYPE_I32); |
|
| 1052 |
TCGv addr; |
|
| 1053 |
TCGv_i32 fp; |
|
| 1054 |
addr = tcg_temp_new_i32(); |
|
| 1051 | 1055 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1052 |
fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1056 |
fp = tcg_temp_new_i32();
|
|
| 1053 | 1057 |
gen_load_fpr32(fp, FREG(B7_4)); |
| 1054 | 1058 |
tcg_gen_qemu_st32(fp, addr, ctx->memidx); |
| 1055 |
tcg_temp_free(fp); |
|
| 1059 |
tcg_temp_free_i32(fp);
|
|
| 1056 | 1060 |
tcg_temp_free(addr); |
| 1057 | 1061 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); |
| 1058 | 1062 |
} |
| 1059 | 1063 |
return; |
| 1060 | 1064 |
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
|
| 1061 | 1065 |
{
|
| 1062 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1066 |
TCGv addr = tcg_temp_new_i32();
|
|
| 1063 | 1067 |
tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
| 1064 | 1068 |
if (ctx->fpscr & FPSCR_SZ) {
|
| 1065 |
TCGv fp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1069 |
TCGv_i64 fp = tcg_temp_new_i64();
|
|
| 1066 | 1070 |
tcg_gen_qemu_ld64(fp, addr, ctx->memidx); |
| 1067 | 1071 |
gen_store_fpr64(fp, XREG(B11_8)); |
| 1068 |
tcg_temp_free(fp); |
|
| 1072 |
tcg_temp_free_i64(fp);
|
|
| 1069 | 1073 |
} else {
|
| 1070 |
TCGv fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1074 |
TCGv_i32 fp = tcg_temp_new_i32();
|
|
| 1071 | 1075 |
tcg_gen_qemu_ld32u(fp, addr, ctx->memidx); |
| 1072 | 1076 |
gen_store_fpr32(fp, FREG(B11_8)); |
| 1073 |
tcg_temp_free(fp); |
|
| 1077 |
tcg_temp_free_i32(fp);
|
|
| 1074 | 1078 |
} |
| 1075 | 1079 |
tcg_temp_free(addr); |
| 1076 | 1080 |
} |
| 1077 | 1081 |
return; |
| 1078 | 1082 |
case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
|
| 1079 | 1083 |
{
|
| 1080 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1084 |
TCGv addr = tcg_temp_new(); |
|
| 1081 | 1085 |
tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
| 1082 | 1086 |
if (ctx->fpscr & FPSCR_SZ) {
|
| 1083 |
TCGv fp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1087 |
TCGv_i64 fp = tcg_temp_new_i64();
|
|
| 1084 | 1088 |
gen_load_fpr64(fp, XREG(B7_4)); |
| 1085 | 1089 |
tcg_gen_qemu_st64(fp, addr, ctx->memidx); |
| 1086 |
tcg_temp_free(fp); |
|
| 1090 |
tcg_temp_free_i64(fp);
|
|
| 1087 | 1091 |
} else {
|
| 1088 |
TCGv fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1092 |
TCGv_i32 fp = tcg_temp_new_i32();
|
|
| 1089 | 1093 |
gen_load_fpr32(fp, FREG(B7_4)); |
| 1090 | 1094 |
tcg_gen_qemu_st32(fp, addr, ctx->memidx); |
| 1091 |
tcg_temp_free(fp); |
|
| 1095 |
tcg_temp_free_i32(fp);
|
|
| 1092 | 1096 |
} |
| 1093 | 1097 |
tcg_temp_free(addr); |
| 1094 | 1098 |
} |
| ... | ... | |
| 1100 | 1104 |
case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
| 1101 | 1105 |
case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
| 1102 | 1106 |
{
|
| 1103 |
TCGv fp0, fp1; |
|
| 1104 |
|
|
| 1105 | 1107 |
if (ctx->fpscr & FPSCR_PR) {
|
| 1108 |
TCGv_i64 fp0, fp1; |
|
| 1109 |
|
|
| 1106 | 1110 |
if (ctx->opcode & 0x0110) |
| 1107 | 1111 |
break; /* illegal instruction */ |
| 1108 |
fp0 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1109 |
fp1 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1112 |
fp0 = tcg_temp_new_i64();
|
|
| 1113 |
fp1 = tcg_temp_new_i64();
|
|
| 1110 | 1114 |
gen_load_fpr64(fp0, DREG(B11_8)); |
| 1111 | 1115 |
gen_load_fpr64(fp1, DREG(B7_4)); |
| 1112 |
} |
|
| 1113 |
else {
|
|
| 1114 |
fp0 = tcg_temp_new(TCG_TYPE_I32); |
|
| 1115 |
fp1 = tcg_temp_new(TCG_TYPE_I32); |
|
| 1116 |
switch (ctx->opcode & 0xf00f) {
|
|
| 1117 |
case 0xf000: /* fadd Rm,Rn */ |
|
| 1118 |
gen_helper_fadd_DT(fp0, fp0, fp1); |
|
| 1119 |
break; |
|
| 1120 |
case 0xf001: /* fsub Rm,Rn */ |
|
| 1121 |
gen_helper_fsub_DT(fp0, fp0, fp1); |
|
| 1122 |
break; |
|
| 1123 |
case 0xf002: /* fmul Rm,Rn */ |
|
| 1124 |
gen_helper_fmul_DT(fp0, fp0, fp1); |
|
| 1125 |
break; |
|
| 1126 |
case 0xf003: /* fdiv Rm,Rn */ |
|
| 1127 |
gen_helper_fdiv_DT(fp0, fp0, fp1); |
|
| 1128 |
break; |
|
| 1129 |
case 0xf004: /* fcmp/eq Rm,Rn */ |
|
| 1130 |
gen_helper_fcmp_eq_DT(fp0, fp1); |
|
| 1131 |
return; |
|
| 1132 |
case 0xf005: /* fcmp/gt Rm,Rn */ |
|
| 1133 |
gen_helper_fcmp_gt_DT(fp0, fp1); |
|
| 1134 |
return; |
|
| 1135 |
} |
|
| 1136 |
gen_store_fpr64(fp0, DREG(B11_8)); |
|
| 1137 |
tcg_temp_free_i64(fp0); |
|
| 1138 |
tcg_temp_free_i64(fp1); |
|
| 1139 |
} else {
|
|
| 1140 |
TCGv_i32 fp0, fp1; |
|
| 1141 |
|
|
| 1142 |
fp0 = tcg_temp_new_i32(); |
|
| 1143 |
fp1 = tcg_temp_new_i32(); |
|
| 1116 | 1144 |
gen_load_fpr32(fp0, FREG(B11_8)); |
| 1117 | 1145 |
gen_load_fpr32(fp1, FREG(B7_4)); |
| 1118 |
} |
|
| 1119 | 1146 |
|
| 1120 |
switch (ctx->opcode & 0xf00f) {
|
|
| 1121 |
case 0xf000: /* fadd Rm,Rn */ |
|
| 1122 |
if (ctx->fpscr & FPSCR_PR) |
|
| 1123 |
tcg_gen_helper_1_2(helper_fadd_DT, fp0, fp0, fp1); |
|
| 1124 |
else |
|
| 1125 |
tcg_gen_helper_1_2(helper_fadd_FT, fp0, fp0, fp1); |
|
| 1126 |
break; |
|
| 1127 |
case 0xf001: /* fsub Rm,Rn */ |
|
| 1128 |
if (ctx->fpscr & FPSCR_PR) |
|
| 1129 |
tcg_gen_helper_1_2(helper_fsub_DT, fp0, fp0, fp1); |
|
| 1130 |
else |
|
| 1131 |
tcg_gen_helper_1_2(helper_fsub_FT, fp0, fp0, fp1); |
|
| 1132 |
break; |
|
| 1133 |
case 0xf002: /* fmul Rm,Rn */ |
|
| 1134 |
if (ctx->fpscr & FPSCR_PR) |
|
| 1135 |
tcg_gen_helper_1_2(helper_fmul_DT, fp0, fp0, fp1); |
|
| 1136 |
else |
|
| 1137 |
tcg_gen_helper_1_2(helper_fmul_FT, fp0, fp0, fp1); |
|
| 1138 |
break; |
|
| 1139 |
case 0xf003: /* fdiv Rm,Rn */ |
|
| 1140 |
if (ctx->fpscr & FPSCR_PR) |
|
| 1141 |
tcg_gen_helper_1_2(helper_fdiv_DT, fp0, fp0, fp1); |
|
| 1142 |
else |
|
| 1143 |
tcg_gen_helper_1_2(helper_fdiv_FT, fp0, fp0, fp1); |
|
| 1144 |
break; |
|
| 1145 |
case 0xf004: /* fcmp/eq Rm,Rn */ |
|
| 1146 |
if (ctx->fpscr & FPSCR_PR) |
|
| 1147 |
tcg_gen_helper_0_2(helper_fcmp_eq_DT, fp0, fp1); |
|
| 1148 |
else |
|
| 1149 |
tcg_gen_helper_0_2(helper_fcmp_eq_FT, fp0, fp1); |
|
| 1150 |
return; |
|
| 1151 |
case 0xf005: /* fcmp/gt Rm,Rn */ |
|
| 1152 |
if (ctx->fpscr & FPSCR_PR) |
|
| 1153 |
tcg_gen_helper_0_2(helper_fcmp_gt_DT, fp0, fp1); |
|
| 1154 |
else |
|
| 1155 |
tcg_gen_helper_0_2(helper_fcmp_gt_FT, fp0, fp1); |
|
| 1156 |
return; |
|
| 1157 |
} |
|
| 1158 |
|
|
| 1159 |
if (ctx->fpscr & FPSCR_PR) {
|
|
| 1160 |
gen_store_fpr64(fp0, DREG(B11_8)); |
|
| 1161 |
} |
|
| 1162 |
else {
|
|
| 1147 |
switch (ctx->opcode & 0xf00f) {
|
|
| 1148 |
case 0xf000: /* fadd Rm,Rn */ |
|
| 1149 |
gen_helper_fadd_FT(fp0, fp0, fp1); |
|
| 1150 |
break; |
|
| 1151 |
case 0xf001: /* fsub Rm,Rn */ |
|
| 1152 |
gen_helper_fsub_FT(fp0, fp0, fp1); |
|
| 1153 |
break; |
|
| 1154 |
case 0xf002: /* fmul Rm,Rn */ |
|
| 1155 |
gen_helper_fmul_FT(fp0, fp0, fp1); |
|
| 1156 |
break; |
|
| 1157 |
case 0xf003: /* fdiv Rm,Rn */ |
|
| 1158 |
gen_helper_fdiv_FT(fp0, fp0, fp1); |
|
| 1159 |
break; |
|
| 1160 |
case 0xf004: /* fcmp/eq Rm,Rn */ |
|
| 1161 |
gen_helper_fcmp_eq_FT(fp0, fp1); |
|
| 1162 |
return; |
|
| 1163 |
case 0xf005: /* fcmp/gt Rm,Rn */ |
|
| 1164 |
gen_helper_fcmp_gt_FT(fp0, fp1); |
|
| 1165 |
return; |
|
| 1166 |
} |
|
| 1163 | 1167 |
gen_store_fpr32(fp0, FREG(B11_8)); |
| 1168 |
tcg_temp_free_i32(fp0); |
|
| 1169 |
tcg_temp_free_i32(fp1); |
|
| 1164 | 1170 |
} |
| 1165 |
tcg_temp_free(fp1); |
|
| 1166 |
tcg_temp_free(fp0); |
|
| 1167 | 1171 |
} |
| 1168 | 1172 |
return; |
| 1169 | 1173 |
} |
| ... | ... | |
| 1175 | 1179 |
case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
| 1176 | 1180 |
{
|
| 1177 | 1181 |
TCGv addr, val; |
| 1178 |
addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1182 |
addr = tcg_temp_new(); |
|
| 1179 | 1183 |
tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
| 1180 |
val = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1184 |
val = tcg_temp_new(); |
|
| 1181 | 1185 |
tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
| 1182 | 1186 |
tcg_gen_andi_i32(val, val, B7_0); |
| 1183 | 1187 |
tcg_gen_qemu_st8(val, addr, ctx->memidx); |
| ... | ... | |
| 1212 | 1216 |
return; |
| 1213 | 1217 |
case 0xc400: /* mov.b @(disp,GBR),R0 */ |
| 1214 | 1218 |
{
|
| 1215 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1219 |
TCGv addr = tcg_temp_new(); |
|
| 1216 | 1220 |
tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
| 1217 | 1221 |
tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx); |
| 1218 | 1222 |
tcg_temp_free(addr); |
| ... | ... | |
| 1220 | 1224 |
return; |
| 1221 | 1225 |
case 0xc500: /* mov.w @(disp,GBR),R0 */ |
| 1222 | 1226 |
{
|
| 1223 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1227 |
TCGv addr = tcg_temp_new(); |
|
| 1224 | 1228 |
tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); |
| 1225 | 1229 |
tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx); |
| 1226 | 1230 |
tcg_temp_free(addr); |
| ... | ... | |
| 1228 | 1232 |
return; |
| 1229 | 1233 |
case 0xc600: /* mov.l @(disp,GBR),R0 */ |
| 1230 | 1234 |
{
|
| 1231 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1235 |
TCGv addr = tcg_temp_new(); |
|
| 1232 | 1236 |
tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); |
| 1233 | 1237 |
tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx); |
| 1234 | 1238 |
tcg_temp_free(addr); |
| ... | ... | |
| 1236 | 1240 |
return; |
| 1237 | 1241 |
case 0xc000: /* mov.b R0,@(disp,GBR) */ |
| 1238 | 1242 |
{
|
| 1239 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1243 |
TCGv addr = tcg_temp_new(); |
|
| 1240 | 1244 |
tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
| 1241 | 1245 |
tcg_gen_qemu_st8(REG(0), addr, ctx->memidx); |
| 1242 | 1246 |
tcg_temp_free(addr); |
| ... | ... | |
| 1244 | 1248 |
return; |
| 1245 | 1249 |
case 0xc100: /* mov.w R0,@(disp,GBR) */ |
| 1246 | 1250 |
{
|
| 1247 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1251 |
TCGv addr = tcg_temp_new(); |
|
| 1248 | 1252 |
tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); |
| 1249 | 1253 |
tcg_gen_qemu_st16(REG(0), addr, ctx->memidx); |
| 1250 | 1254 |
tcg_temp_free(addr); |
| ... | ... | |
| 1252 | 1256 |
return; |
| 1253 | 1257 |
case 0xc200: /* mov.l R0,@(disp,GBR) */ |
| 1254 | 1258 |
{
|
| 1255 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1259 |
TCGv addr = tcg_temp_new(); |
|
| 1256 | 1260 |
tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); |
| 1257 | 1261 |
tcg_gen_qemu_st32(REG(0), addr, ctx->memidx); |
| 1258 | 1262 |
tcg_temp_free(addr); |
| ... | ... | |
| 1260 | 1264 |
return; |
| 1261 | 1265 |
case 0x8000: /* mov.b R0,@(disp,Rn) */ |
| 1262 | 1266 |
{
|
| 1263 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1267 |
TCGv addr = tcg_temp_new(); |
|
| 1264 | 1268 |
tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
| 1265 | 1269 |
tcg_gen_qemu_st8(REG(0), addr, ctx->memidx); |
| 1266 | 1270 |
tcg_temp_free(addr); |
| ... | ... | |
| 1268 | 1272 |
return; |
| 1269 | 1273 |
case 0x8100: /* mov.w R0,@(disp,Rn) */ |
| 1270 | 1274 |
{
|
| 1271 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1275 |
TCGv addr = tcg_temp_new(); |
|
| 1272 | 1276 |
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); |
| 1273 | 1277 |
tcg_gen_qemu_st16(REG(0), addr, ctx->memidx); |
| 1274 | 1278 |
tcg_temp_free(addr); |
| ... | ... | |
| 1276 | 1280 |
return; |
| 1277 | 1281 |
case 0x8400: /* mov.b @(disp,Rn),R0 */ |
| 1278 | 1282 |
{
|
| 1279 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1283 |
TCGv addr = tcg_temp_new(); |
|
| 1280 | 1284 |
tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
| 1281 | 1285 |
tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx); |
| 1282 | 1286 |
tcg_temp_free(addr); |
| ... | ... | |
| 1284 | 1288 |
return; |
| 1285 | 1289 |
case 0x8500: /* mov.w @(disp,Rn),R0 */ |
| 1286 | 1290 |
{
|
| 1287 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1291 |
TCGv addr = tcg_temp_new(); |
|
| 1288 | 1292 |
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); |
| 1289 | 1293 |
tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx); |
| 1290 | 1294 |
tcg_temp_free(addr); |
| ... | ... | |
| 1299 | 1303 |
case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
| 1300 | 1304 |
{
|
| 1301 | 1305 |
TCGv addr, val; |
| 1302 |
addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1306 |
addr = tcg_temp_new(); |
|
| 1303 | 1307 |
tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
| 1304 |
val = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1308 |
val = tcg_temp_new(); |
|
| 1305 | 1309 |
tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
| 1306 | 1310 |
tcg_gen_ori_i32(val, val, B7_0); |
| 1307 | 1311 |
tcg_gen_qemu_st8(val, addr, ctx->memidx); |
| ... | ... | |
| 1315 | 1319 |
CHECK_NOT_DELAY_SLOT |
| 1316 | 1320 |
tcg_gen_movi_i32(cpu_pc, ctx->pc); |
| 1317 | 1321 |
imm = tcg_const_i32(B7_0); |
| 1318 |
tcg_gen_helper_0_1(helper_trapa, imm);
|
|
| 1322 |
gen_helper_trapa(imm);
|
|
| 1319 | 1323 |
tcg_temp_free(imm); |
| 1320 | 1324 |
ctx->bstate = BS_BRANCH; |
| 1321 | 1325 |
} |
| 1322 | 1326 |
return; |
| 1323 | 1327 |
case 0xc800: /* tst #imm,R0 */ |
| 1324 | 1328 |
{
|
| 1325 |
TCGv val = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1329 |
TCGv val = tcg_temp_new(); |
|
| 1326 | 1330 |
tcg_gen_andi_i32(val, REG(0), B7_0); |
| 1327 | 1331 |
gen_cmp_imm(TCG_COND_EQ, val, 0); |
| 1328 | 1332 |
tcg_temp_free(val); |
| ... | ... | |
| 1330 | 1334 |
return; |
| 1331 | 1335 |
case 0xcc00: /* tst.b #imm,@(R0,GBR) */ |
| 1332 | 1336 |
{
|
| 1333 |
TCGv val = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1337 |
TCGv val = tcg_temp_new(); |
|
| 1334 | 1338 |
tcg_gen_add_i32(val, REG(0), cpu_gbr); |
| 1335 | 1339 |
tcg_gen_qemu_ld8u(val, val, ctx->memidx); |
| 1336 | 1340 |
tcg_gen_andi_i32(val, val, B7_0); |
| ... | ... | |
| 1344 | 1348 |
case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
| 1345 | 1349 |
{
|
| 1346 | 1350 |
TCGv addr, val; |
| 1347 |
addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1351 |
addr = tcg_temp_new(); |
|
| 1348 | 1352 |
tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
| 1349 |
val = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1353 |
val = tcg_temp_new(); |
|
| 1350 | 1354 |
tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
| 1351 | 1355 |
tcg_gen_xori_i32(val, val, B7_0); |
| 1352 | 1356 |
tcg_gen_qemu_st8(val, addr, ctx->memidx); |
| ... | ... | |
| 1373 | 1377 |
case 0x4083: /* stc.l Rm_BANK,@-Rn */ |
| 1374 | 1378 |
CHECK_PRIVILEGED |
| 1375 | 1379 |
{
|
| 1376 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1380 |
TCGv addr = tcg_temp_new(); |
|
| 1377 | 1381 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1378 | 1382 |
tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx); |
| 1379 | 1383 |
tcg_temp_free(addr); |
| ... | ... | |
| 1427 | 1431 |
case 0x4007: /* ldc.l @Rm+,SR */ |
| 1428 | 1432 |
CHECK_PRIVILEGED |
| 1429 | 1433 |
{
|
| 1430 |
TCGv val = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1434 |
TCGv val = tcg_temp_new(); |
|
| 1431 | 1435 |
tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx); |
| 1432 | 1436 |
tcg_gen_andi_i32(cpu_sr, val, 0x700083f3); |
| 1433 | 1437 |
tcg_temp_free(val); |
| ... | ... | |
| 1442 | 1446 |
case 0x4003: /* stc SR,@-Rn */ |
| 1443 | 1447 |
CHECK_PRIVILEGED |
| 1444 | 1448 |
{
|
| 1445 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1449 |
TCGv addr = tcg_temp_new(); |
|
| 1446 | 1450 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1447 | 1451 |
tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx); |
| 1448 | 1452 |
tcg_temp_free(addr); |
| ... | ... | |
| 1466 | 1470 |
case stpnum: \ |
| 1467 | 1471 |
prechk \ |
| 1468 | 1472 |
{ \
|
| 1469 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32); \
|
|
| 1473 |
TCGv addr = tcg_temp_new(); \ |
|
| 1470 | 1474 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); \ |
| 1471 | 1475 |
tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \ |
| 1472 | 1476 |
tcg_temp_free(addr); \ |
| ... | ... | |
| 1483 | 1487 |
LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {})
|
| 1484 | 1488 |
LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {})
|
| 1485 | 1489 |
case 0x406a: /* lds Rm,FPSCR */ |
| 1486 |
tcg_gen_helper_0_1(helper_ld_fpscr, REG(B11_8));
|
|
| 1490 |
gen_helper_ld_fpscr(REG(B11_8));
|
|
| 1487 | 1491 |
ctx->bstate = BS_STOP; |
| 1488 | 1492 |
return; |
| 1489 | 1493 |
case 0x4066: /* lds.l @Rm+,FPSCR */ |
| 1490 | 1494 |
{
|
| 1491 |
TCGv addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1495 |
TCGv addr = tcg_temp_new(); |
|
| 1492 | 1496 |
tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx); |
| 1493 | 1497 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); |
| 1494 |
tcg_gen_helper_0_1(helper_ld_fpscr, addr);
|
|
| 1498 |
gen_helper_ld_fpscr(addr);
|
|
| 1495 | 1499 |
tcg_temp_free(addr); |
| 1496 | 1500 |
ctx->bstate = BS_STOP; |
| 1497 | 1501 |
} |
| ... | ... | |
| 1502 | 1506 |
case 0x4062: /* sts FPSCR,@-Rn */ |
| 1503 | 1507 |
{
|
| 1504 | 1508 |
TCGv addr, val; |
| 1505 |
val = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1509 |
val = tcg_temp_new(); |
|
| 1506 | 1510 |
tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff); |
| 1507 |
addr = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1511 |
addr = tcg_temp_new(); |
|
| 1508 | 1512 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1509 | 1513 |
tcg_gen_qemu_st32(val, addr, ctx->memidx); |
| 1510 | 1514 |
tcg_temp_free(addr); |
| ... | ... | |
| 1531 | 1535 |
return; |
| 1532 | 1536 |
case 0x0093: /* ocbi @Rn */ |
| 1533 | 1537 |
{
|
| 1534 |
TCGv dummy = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1538 |
TCGv dummy = tcg_temp_new(); |
|
| 1535 | 1539 |
tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
| 1536 | 1540 |
tcg_temp_free(dummy); |
| 1537 | 1541 |
} |
| 1538 | 1542 |
return; |
| 1539 | 1543 |
case 0x00a3: /* ocbp @Rn */ |
| 1540 | 1544 |
{
|
| 1541 |
TCGv dummy = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1545 |
TCGv dummy = tcg_temp_new(); |
|
| 1542 | 1546 |
tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
| 1543 | 1547 |
tcg_temp_free(dummy); |
| 1544 | 1548 |
} |
| 1545 | 1549 |
return; |
| 1546 | 1550 |
case 0x00b3: /* ocbwb @Rn */ |
| 1547 | 1551 |
{
|
| 1548 |
TCGv dummy = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1552 |
TCGv dummy = tcg_temp_new(); |
|
| 1549 | 1553 |
tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
| 1550 | 1554 |
tcg_temp_free(dummy); |
| 1551 | 1555 |
} |
| ... | ... | |
| 1554 | 1558 |
return; |
| 1555 | 1559 |
case 0x4024: /* rotcl Rn */ |
| 1556 | 1560 |
{
|
| 1557 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1561 |
TCGv tmp = tcg_temp_new(); |
|
| 1558 | 1562 |
tcg_gen_mov_i32(tmp, cpu_sr); |
| 1559 | 1563 |
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
| 1560 | 1564 |
tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); |
| ... | ... | |
| 1564 | 1568 |
return; |
| 1565 | 1569 |
case 0x4025: /* rotcr Rn */ |
| 1566 | 1570 |
{
|
| 1567 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1571 |
TCGv tmp = tcg_temp_new(); |
|
| 1568 | 1572 |
tcg_gen_mov_i32(tmp, cpu_sr); |
| 1569 | 1573 |
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
| 1570 | 1574 |
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); |
| ... | ... | |
| 1629 | 1633 |
return; |
| 1630 | 1634 |
case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ |
| 1631 | 1635 |
{
|
| 1632 |
TCGv fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1636 |
TCGv fp = tcg_temp_new(); |
|
| 1633 | 1637 |
tcg_gen_mov_i32(fp, cpu_fpul); |
| 1634 | 1638 |
gen_store_fpr32(fp, FREG(B11_8)); |
| 1635 | 1639 |
tcg_temp_free(fp); |
| ... | ... | |
| 1637 | 1641 |
return; |
| 1638 | 1642 |
case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ |
| 1639 | 1643 |
{
|
| 1640 |
TCGv fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1644 |
TCGv fp = tcg_temp_new(); |
|
| 1641 | 1645 |
gen_load_fpr32(fp, FREG(B11_8)); |
| 1642 | 1646 |
tcg_gen_mov_i32(cpu_fpul, fp); |
| 1643 | 1647 |
tcg_temp_free(fp); |
| ... | ... | |
| 1645 | 1649 |
return; |
| 1646 | 1650 |
case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ |
| 1647 | 1651 |
if (ctx->fpscr & FPSCR_PR) {
|
| 1648 |
TCGv fp; |
|
| 1652 |
TCGv_i64 fp;
|
|
| 1649 | 1653 |
if (ctx->opcode & 0x0100) |
| 1650 | 1654 |
break; /* illegal instruction */ |
| 1651 |
fp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1652 |
tcg_gen_helper_1_1(helper_float_DT, fp, cpu_fpul);
|
|
| 1655 |
fp = tcg_temp_new_i64();
|
|
| 1656 |
gen_helper_float_DT(fp, cpu_fpul);
|
|
| 1653 | 1657 |
gen_store_fpr64(fp, DREG(B11_8)); |
| 1654 |
tcg_temp_free(fp); |
|
| 1658 |
tcg_temp_free_i64(fp);
|
|
| 1655 | 1659 |
} |
| 1656 | 1660 |
else {
|
| 1657 |
TCGv fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1658 |
tcg_gen_helper_1_1(helper_float_FT, fp, cpu_fpul);
|
|
| 1661 |
TCGv_i32 fp = tcg_temp_new_i32();
|
|
| 1662 |
gen_helper_float_FT(fp, cpu_fpul);
|
|
| 1659 | 1663 |
gen_store_fpr32(fp, FREG(B11_8)); |
| 1660 |
tcg_temp_free(fp); |
|
| 1664 |
tcg_temp_free_i32(fp);
|
|
| 1661 | 1665 |
} |
| 1662 | 1666 |
return; |
| 1663 | 1667 |
case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
| 1664 | 1668 |
if (ctx->fpscr & FPSCR_PR) {
|
| 1665 |
TCGv fp; |
|
| 1669 |
TCGv_i64 fp;
|
|
| 1666 | 1670 |
if (ctx->opcode & 0x0100) |
| 1667 | 1671 |
break; /* illegal instruction */ |
| 1668 |
fp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1672 |
fp = tcg_temp_new_i64();
|
|
| 1669 | 1673 |
gen_load_fpr64(fp, DREG(B11_8)); |
| 1670 |
tcg_gen_helper_1_1(helper_ftrc_DT, cpu_fpul, fp);
|
|
| 1671 |
tcg_temp_free(fp); |
|
| 1674 |
gen_helper_ftrc_DT(cpu_fpul, fp);
|
|
| 1675 |
tcg_temp_free_i64(fp);
|
|
| 1672 | 1676 |
} |
| 1673 | 1677 |
else {
|
| 1674 |
TCGv fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1678 |
TCGv_i32 fp = tcg_temp_new_i32();
|
|
| 1675 | 1679 |
gen_load_fpr32(fp, FREG(B11_8)); |
| 1676 |
tcg_gen_helper_1_1(helper_ftrc_FT, cpu_fpul, fp);
|
|
| 1677 |
tcg_temp_free(fp); |
|
| 1680 |
gen_helper_ftrc_FT(cpu_fpul, fp);
|
|
| 1681 |
tcg_temp_free_i32(fp);
|
|
| 1678 | 1682 |
} |
| 1679 | 1683 |
return; |
| 1680 | 1684 |
case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ |
| 1681 | 1685 |
{
|
| 1682 |
TCGv fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1686 |
TCGv_i32 fp = tcg_temp_new_i32();
|
|
| 1683 | 1687 |
gen_load_fpr32(fp, FREG(B11_8)); |
| 1684 |
tcg_gen_helper_1_1(helper_fneg_T, fp, fp);
|
|
| 1688 |
gen_helper_fneg_T(fp, fp);
|
|
| 1685 | 1689 |
gen_store_fpr32(fp, FREG(B11_8)); |
| 1686 |
tcg_temp_free(fp); |
|
| 1690 |
tcg_temp_free_i32(fp);
|
|
| 1687 | 1691 |
} |
| 1688 | 1692 |
return; |
| 1689 | 1693 |
case 0xf05d: /* fabs FRn/DRn */ |
| 1690 | 1694 |
if (ctx->fpscr & FPSCR_PR) {
|
| 1691 | 1695 |
if (ctx->opcode & 0x0100) |
| 1692 | 1696 |
break; /* illegal instruction */ |
| 1693 |
TCGv fp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1697 |
TCGv_i64 fp = tcg_temp_new_i64();
|
|
| 1694 | 1698 |
gen_load_fpr64(fp, DREG(B11_8)); |
| 1695 |
tcg_gen_helper_1_1(helper_fabs_DT, fp, fp);
|
|
| 1699 |
gen_helper_fabs_DT(fp, fp);
|
|
| 1696 | 1700 |
gen_store_fpr64(fp, DREG(B11_8)); |
| 1697 |
tcg_temp_free(fp); |
|
| 1701 |
tcg_temp_free_i64(fp);
|
|
| 1698 | 1702 |
} else {
|
| 1699 |
TCGv fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1703 |
TCGv_i32 fp = tcg_temp_new_i32();
|
|
| 1700 | 1704 |
gen_load_fpr32(fp, FREG(B11_8)); |
| 1701 |
tcg_gen_helper_1_1(helper_fabs_FT, fp, fp);
|
|
| 1705 |
gen_helper_fabs_FT(fp, fp);
|
|
| 1702 | 1706 |
gen_store_fpr32(fp, FREG(B11_8)); |
| 1703 |
tcg_temp_free(fp); |
|
| 1707 |
tcg_temp_free_i32(fp);
|
|
| 1704 | 1708 |
} |
| 1705 | 1709 |
return; |
| 1706 | 1710 |
case 0xf06d: /* fsqrt FRn */ |
| 1707 | 1711 |
if (ctx->fpscr & FPSCR_PR) {
|
| 1708 | 1712 |
if (ctx->opcode & 0x0100) |
| 1709 | 1713 |
break; /* illegal instruction */ |
| 1710 |
TCGv fp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1714 |
TCGv_i64 fp = tcg_temp_new_i64();
|
|
| 1711 | 1715 |
gen_load_fpr64(fp, DREG(B11_8)); |
| 1712 |
tcg_gen_helper_1_1(helper_fsqrt_DT, fp, fp);
|
|
| 1716 |
gen_helper_fsqrt_DT(fp, fp);
|
|
| 1713 | 1717 |
gen_store_fpr64(fp, DREG(B11_8)); |
| 1714 |
tcg_temp_free(fp); |
|
| 1718 |
tcg_temp_free_i64(fp);
|
|
| 1715 | 1719 |
} else {
|
| 1716 |
TCGv fp = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1720 |
TCGv_i32 fp = tcg_temp_new_i32();
|
|
| 1717 | 1721 |
gen_load_fpr32(fp, FREG(B11_8)); |
| 1718 |
tcg_gen_helper_1_1(helper_fsqrt_FT, fp, fp);
|
|
| 1722 |
gen_helper_fsqrt_FT(fp, fp);
|
|
| 1719 | 1723 |
gen_store_fpr32(fp, FREG(B11_8)); |
| 1720 |
tcg_temp_free(fp); |
|
| 1724 |
tcg_temp_free_i32(fp);
|
|
| 1721 | 1725 |
} |
| 1722 | 1726 |
return; |
| 1723 | 1727 |
case 0xf07d: /* fsrra FRn */ |
| 1724 | 1728 |
break; |
| 1725 | 1729 |
case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ |
| 1726 | 1730 |
if (!(ctx->fpscr & FPSCR_PR)) {
|
| 1727 |
TCGv val = tcg_const_i32(0); |
|
| 1731 |
TCGv_i32 val = tcg_const_i32(0);
|
|
| 1728 | 1732 |
gen_load_fpr32(val, FREG(B11_8)); |
| 1729 |
tcg_temp_free(val); |
|
| 1733 |
tcg_temp_free_i32(val);
|
|
| 1730 | 1734 |
return; |
| 1731 | 1735 |
} |
| 1732 | 1736 |
break; |
| 1733 | 1737 |
case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ |
| 1734 | 1738 |
if (!(ctx->fpscr & FPSCR_PR)) {
|
| 1735 |
TCGv val = tcg_const_i32(0x3f800000); |
|
| 1739 |
TCGv_i32 val = tcg_const_i32(0x3f800000);
|
|
| 1736 | 1740 |
gen_load_fpr32(val, FREG(B11_8)); |
| 1737 |
tcg_temp_free(val); |
|
| 1741 |
tcg_temp_free_i32(val);
|
|
| 1738 | 1742 |
return; |
| 1739 | 1743 |
} |
| 1740 | 1744 |
break; |
| 1741 | 1745 |
case 0xf0ad: /* fcnvsd FPUL,DRn */ |
| 1742 | 1746 |
{
|
| 1743 |
TCGv fp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1744 |
tcg_gen_helper_1_1(helper_fcnvsd_FT_DT, fp, cpu_fpul);
|
|
| 1747 |
TCGv_i64 fp = tcg_temp_new_i64();
|
|
| 1748 |
gen_helper_fcnvsd_FT_DT(fp, cpu_fpul);
|
|
| 1745 | 1749 |
gen_store_fpr64(fp, DREG(B11_8)); |
| 1746 |
tcg_temp_free(fp); |
|
| 1750 |
tcg_temp_free_i64(fp);
|
|
| 1747 | 1751 |
} |
| 1748 | 1752 |
return; |
| 1749 | 1753 |
case 0xf0bd: /* fcnvds DRn,FPUL */ |
| 1750 | 1754 |
{
|
| 1751 |
TCGv fp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 1755 |
TCGv_i64 fp = tcg_temp_new_i64();
|
|
| 1752 | 1756 |
gen_load_fpr64(fp, DREG(B11_8)); |
| 1753 |
tcg_gen_helper_1_1(helper_fcnvds_DT_FT, cpu_fpul, fp);
|
|
| 1754 |
tcg_temp_free(fp); |
|
| 1757 |
gen_helper_fcnvds_DT_FT(cpu_fpul, fp);
|
|
| 1758 |
tcg_temp_free_i64(fp);
|
|
| 1755 | 1759 |
} |
| 1756 | 1760 |
return; |
| 1757 | 1761 |
} |
| 1758 | 1762 |
|
| 1759 | 1763 |
fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", |
| 1760 | 1764 |
ctx->opcode, ctx->pc); |
| 1761 |
tcg_gen_helper_0_0(helper_raise_illegal_instruction);
|
|
| 1765 |
gen_helper_raise_illegal_instruction();
|
|
| 1762 | 1766 |
ctx->bstate = BS_EXCP; |
| 1763 | 1767 |
} |
| 1764 | 1768 |
|
| ... | ... | |
| 1837 | 1841 |
if (ctx.pc == env->breakpoints[i]) {
|
| 1838 | 1842 |
/* We have hit a breakpoint - make sure PC is up-to-date */ |
| 1839 | 1843 |
tcg_gen_movi_i32(cpu_pc, ctx.pc); |
| 1840 |
tcg_gen_helper_0_0(helper_debug);
|
|
| 1844 |
gen_helper_debug();
|
|
| 1841 | 1845 |
ctx.bstate = BS_EXCP; |
| 1842 | 1846 |
break; |
| 1843 | 1847 |
} |
| ... | ... | |
| 1879 | 1883 |
gen_io_end(); |
| 1880 | 1884 |
if (env->singlestep_enabled) {
|
| 1881 | 1885 |
tcg_gen_movi_i32(cpu_pc, ctx.pc); |
| 1882 |
tcg_gen_helper_0_0(helper_debug);
|
|
| 1886 |
gen_helper_debug();
|
|
| 1883 | 1887 |
} else {
|
| 1884 | 1888 |
switch (ctx.bstate) {
|
| 1885 | 1889 |
case BS_STOP: |
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