Revision a7812ae4 target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 31 | 31 |
#include "helper.h" |
| 32 | 32 |
#include "tcg-op.h" |
| 33 | 33 |
|
| 34 |
#define GEN_HELPER 1 |
|
| 35 |
#include "helper.h" |
|
| 36 |
|
|
| 34 | 37 |
#define DEBUG_DISAS |
| 35 | 38 |
|
| 36 | 39 |
#define DYNAMIC_PC 1 /* dynamic pc value */ |
| ... | ... | |
| 38 | 41 |
according to jump_pc[T2] */ |
| 39 | 42 |
|
| 40 | 43 |
/* global register indexes */ |
| 41 |
static TCGv cpu_env, cpu_regwptr; |
|
| 44 |
static TCGv_ptr cpu_env, cpu_regwptr;
|
|
| 42 | 45 |
static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; |
| 43 |
static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
|
| 46 |
static TCGv_i32 cpu_psr; |
|
| 47 |
static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
|
| 44 | 48 |
static TCGv cpu_y; |
| 45 | 49 |
#ifndef CONFIG_USER_ONLY |
| 46 | 50 |
static TCGv cpu_tbr; |
| 47 | 51 |
#endif |
| 48 | 52 |
static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val; |
| 49 | 53 |
#ifdef TARGET_SPARC64 |
| 50 |
static TCGv cpu_xcc, cpu_asi, cpu_fprs, cpu_gsr; |
|
| 54 |
static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs; |
|
| 55 |
static TCGv cpu_gsr; |
|
| 51 | 56 |
static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr; |
| 52 |
static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver, cpu_softint; |
|
| 57 |
static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; |
|
| 58 |
static TCGv_i32 cpu_softint; |
|
| 53 | 59 |
#else |
| 54 | 60 |
static TCGv cpu_wim; |
| 55 | 61 |
#endif |
| 56 | 62 |
/* local register indexes (only used inside old micro ops) */ |
| 57 |
static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64; |
|
| 63 |
static TCGv cpu_tmp0; |
|
| 64 |
static TCGv_i32 cpu_tmp32; |
|
| 65 |
static TCGv_i64 cpu_tmp64; |
|
| 58 | 66 |
/* Floating point registers */ |
| 59 |
static TCGv cpu_fpr[TARGET_FPREGS]; |
|
| 67 |
static TCGv_i32 cpu_fpr[TARGET_FPREGS];
|
|
| 60 | 68 |
|
| 61 | 69 |
#include "gen-icount.h" |
| 62 | 70 |
|
| ... | ... | |
| 239 | 247 |
} |
| 240 | 248 |
|
| 241 | 249 |
// XXX suboptimal |
| 242 |
static inline void gen_mov_reg_N(TCGv reg, TCGv src) |
|
| 250 |
static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
|
|
| 243 | 251 |
{
|
| 244 | 252 |
tcg_gen_extu_i32_tl(reg, src); |
| 245 | 253 |
tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); |
| 246 | 254 |
tcg_gen_andi_tl(reg, reg, 0x1); |
| 247 | 255 |
} |
| 248 | 256 |
|
| 249 |
static inline void gen_mov_reg_Z(TCGv reg, TCGv src) |
|
| 257 |
static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
|
|
| 250 | 258 |
{
|
| 251 | 259 |
tcg_gen_extu_i32_tl(reg, src); |
| 252 | 260 |
tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); |
| 253 | 261 |
tcg_gen_andi_tl(reg, reg, 0x1); |
| 254 | 262 |
} |
| 255 | 263 |
|
| 256 |
static inline void gen_mov_reg_V(TCGv reg, TCGv src) |
|
| 264 |
static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
|
|
| 257 | 265 |
{
|
| 258 | 266 |
tcg_gen_extu_i32_tl(reg, src); |
| 259 | 267 |
tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); |
| 260 | 268 |
tcg_gen_andi_tl(reg, reg, 0x1); |
| 261 | 269 |
} |
| 262 | 270 |
|
| 263 |
static inline void gen_mov_reg_C(TCGv reg, TCGv src) |
|
| 271 |
static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
|
|
| 264 | 272 |
{
|
| 265 | 273 |
tcg_gen_extu_i32_tl(reg, src); |
| 266 | 274 |
tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); |
| ... | ... | |
| 292 | 300 |
|
| 293 | 301 |
l1 = gen_new_label(); |
| 294 | 302 |
l2 = gen_new_label(); |
| 295 |
r_temp = tcg_temp_new(TCG_TYPE_TL);
|
|
| 303 |
r_temp = tcg_temp_new(); |
|
| 296 | 304 |
tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL); |
| 297 | 305 |
tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1); |
| 298 | 306 |
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); |
| ... | ... | |
| 330 | 338 |
int l1; |
| 331 | 339 |
|
| 332 | 340 |
l1 = gen_new_label(); |
| 333 |
r_temp1 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 334 |
r_temp2 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 341 |
r_temp1 = tcg_temp_new(); |
|
| 342 |
r_temp2 = tcg_temp_new(); |
|
| 335 | 343 |
tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL); |
| 336 | 344 |
tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL); |
| 337 | 345 |
tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); |
| ... | ... | |
| 361 | 369 |
{
|
| 362 | 370 |
TCGv r_temp; |
| 363 | 371 |
|
| 364 |
r_temp = tcg_temp_new(TCG_TYPE_TL);
|
|
| 372 |
r_temp = tcg_temp_new(); |
|
| 365 | 373 |
tcg_gen_xor_tl(r_temp, src1, src2); |
| 366 | 374 |
tcg_gen_not_tl(r_temp, r_temp); |
| 367 | 375 |
tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
| ... | ... | |
| 378 | 386 |
{
|
| 379 | 387 |
TCGv r_temp; |
| 380 | 388 |
|
| 381 |
r_temp = tcg_temp_new(TCG_TYPE_TL);
|
|
| 389 |
r_temp = tcg_temp_new(); |
|
| 382 | 390 |
tcg_gen_xor_tl(r_temp, src1, src2); |
| 383 | 391 |
tcg_gen_not_tl(r_temp, r_temp); |
| 384 | 392 |
tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
| ... | ... | |
| 393 | 401 |
|
| 394 | 402 |
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
| 395 | 403 |
{
|
| 396 |
TCGv r_temp, r_const; |
|
| 404 |
TCGv r_temp; |
|
| 405 |
TCGv_i32 r_const; |
|
| 397 | 406 |
int l1; |
| 398 | 407 |
|
| 399 | 408 |
l1 = gen_new_label(); |
| 400 | 409 |
|
| 401 |
r_temp = tcg_temp_new(TCG_TYPE_TL);
|
|
| 410 |
r_temp = tcg_temp_new(); |
|
| 402 | 411 |
tcg_gen_xor_tl(r_temp, src1, src2); |
| 403 | 412 |
tcg_gen_not_tl(r_temp, r_temp); |
| 404 | 413 |
tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
| ... | ... | |
| 406 | 415 |
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
| 407 | 416 |
tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); |
| 408 | 417 |
r_const = tcg_const_i32(TT_TOVF); |
| 409 |
tcg_gen_helper_0_1(raise_exception, r_const);
|
|
| 410 |
tcg_temp_free(r_const); |
|
| 418 |
gen_helper_raise_exception(r_const);
|
|
| 419 |
tcg_temp_free_i32(r_const);
|
|
| 411 | 420 |
gen_set_label(l1); |
| 412 | 421 |
tcg_temp_free(r_temp); |
| 413 | 422 |
} |
| ... | ... | |
| 427 | 436 |
static inline void gen_tag_tv(TCGv src1, TCGv src2) |
| 428 | 437 |
{
|
| 429 | 438 |
int l1; |
| 430 |
TCGv r_const; |
|
| 439 |
TCGv_i32 r_const;
|
|
| 431 | 440 |
|
| 432 | 441 |
l1 = gen_new_label(); |
| 433 | 442 |
tcg_gen_or_tl(cpu_tmp0, src1, src2); |
| 434 | 443 |
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3); |
| 435 | 444 |
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); |
| 436 | 445 |
r_const = tcg_const_i32(TT_TOVF); |
| 437 |
tcg_gen_helper_0_1(raise_exception, r_const);
|
|
| 438 |
tcg_temp_free(r_const); |
|
| 446 |
gen_helper_raise_exception(r_const);
|
|
| 447 |
tcg_temp_free_i32(r_const);
|
|
| 439 | 448 |
gen_set_label(l1); |
| 440 | 449 |
} |
| 441 | 450 |
|
| ... | ... | |
| 529 | 538 |
int l1; |
| 530 | 539 |
|
| 531 | 540 |
l1 = gen_new_label(); |
| 532 |
r_temp1 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 533 |
r_temp2 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 541 |
r_temp1 = tcg_temp_new(); |
|
| 542 |
r_temp2 = tcg_temp_new(); |
|
| 534 | 543 |
tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL); |
| 535 | 544 |
tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL); |
| 536 | 545 |
tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); |
| ... | ... | |
| 560 | 569 |
{
|
| 561 | 570 |
TCGv r_temp; |
| 562 | 571 |
|
| 563 |
r_temp = tcg_temp_new(TCG_TYPE_TL);
|
|
| 572 |
r_temp = tcg_temp_new(); |
|
| 564 | 573 |
tcg_gen_xor_tl(r_temp, src1, src2); |
| 565 | 574 |
tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
| 566 | 575 |
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
| ... | ... | |
| 576 | 585 |
{
|
| 577 | 586 |
TCGv r_temp; |
| 578 | 587 |
|
| 579 |
r_temp = tcg_temp_new(TCG_TYPE_TL);
|
|
| 588 |
r_temp = tcg_temp_new(); |
|
| 580 | 589 |
tcg_gen_xor_tl(r_temp, src1, src2); |
| 581 | 590 |
tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
| 582 | 591 |
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
| ... | ... | |
| 590 | 599 |
|
| 591 | 600 |
static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
| 592 | 601 |
{
|
| 593 |
TCGv r_temp, r_const; |
|
| 602 |
TCGv r_temp; |
|
| 603 |
TCGv_i32 r_const; |
|
| 594 | 604 |
int l1; |
| 595 | 605 |
|
| 596 | 606 |
l1 = gen_new_label(); |
| 597 | 607 |
|
| 598 |
r_temp = tcg_temp_new(TCG_TYPE_TL);
|
|
| 608 |
r_temp = tcg_temp_new(); |
|
| 599 | 609 |
tcg_gen_xor_tl(r_temp, src1, src2); |
| 600 | 610 |
tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
| 601 | 611 |
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
| 602 | 612 |
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
| 603 | 613 |
tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); |
| 604 | 614 |
r_const = tcg_const_i32(TT_TOVF); |
| 605 |
tcg_gen_helper_0_1(raise_exception, r_const);
|
|
| 606 |
tcg_temp_free(r_const); |
|
| 615 |
gen_helper_raise_exception(r_const);
|
|
| 616 |
tcg_temp_free_i32(r_const);
|
|
| 607 | 617 |
gen_set_label(l1); |
| 608 | 618 |
tcg_temp_free(r_temp); |
| 609 | 619 |
} |
| ... | ... | |
| 694 | 704 |
int l1; |
| 695 | 705 |
|
| 696 | 706 |
l1 = gen_new_label(); |
| 697 |
r_temp = tcg_temp_new(TCG_TYPE_TL);
|
|
| 707 |
r_temp = tcg_temp_new(); |
|
| 698 | 708 |
|
| 699 | 709 |
/* old op: |
| 700 | 710 |
if (!(env->y & 1)) |
| ... | ... | |
| 740 | 750 |
|
| 741 | 751 |
static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
| 742 | 752 |
{
|
| 743 |
TCGv r_temp, r_temp2; |
|
| 753 |
TCGv_i64 r_temp, r_temp2;
|
|
| 744 | 754 |
|
| 745 |
r_temp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 746 |
r_temp2 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 755 |
r_temp = tcg_temp_new_i64();
|
|
| 756 |
r_temp2 = tcg_temp_new_i64();
|
|
| 747 | 757 |
|
| 748 | 758 |
tcg_gen_extu_tl_i64(r_temp, src2); |
| 749 | 759 |
tcg_gen_extu_tl_i64(r_temp2, src1); |
| ... | ... | |
| 751 | 761 |
|
| 752 | 762 |
tcg_gen_shri_i64(r_temp, r_temp2, 32); |
| 753 | 763 |
tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
| 754 |
tcg_temp_free(r_temp); |
|
| 764 |
tcg_temp_free_i64(r_temp);
|
|
| 755 | 765 |
tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff); |
| 756 | 766 |
#ifdef TARGET_SPARC64 |
| 757 | 767 |
tcg_gen_mov_i64(dst, r_temp2); |
| 758 | 768 |
#else |
| 759 | 769 |
tcg_gen_trunc_i64_tl(dst, r_temp2); |
| 760 | 770 |
#endif |
| 761 |
tcg_temp_free(r_temp2); |
|
| 771 |
tcg_temp_free_i64(r_temp2);
|
|
| 762 | 772 |
} |
| 763 | 773 |
|
| 764 | 774 |
static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) |
| 765 | 775 |
{
|
| 766 |
TCGv r_temp, r_temp2; |
|
| 776 |
TCGv_i64 r_temp, r_temp2;
|
|
| 767 | 777 |
|
| 768 |
r_temp = tcg_temp_new(TCG_TYPE_I64);
|
|
| 769 |
r_temp2 = tcg_temp_new(TCG_TYPE_I64);
|
|
| 778 |
r_temp = tcg_temp_new_i64();
|
|
| 779 |
r_temp2 = tcg_temp_new_i64();
|
|
| 770 | 780 |
|
| 771 | 781 |
tcg_gen_ext_tl_i64(r_temp, src2); |
| 772 | 782 |
tcg_gen_ext_tl_i64(r_temp2, src1); |
| ... | ... | |
| 774 | 784 |
|
| 775 | 785 |
tcg_gen_shri_i64(r_temp, r_temp2, 32); |
| 776 | 786 |
tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
| 777 |
tcg_temp_free(r_temp); |
|
| 787 |
tcg_temp_free_i64(r_temp);
|
|
| 778 | 788 |
tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff); |
| 779 | 789 |
#ifdef TARGET_SPARC64 |
| 780 | 790 |
tcg_gen_mov_i64(dst, r_temp2); |
| 781 | 791 |
#else |
| 782 | 792 |
tcg_gen_trunc_i64_tl(dst, r_temp2); |
| 783 | 793 |
#endif |
| 784 |
tcg_temp_free(r_temp2); |
|
| 794 |
tcg_temp_free_i64(r_temp2);
|
|
| 785 | 795 |
} |
| 786 | 796 |
|
| 787 | 797 |
#ifdef TARGET_SPARC64 |
| 788 | 798 |
static inline void gen_trap_ifdivzero_tl(TCGv divisor) |
| 789 | 799 |
{
|
| 790 |
TCGv r_const; |
|
| 800 |
TCGv_i32 r_const;
|
|
| 791 | 801 |
int l1; |
| 792 | 802 |
|
| 793 | 803 |
l1 = gen_new_label(); |
| 794 | 804 |
tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1); |
| 795 | 805 |
r_const = tcg_const_i32(TT_DIV_ZERO); |
| 796 |
tcg_gen_helper_0_1(raise_exception, r_const);
|
|
| 797 |
tcg_temp_free(r_const); |
|
| 806 |
gen_helper_raise_exception(r_const);
|
|
| 807 |
tcg_temp_free_i32(r_const);
|
|
| 798 | 808 |
gen_set_label(l1); |
| 799 | 809 |
} |
| 800 | 810 |
|
| ... | ... | |
| 849 | 859 |
} |
| 850 | 860 |
|
| 851 | 861 |
// Z |
| 852 |
static inline void gen_op_eval_be(TCGv dst, TCGv src) |
|
| 862 |
static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
|
|
| 853 | 863 |
{
|
| 854 | 864 |
gen_mov_reg_Z(dst, src); |
| 855 | 865 |
} |
| 856 | 866 |
|
| 857 | 867 |
// Z | (N ^ V) |
| 858 |
static inline void gen_op_eval_ble(TCGv dst, TCGv src) |
|
| 868 |
static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
|
|
| 859 | 869 |
{
|
| 860 | 870 |
gen_mov_reg_N(cpu_tmp0, src); |
| 861 | 871 |
gen_mov_reg_V(dst, src); |
| ... | ... | |
| 865 | 875 |
} |
| 866 | 876 |
|
| 867 | 877 |
// N ^ V |
| 868 |
static inline void gen_op_eval_bl(TCGv dst, TCGv src) |
|
| 878 |
static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
|
|
| 869 | 879 |
{
|
| 870 | 880 |
gen_mov_reg_V(cpu_tmp0, src); |
| 871 | 881 |
gen_mov_reg_N(dst, src); |
| ... | ... | |
| 873 | 883 |
} |
| 874 | 884 |
|
| 875 | 885 |
// C | Z |
| 876 |
static inline void gen_op_eval_bleu(TCGv dst, TCGv src) |
|
| 886 |
static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
|
|
| 877 | 887 |
{
|
| 878 | 888 |
gen_mov_reg_Z(cpu_tmp0, src); |
| 879 | 889 |
gen_mov_reg_C(dst, src); |
| ... | ... | |
| 881 | 891 |
} |
| 882 | 892 |
|
| 883 | 893 |
// C |
| 884 |
static inline void gen_op_eval_bcs(TCGv dst, TCGv src) |
|
| 894 |
static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
|
|
| 885 | 895 |
{
|
| 886 | 896 |
gen_mov_reg_C(dst, src); |
| 887 | 897 |
} |
| 888 | 898 |
|
| 889 | 899 |
// V |
| 890 |
static inline void gen_op_eval_bvs(TCGv dst, TCGv src) |
|
| 900 |
static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
|
|
| 891 | 901 |
{
|
| 892 | 902 |
gen_mov_reg_V(dst, src); |
| 893 | 903 |
} |
| ... | ... | |
| 899 | 909 |
} |
| 900 | 910 |
|
| 901 | 911 |
// N |
| 902 |
static inline void gen_op_eval_bneg(TCGv dst, TCGv src) |
|
| 912 |
static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
|
|
| 903 | 913 |
{
|
| 904 | 914 |
gen_mov_reg_N(dst, src); |
| 905 | 915 |
} |
| 906 | 916 |
|
| 907 | 917 |
// !Z |
| 908 |
static inline void gen_op_eval_bne(TCGv dst, TCGv src) |
|
| 918 |
static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
|
|
| 909 | 919 |
{
|
| 910 | 920 |
gen_mov_reg_Z(dst, src); |
| 911 | 921 |
tcg_gen_xori_tl(dst, dst, 0x1); |
| 912 | 922 |
} |
| 913 | 923 |
|
| 914 | 924 |
// !(Z | (N ^ V)) |
| 915 |
static inline void gen_op_eval_bg(TCGv dst, TCGv src) |
|
| 925 |
static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
|
|
| 916 | 926 |
{
|
| 917 | 927 |
gen_mov_reg_N(cpu_tmp0, src); |
| 918 | 928 |
gen_mov_reg_V(dst, src); |
| ... | ... | |
| 923 | 933 |
} |
| 924 | 934 |
|
| 925 | 935 |
// !(N ^ V) |
| 926 |
static inline void gen_op_eval_bge(TCGv dst, TCGv src) |
|
| 936 |
static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
|
|
| 927 | 937 |
{
|
| 928 | 938 |
gen_mov_reg_V(cpu_tmp0, src); |
| 929 | 939 |
gen_mov_reg_N(dst, src); |
| ... | ... | |
| 932 | 942 |
} |
| 933 | 943 |
|
| 934 | 944 |
// !(C | Z) |
| 935 |
static inline void gen_op_eval_bgu(TCGv dst, TCGv src) |
|
| 945 |
static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
|
|
| 936 | 946 |
{
|
| 937 | 947 |
gen_mov_reg_Z(cpu_tmp0, src); |
| 938 | 948 |
gen_mov_reg_C(dst, src); |
| ... | ... | |
| 941 | 951 |
} |
| 942 | 952 |
|
| 943 | 953 |
// !C |
| 944 |
static inline void gen_op_eval_bcc(TCGv dst, TCGv src) |
|
| 954 |
static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
|
|
| 945 | 955 |
{
|
| 946 | 956 |
gen_mov_reg_C(dst, src); |
| 947 | 957 |
tcg_gen_xori_tl(dst, dst, 0x1); |
| 948 | 958 |
} |
| 949 | 959 |
|
| 950 | 960 |
// !N |
| 951 |
static inline void gen_op_eval_bpos(TCGv dst, TCGv src) |
|
| 961 |
static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
|
|
| 952 | 962 |
{
|
| 953 | 963 |
gen_mov_reg_N(dst, src); |
| 954 | 964 |
tcg_gen_xori_tl(dst, dst, 0x1); |
| 955 | 965 |
} |
| 956 | 966 |
|
| 957 | 967 |
// !V |
| 958 |
static inline void gen_op_eval_bvc(TCGv dst, TCGv src) |
|
| 968 |
static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
|
|
| 959 | 969 |
{
|
| 960 | 970 |
gen_mov_reg_V(dst, src); |
| 961 | 971 |
tcg_gen_xori_tl(dst, dst, 0x1); |
| ... | ... | |
| 1207 | 1217 |
|
| 1208 | 1218 |
static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond) |
| 1209 | 1219 |
{
|
| 1210 |
TCGv r_src; |
|
| 1220 |
TCGv_i32 r_src;
|
|
| 1211 | 1221 |
|
| 1212 | 1222 |
#ifdef TARGET_SPARC64 |
| 1213 | 1223 |
if (cc) |
| ... | ... | |
| 1467 | 1477 |
} |
| 1468 | 1478 |
} |
| 1469 | 1479 |
|
| 1470 |
static GenOpFunc * const gen_fcmpd[4] = {
|
|
| 1471 |
helper_fcmpd, |
|
| 1472 |
helper_fcmpd_fcc1, |
|
| 1473 |
helper_fcmpd_fcc2, |
|
| 1474 |
helper_fcmpd_fcc3, |
|
| 1475 |
}; |
|
| 1476 |
|
|
| 1477 |
static GenOpFunc * const gen_fcmpq[4] = {
|
|
| 1478 |
helper_fcmpq, |
|
| 1479 |
helper_fcmpq_fcc1, |
|
| 1480 |
helper_fcmpq_fcc2, |
|
| 1481 |
helper_fcmpq_fcc3, |
|
| 1482 |
}; |
|
| 1483 |
|
|
| 1484 |
static GenOpFunc * const gen_fcmped[4] = {
|
|
| 1485 |
helper_fcmped, |
|
| 1486 |
helper_fcmped_fcc1, |
|
| 1487 |
helper_fcmped_fcc2, |
|
| 1488 |
helper_fcmped_fcc3, |
|
| 1489 |
}; |
|
| 1490 |
|
|
| 1491 |
static GenOpFunc * const gen_fcmpeq[4] = {
|
|
| 1492 |
helper_fcmpeq, |
|
| 1493 |
helper_fcmpeq_fcc1, |
|
| 1494 |
helper_fcmpeq_fcc2, |
|
| 1495 |
helper_fcmpeq_fcc3, |
|
| 1496 |
}; |
|
| 1497 |
|
|
| 1498 |
static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) |
|
| 1480 |
static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) |
|
| 1499 | 1481 |
{
|
| 1500 | 1482 |
switch (fccno) {
|
| 1501 | 1483 |
case 0: |
| 1502 |
tcg_gen_helper_0_2(helper_fcmps, r_rs1, r_rs2);
|
|
| 1484 |
gen_helper_fcmps(r_rs1, r_rs2);
|
|
| 1503 | 1485 |
break; |
| 1504 | 1486 |
case 1: |
| 1505 |
tcg_gen_helper_0_2(helper_fcmps_fcc1, r_rs1, r_rs2);
|
|
| 1487 |
gen_helper_fcmps_fcc1(r_rs1, r_rs2);
|
|
| 1506 | 1488 |
break; |
| 1507 | 1489 |
case 2: |
| 1508 |
tcg_gen_helper_0_2(helper_fcmps_fcc2, r_rs1, r_rs2);
|
|
| 1490 |
gen_helper_fcmps_fcc2(r_rs1, r_rs2);
|
|
| 1509 | 1491 |
break; |
| 1510 | 1492 |
case 3: |
| 1511 |
tcg_gen_helper_0_2(helper_fcmps_fcc3, r_rs1, r_rs2);
|
|
| 1493 |
gen_helper_fcmps_fcc3(r_rs1, r_rs2);
|
|
| 1512 | 1494 |
break; |
| 1513 | 1495 |
} |
| 1514 | 1496 |
} |
| 1515 | 1497 |
|
| 1516 | 1498 |
static inline void gen_op_fcmpd(int fccno) |
| 1517 | 1499 |
{
|
| 1518 |
tcg_gen_helper_0_0(gen_fcmpd[fccno]); |
|
| 1500 |
switch (fccno) {
|
|
| 1501 |
case 0: |
|
| 1502 |
gen_helper_fcmpd(); |
|
| 1503 |
break; |
|
| 1504 |
case 1: |
|
| 1505 |
gen_helper_fcmpd_fcc1(); |
|
| 1506 |
break; |
|
| 1507 |
case 2: |
|
| 1508 |
gen_helper_fcmpd_fcc2(); |
|
| 1509 |
break; |
|
| 1510 |
case 3: |
|
| 1511 |
gen_helper_fcmpd_fcc3(); |
|
| 1512 |
break; |
|
| 1513 |
} |
|
| 1519 | 1514 |
} |
| 1520 | 1515 |
|
| 1521 | 1516 |
static inline void gen_op_fcmpq(int fccno) |
| 1522 | 1517 |
{
|
| 1523 |
tcg_gen_helper_0_0(gen_fcmpq[fccno]); |
|
| 1518 |
switch (fccno) {
|
|
| 1519 |
case 0: |
|
| 1520 |
gen_helper_fcmpq(); |
|
| 1521 |
break; |
|
| 1522 |
case 1: |
|
| 1523 |
gen_helper_fcmpq_fcc1(); |
|
| 1524 |
break; |
|
| 1525 |
case 2: |
|
| 1526 |
gen_helper_fcmpq_fcc2(); |
|
| 1527 |
break; |
|
| 1528 |
case 3: |
|
| 1529 |
gen_helper_fcmpq_fcc3(); |
|
| 1530 |
break; |
|
| 1531 |
} |
|
| 1524 | 1532 |
} |
| 1525 | 1533 |
|
| 1526 |
static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
|
|
| 1534 |
static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
|
|
| 1527 | 1535 |
{
|
| 1528 | 1536 |
switch (fccno) {
|
| 1529 | 1537 |
case 0: |
| 1530 |
tcg_gen_helper_0_2(helper_fcmpes, r_rs1, r_rs2);
|
|
| 1538 |
gen_helper_fcmpes(r_rs1, r_rs2);
|
|
| 1531 | 1539 |
break; |
| 1532 | 1540 |
case 1: |
| 1533 |
tcg_gen_helper_0_2(helper_fcmpes_fcc1, r_rs1, r_rs2);
|
|
| 1541 |
gen_helper_fcmpes_fcc1(r_rs1, r_rs2);
|
|
| 1534 | 1542 |
break; |
| 1535 | 1543 |
case 2: |
| 1536 |
tcg_gen_helper_0_2(helper_fcmpes_fcc2, r_rs1, r_rs2);
|
|
| 1544 |
gen_helper_fcmpes_fcc2(r_rs1, r_rs2);
|
|
| 1537 | 1545 |
break; |
| 1538 | 1546 |
case 3: |
| 1539 |
tcg_gen_helper_0_2(helper_fcmpes_fcc3, r_rs1, r_rs2);
|
|
| 1547 |
gen_helper_fcmpes_fcc3(r_rs1, r_rs2);
|
|
| 1540 | 1548 |
break; |
| 1541 | 1549 |
} |
| 1542 | 1550 |
} |
| 1543 | 1551 |
|
| 1544 | 1552 |
static inline void gen_op_fcmped(int fccno) |
| 1545 | 1553 |
{
|
| 1546 |
tcg_gen_helper_0_0(gen_fcmped[fccno]); |
|
| 1554 |
switch (fccno) {
|
|
| 1555 |
case 0: |
|
| 1556 |
gen_helper_fcmped(); |
|
| 1557 |
break; |
|
| 1558 |
case 1: |
|
| 1559 |
gen_helper_fcmped_fcc1(); |
|
| 1560 |
break; |
|
| 1561 |
case 2: |
|
| 1562 |
gen_helper_fcmped_fcc2(); |
|
| 1563 |
break; |
|
| 1564 |
case 3: |
|
| 1565 |
gen_helper_fcmped_fcc3(); |
|
| 1566 |
break; |
|
| 1567 |
} |
|
| 1547 | 1568 |
} |
| 1548 | 1569 |
|
| 1549 | 1570 |
static inline void gen_op_fcmpeq(int fccno) |
| 1550 | 1571 |
{
|
| 1551 |
tcg_gen_helper_0_0(gen_fcmpeq[fccno]); |
|
| 1572 |
switch (fccno) {
|
|
| 1573 |
case 0: |
|
| 1574 |
gen_helper_fcmpeq(); |
|
| 1575 |
break; |
|
| 1576 |
case 1: |
|
| 1577 |
gen_helper_fcmpeq_fcc1(); |
|
| 1578 |
break; |
|
| 1579 |
case 2: |
|
| 1580 |
gen_helper_fcmpeq_fcc2(); |
|
| 1581 |
break; |
|
| 1582 |
case 3: |
|
| 1583 |
gen_helper_fcmpeq_fcc3(); |
|
| 1584 |
break; |
|
| 1585 |
} |
|
| 1552 | 1586 |
} |
| 1553 | 1587 |
|
| 1554 | 1588 |
#else |
| 1555 | 1589 |
|
| 1556 | 1590 |
static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) |
| 1557 | 1591 |
{
|
| 1558 |
tcg_gen_helper_0_2(helper_fcmps, r_rs1, r_rs2);
|
|
| 1592 |
gen_helper_fcmps(r_rs1, r_rs2);
|
|
| 1559 | 1593 |
} |
| 1560 | 1594 |
|
| 1561 | 1595 |
static inline void gen_op_fcmpd(int fccno) |
| 1562 | 1596 |
{
|
| 1563 |
tcg_gen_helper_0_0(helper_fcmpd);
|
|
| 1597 |
gen_helper_fcmpd();
|
|
| 1564 | 1598 |
} |
| 1565 | 1599 |
|
| 1566 | 1600 |
static inline void gen_op_fcmpq(int fccno) |
| 1567 | 1601 |
{
|
| 1568 |
tcg_gen_helper_0_0(helper_fcmpq);
|
|
| 1602 |
gen_helper_fcmpq();
|
|
| 1569 | 1603 |
} |
| 1570 | 1604 |
|
| 1571 | 1605 |
static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) |
| 1572 | 1606 |
{
|
| 1573 |
tcg_gen_helper_0_2(helper_fcmpes, r_rs1, r_rs2);
|
|
| 1607 |
gen_helper_fcmpes(r_rs1, r_rs2);
|
|
| 1574 | 1608 |
} |
| 1575 | 1609 |
|
| 1576 | 1610 |
static inline void gen_op_fcmped(int fccno) |
| 1577 | 1611 |
{
|
| 1578 |
tcg_gen_helper_0_0(helper_fcmped);
|
|
| 1612 |
gen_helper_fcmped();
|
|
| 1579 | 1613 |
} |
| 1580 | 1614 |
|
| 1581 | 1615 |
static inline void gen_op_fcmpeq(int fccno) |
| 1582 | 1616 |
{
|
| 1583 |
tcg_gen_helper_0_0(helper_fcmpeq);
|
|
| 1617 |
gen_helper_fcmpeq();
|
|
| 1584 | 1618 |
} |
| 1585 | 1619 |
#endif |
| 1586 | 1620 |
|
| 1587 | 1621 |
static inline void gen_op_fpexception_im(int fsr_flags) |
| 1588 | 1622 |
{
|
| 1589 |
TCGv r_const; |
|
| 1623 |
TCGv_i32 r_const;
|
|
| 1590 | 1624 |
|
| 1591 | 1625 |
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); |
| 1592 | 1626 |
tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
| 1593 | 1627 |
r_const = tcg_const_i32(TT_FP_EXCP); |
| 1594 |
tcg_gen_helper_0_1(raise_exception, r_const);
|
|
| 1595 |
tcg_temp_free(r_const); |
|
| 1628 |
gen_helper_raise_exception(r_const);
|
|
| 1629 |
tcg_temp_free_i32(r_const);
|
|
| 1596 | 1630 |
} |
| 1597 | 1631 |
|
| 1598 | 1632 |
static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) |
| 1599 | 1633 |
{
|
| 1600 | 1634 |
#if !defined(CONFIG_USER_ONLY) |
| 1601 | 1635 |
if (!dc->fpu_enabled) {
|
| 1602 |
TCGv r_const; |
|
| 1636 |
TCGv_i32 r_const;
|
|
| 1603 | 1637 |
|
| 1604 | 1638 |
save_state(dc, r_cond); |
| 1605 | 1639 |
r_const = tcg_const_i32(TT_NFPU_INSN); |
| 1606 |
tcg_gen_helper_0_1(raise_exception, r_const);
|
|
| 1607 |
tcg_temp_free(r_const); |
|
| 1640 |
gen_helper_raise_exception(r_const);
|
|
| 1641 |
tcg_temp_free_i32(r_const);
|
|
| 1608 | 1642 |
dc->is_br = 1; |
| 1609 | 1643 |
return 1; |
| 1610 | 1644 |
} |
| ... | ... | |
| 1619 | 1653 |
|
| 1620 | 1654 |
static inline void gen_clear_float_exceptions(void) |
| 1621 | 1655 |
{
|
| 1622 |
tcg_gen_helper_0_0(helper_clear_float_exceptions);
|
|
| 1656 |
gen_helper_clear_float_exceptions();
|
|
| 1623 | 1657 |
} |
| 1624 | 1658 |
|
| 1625 | 1659 |
/* asi moves */ |
| 1626 | 1660 |
#ifdef TARGET_SPARC64 |
| 1627 |
static inline TCGv gen_get_asi(int insn, TCGv r_addr) |
|
| 1661 |
static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr)
|
|
| 1628 | 1662 |
{
|
| 1629 | 1663 |
int asi; |
| 1630 |
TCGv r_asi; |
|
| 1664 |
TCGv_i32 r_asi;
|
|
| 1631 | 1665 |
|
| 1632 | 1666 |
if (IS_IMM) {
|
| 1633 |
r_asi = tcg_temp_new(TCG_TYPE_I32);
|
|
| 1667 |
r_asi = tcg_temp_new_i32();
|
|
| 1634 | 1668 |
tcg_gen_mov_i32(r_asi, cpu_asi); |
| 1635 | 1669 |
} else {
|
| 1636 | 1670 |
asi = GET_FIELD(insn, 19, 26); |
| ... | ... | |
| 1642 | 1676 |
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
| 1643 | 1677 |
int sign) |
| 1644 | 1678 |
{
|
| 1645 |
TCGv r_asi, r_size, r_sign; |
|
| 1679 |
TCGv_i32 r_asi, r_size, r_sign;
|
|
| 1646 | 1680 |
|
| 1647 | 1681 |
r_asi = gen_get_asi(insn, addr); |
| 1648 | 1682 |
r_size = tcg_const_i32(size); |
| 1649 | 1683 |
r_sign = tcg_const_i32(sign); |
| 1650 |
tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
|
|
| 1651 |
tcg_temp_free(r_sign); |
|
| 1652 |
tcg_temp_free(r_size); |
|
| 1653 |
tcg_temp_free(r_asi); |
|
| 1684 |
gen_helper_ld_asi(dst, addr, r_asi, r_size, r_sign);
|
|
| 1685 |
tcg_temp_free_i32(r_sign);
|
|
| 1686 |
tcg_temp_free_i32(r_size);
|
|
| 1687 |
tcg_temp_free_i32(r_asi);
|
|
| 1654 | 1688 |
} |
| 1655 | 1689 |
|
| 1656 | 1690 |
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
| 1657 | 1691 |
{
|
| 1658 |
TCGv r_asi, r_size; |
|
| 1692 |
TCGv_i32 r_asi, r_size;
|
|
| 1659 | 1693 |
|
| 1660 | 1694 |
r_asi = gen_get_asi(insn, addr); |
| 1661 | 1695 |
r_size = tcg_const_i32(size); |
| 1662 |
tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
|
|
| 1663 |
tcg_temp_free(r_size); |
|
| 1664 |
tcg_temp_free(r_asi); |
|
| 1696 |
gen_helper_st_asi(addr, src, r_asi, r_size);
|
|
| 1697 |
tcg_temp_free_i32(r_size);
|
|
| 1698 |
tcg_temp_free_i32(r_asi);
|
|
| 1665 | 1699 |
} |
| 1666 | 1700 |
|
| 1667 | 1701 |
static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) |
| 1668 | 1702 |
{
|
| 1669 |
TCGv r_asi, r_size, r_rd; |
|
| 1703 |
TCGv_i32 r_asi, r_size, r_rd;
|
|
| 1670 | 1704 |
|
| 1671 | 1705 |
r_asi = gen_get_asi(insn, addr); |
| 1672 | 1706 |
r_size = tcg_const_i32(size); |
| 1673 | 1707 |
r_rd = tcg_const_i32(rd); |
| 1674 |
tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
|
|
| 1675 |
tcg_temp_free(r_rd); |
|
| 1676 |
tcg_temp_free(r_size); |
|
| 1677 |
tcg_temp_free(r_asi); |
|
| 1708 |
gen_helper_ldf_asi(addr, r_asi, r_size, r_rd);
|
|
| 1709 |
tcg_temp_free_i32(r_rd);
|
|
| 1710 |
tcg_temp_free_i32(r_size);
|
|
| 1711 |
tcg_temp_free_i32(r_asi);
|
|
| 1678 | 1712 |
} |
| 1679 | 1713 |
|
| 1680 | 1714 |
static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) |
| 1681 | 1715 |
{
|
| 1682 |
TCGv r_asi, r_size, r_rd; |
|
| 1716 |
TCGv_i32 r_asi, r_size, r_rd;
|
|
| 1683 | 1717 |
|
| 1684 | 1718 |
r_asi = gen_get_asi(insn, addr); |
| 1685 | 1719 |
r_size = tcg_const_i32(size); |
| 1686 | 1720 |
r_rd = tcg_const_i32(rd); |
| 1687 |
tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
|
|
| 1688 |
tcg_temp_free(r_rd); |
|
| 1689 |
tcg_temp_free(r_size); |
|
| 1690 |
tcg_temp_free(r_asi); |
|
| 1721 |
gen_helper_stf_asi(addr, r_asi, r_size, r_rd);
|
|
| 1722 |
tcg_temp_free_i32(r_rd);
|
|
| 1723 |
tcg_temp_free_i32(r_size);
|
|
| 1724 |
tcg_temp_free_i32(r_asi);
|
|
| 1691 | 1725 |
} |
| 1692 | 1726 |
|
| 1693 | 1727 |
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
| 1694 | 1728 |
{
|
| 1695 |
TCGv r_asi, r_size, r_sign; |
|
| 1729 |
TCGv_i32 r_asi, r_size, r_sign;
|
|
| 1696 | 1730 |
|
| 1697 | 1731 |
r_asi = gen_get_asi(insn, addr); |
| 1698 | 1732 |
r_size = tcg_const_i32(4); |
| 1699 | 1733 |
r_sign = tcg_const_i32(0); |
| 1700 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
|
|
| 1701 |
tcg_temp_free(r_sign); |
|
| 1702 |
tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
|
|
| 1703 |
tcg_temp_free(r_size); |
|
| 1704 |
tcg_temp_free(r_asi); |
|
| 1734 |
gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
|
|
| 1735 |
tcg_temp_free_i32(r_sign);
|
|
| 1736 |
gen_helper_st_asi(addr, dst, r_asi, r_size);
|
|
| 1737 |
tcg_temp_free_i32(r_size);
|
|
| 1738 |
tcg_temp_free_i32(r_asi);
|
|
| 1705 | 1739 |
tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
| 1706 | 1740 |
} |
| 1707 | 1741 |
|
| 1708 | 1742 |
static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
| 1709 | 1743 |
{
|
| 1710 |
TCGv r_asi, r_rd; |
|
| 1744 |
TCGv_i32 r_asi, r_rd;
|
|
| 1711 | 1745 |
|
| 1712 | 1746 |
r_asi = gen_get_asi(insn, addr); |
| 1713 | 1747 |
r_rd = tcg_const_i32(rd); |
| 1714 |
tcg_gen_helper_0_3(helper_ldda_asi, addr, r_asi, r_rd);
|
|
| 1715 |
tcg_temp_free(r_rd); |
|
| 1716 |
tcg_temp_free(r_asi); |
|
| 1748 |
gen_helper_ldda_asi(addr, r_asi, r_rd);
|
|
| 1749 |
tcg_temp_free_i32(r_rd);
|
|
| 1750 |
tcg_temp_free_i32(r_asi);
|
|
| 1717 | 1751 |
} |
| 1718 | 1752 |
|
| 1719 | 1753 |
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
| 1720 | 1754 |
{
|
| 1721 |
TCGv r_asi, r_size; |
|
| 1755 |
TCGv_i32 r_asi, r_size;
|
|
| 1722 | 1756 |
|
| 1723 | 1757 |
gen_movl_reg_TN(rd + 1, cpu_tmp0); |
| 1724 | 1758 |
tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); |
| 1725 | 1759 |
r_asi = gen_get_asi(insn, addr); |
| 1726 | 1760 |
r_size = tcg_const_i32(8); |
| 1727 |
tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
|
|
| 1728 |
tcg_temp_free(r_size); |
|
| 1729 |
tcg_temp_free(r_asi); |
|
| 1761 |
gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
|
|
| 1762 |
tcg_temp_free_i32(r_size);
|
|
| 1763 |
tcg_temp_free_i32(r_asi);
|
|
| 1730 | 1764 |
} |
| 1731 | 1765 |
|
| 1732 | 1766 |
static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
| 1733 | 1767 |
int rd) |
| 1734 | 1768 |
{
|
| 1735 |
TCGv r_val1, r_asi; |
|
| 1769 |
TCGv r_val1; |
|
| 1770 |
TCGv_i32 r_asi; |
|
| 1736 | 1771 |
|
| 1737 |
r_val1 = tcg_temp_new(TCG_TYPE_TL);
|
|
| 1772 |
r_val1 = tcg_temp_new(); |
|
| 1738 | 1773 |
gen_movl_reg_TN(rd, r_val1); |
| 1739 | 1774 |
r_asi = gen_get_asi(insn, addr); |
| 1740 |
tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
|
|
| 1741 |
tcg_temp_free(r_asi); |
|
| 1775 |
gen_helper_cas_asi(dst, addr, r_val1, val2, r_asi);
|
|
| 1776 |
tcg_temp_free_i32(r_asi);
|
|
| 1742 | 1777 |
tcg_temp_free(r_val1); |
| 1743 | 1778 |
} |
| 1744 | 1779 |
|
| 1745 | 1780 |
static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
| 1746 | 1781 |
int rd) |
| 1747 | 1782 |
{
|
| 1748 |
TCGv r_asi; |
|
| 1783 |
TCGv_i32 r_asi;
|
|
| 1749 | 1784 |
|
| 1750 | 1785 |
gen_movl_reg_TN(rd, cpu_tmp64); |
| 1751 | 1786 |
r_asi = gen_get_asi(insn, addr); |
| 1752 |
tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
|
|
| 1753 |
tcg_temp_free(r_asi); |
|
| 1787 |
gen_helper_casx_asi(dst, addr, cpu_tmp64, val2, r_asi);
|
|
| 1788 |
tcg_temp_free_i32(r_asi);
|
|
| 1754 | 1789 |
} |
| 1755 | 1790 |
|
| 1756 | 1791 |
#elif !defined(CONFIG_USER_ONLY) |
| ... | ... | |
| 1758 | 1793 |
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
| 1759 | 1794 |
int sign) |
| 1760 | 1795 |
{
|
| 1761 |
TCGv r_asi, r_size, r_sign; |
|
| 1796 |
TCGv_i32 r_asi, r_size, r_sign;
|
|
| 1762 | 1797 |
|
| 1763 | 1798 |
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
| 1764 | 1799 |
r_size = tcg_const_i32(size); |
| 1765 | 1800 |
r_sign = tcg_const_i32(sign); |
| 1766 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
|
|
| 1801 |
gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
|
|
| 1767 | 1802 |
tcg_temp_free(r_sign); |
| 1768 | 1803 |
tcg_temp_free(r_size); |
| 1769 | 1804 |
tcg_temp_free(r_asi); |
| ... | ... | |
| 1772 | 1807 |
|
| 1773 | 1808 |
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
| 1774 | 1809 |
{
|
| 1775 |
TCGv r_asi, r_size; |
|
| 1810 |
TCGv_i32 r_asi, r_size;
|
|
| 1776 | 1811 |
|
| 1777 | 1812 |
tcg_gen_extu_tl_i64(cpu_tmp64, src); |
| 1778 | 1813 |
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
| 1779 | 1814 |
r_size = tcg_const_i32(size); |
| 1780 |
tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
|
|
| 1815 |
gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
|
|
| 1781 | 1816 |
tcg_temp_free(r_size); |
| 1782 | 1817 |
tcg_temp_free(r_asi); |
| 1783 | 1818 |
} |
| 1784 | 1819 |
|
| 1785 | 1820 |
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
| 1786 | 1821 |
{
|
| 1787 |
TCGv r_asi, r_size, r_sign; |
|
| 1822 |
TCGv_i32 r_asi, r_size, r_sign; |
|
| 1823 |
TCGv_i64 r_val; |
|
| 1788 | 1824 |
|
| 1789 | 1825 |
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
| 1790 | 1826 |
r_size = tcg_const_i32(4); |
| 1791 | 1827 |
r_sign = tcg_const_i32(0); |
| 1792 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
|
|
| 1828 |
gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
|
|
| 1793 | 1829 |
tcg_temp_free(r_sign); |
| 1794 |
tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size); |
|
| 1830 |
r_val = tcg_temp_new_i64(); |
|
| 1831 |
tcg_gen_extu_tl_i64(r_val, dst); |
|
| 1832 |
gen_helper_st_asi(addr, r_val, r_asi, r_size); |
|
| 1833 |
tcg_temp_free_i64(r_val); |
|
| 1795 | 1834 |
tcg_temp_free(r_size); |
| 1796 | 1835 |
tcg_temp_free(r_asi); |
| 1797 | 1836 |
tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
| ... | ... | |
| 1799 | 1838 |
|
| 1800 | 1839 |
static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
| 1801 | 1840 |
{
|
| 1802 |
TCGv r_asi, r_size, r_sign; |
|
| 1841 |
TCGv_i32 r_asi, r_size, r_sign;
|
|
| 1803 | 1842 |
|
| 1804 | 1843 |
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
| 1805 | 1844 |
r_size = tcg_const_i32(8); |
| 1806 | 1845 |
r_sign = tcg_const_i32(0); |
| 1807 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
|
|
| 1846 |
gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
|
|
| 1808 | 1847 |
tcg_temp_free(r_sign); |
| 1809 | 1848 |
tcg_temp_free(r_size); |
| 1810 | 1849 |
tcg_temp_free(r_asi); |
| ... | ... | |
| 1817 | 1856 |
|
| 1818 | 1857 |
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
| 1819 | 1858 |
{
|
| 1820 |
TCGv r_asi, r_size; |
|
| 1859 |
TCGv_i32 r_asi, r_size;
|
|
| 1821 | 1860 |
|
| 1822 | 1861 |
gen_movl_reg_TN(rd + 1, cpu_tmp0); |
| 1823 | 1862 |
tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); |
| 1824 | 1863 |
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
| 1825 | 1864 |
r_size = tcg_const_i32(8); |
| 1826 |
tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
|
|
| 1865 |
gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
|
|
| 1827 | 1866 |
tcg_temp_free(r_size); |
| 1828 | 1867 |
tcg_temp_free(r_asi); |
| 1829 | 1868 |
} |
| ... | ... | |
| 1832 | 1871 |
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
| 1833 | 1872 |
static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) |
| 1834 | 1873 |
{
|
| 1835 |
TCGv r_val, r_asi, r_size; |
|
| 1874 |
TCGv_i64 r_val; |
|
| 1875 |
TCGv_i32 r_asi, r_size; |
|
| 1836 | 1876 |
|
| 1837 | 1877 |
gen_ld_asi(dst, addr, insn, 1, 0); |
| 1838 | 1878 |
|
| 1839 | 1879 |
r_val = tcg_const_i64(0xffULL); |
| 1840 | 1880 |
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
| 1841 | 1881 |
r_size = tcg_const_i32(1); |
| 1842 |
tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
|
|
| 1843 |
tcg_temp_free(r_size); |
|
| 1844 |
tcg_temp_free(r_asi); |
|
| 1845 |
tcg_temp_free(r_val); |
|
| 1882 |
gen_helper_st_asi(addr, r_val, r_asi, r_size);
|
|
| 1883 |
tcg_temp_free_i32(r_size);
|
|
| 1884 |
tcg_temp_free_i32(r_asi);
|
|
| 1885 |
tcg_temp_free_i64(r_val);
|
|
| 1846 | 1886 |
} |
| 1847 | 1887 |
#endif |
| 1848 | 1888 |
|
| ... | ... | |
| 1900 | 1940 |
|
| 1901 | 1941 |
rd = GET_FIELD(insn, 2, 6); |
| 1902 | 1942 |
|
| 1903 |
cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
|
|
| 1904 |
cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
|
|
| 1943 |
cpu_src1 = tcg_temp_new(); // const |
|
| 1944 |
cpu_src2 = tcg_temp_new(); // const |
|
| 1905 | 1945 |
|
| 1906 | 1946 |
switch (opc) {
|
| 1907 | 1947 |
case 0: /* branches/sethi */ |
| ... | ... | |
| 2028 | 2068 |
else |
| 2029 | 2069 |
tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
| 2030 | 2070 |
tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
| 2031 |
tcg_gen_helper_0_1(raise_exception, cpu_dst); |
|
| 2071 |
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
|
| 2072 |
gen_helper_raise_exception(cpu_tmp32); |
|
| 2032 | 2073 |
} else if (cond != 0) {
|
| 2033 |
TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
|
|
| 2074 |
TCGv r_cond = tcg_temp_new(); |
|
| 2034 | 2075 |
int l1; |
| 2035 | 2076 |
#ifdef TARGET_SPARC64 |
| 2036 | 2077 |
/* V9 icc/xcc */ |
| ... | ... | |
| 2056 | 2097 |
else |
| 2057 | 2098 |
tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
| 2058 | 2099 |
tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
| 2059 |
tcg_gen_helper_0_1(raise_exception, cpu_dst); |
|
| 2100 |
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
|
| 2101 |
gen_helper_raise_exception(cpu_tmp32); |
|
| 2060 | 2102 |
|
| 2061 | 2103 |
gen_set_label(l1); |
| 2062 | 2104 |
tcg_temp_free(r_cond); |
| ... | ... | |
| 2083 | 2125 |
break; |
| 2084 | 2126 |
#ifdef TARGET_SPARC64 |
| 2085 | 2127 |
case 0x2: /* V9 rdccr */ |
| 2086 |
tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
|
|
| 2128 |
gen_helper_rdccr(cpu_dst);
|
|
| 2087 | 2129 |
gen_movl_TN_reg(rd, cpu_dst); |
| 2088 | 2130 |
break; |
| 2089 | 2131 |
case 0x3: /* V9 rdasi */ |
| ... | ... | |
| 2092 | 2134 |
break; |
| 2093 | 2135 |
case 0x4: /* V9 rdtick */ |
| 2094 | 2136 |
{
|
| 2095 |
TCGv r_tickptr; |
|
| 2137 |
TCGv_ptr r_tickptr;
|
|
| 2096 | 2138 |
|
| 2097 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
|
|
| 2139 |
r_tickptr = tcg_temp_new_ptr();
|
|
| 2098 | 2140 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
| 2099 | 2141 |
offsetof(CPUState, tick)); |
| 2100 |
tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
|
| 2101 |
r_tickptr); |
|
| 2102 |
tcg_temp_free(r_tickptr); |
|
| 2142 |
gen_helper_tick_get_count(cpu_dst, r_tickptr); |
|
| 2143 |
tcg_temp_free_ptr(r_tickptr); |
|
| 2103 | 2144 |
gen_movl_TN_reg(rd, cpu_dst); |
| 2104 | 2145 |
} |
| 2105 | 2146 |
break; |
| ... | ... | |
| 2132 | 2173 |
break; |
| 2133 | 2174 |
case 0x18: /* System tick */ |
| 2134 | 2175 |
{
|
| 2135 |
TCGv r_tickptr; |
|
| 2176 |
TCGv_ptr r_tickptr;
|
|
| 2136 | 2177 |
|
| 2137 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
|
|
| 2178 |
r_tickptr = tcg_temp_new_ptr();
|
|
| 2138 | 2179 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
| 2139 | 2180 |
offsetof(CPUState, stick)); |
| 2140 |
tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
|
| 2141 |
r_tickptr); |
|
| 2142 |
tcg_temp_free(r_tickptr); |
|
| 2181 |
gen_helper_tick_get_count(cpu_dst, r_tickptr); |
|
| 2182 |
tcg_temp_free_ptr(r_tickptr); |
|
| 2143 | 2183 |
gen_movl_TN_reg(rd, cpu_dst); |
| 2144 | 2184 |
} |
| 2145 | 2185 |
break; |
| ... | ... | |
| 2160 | 2200 |
#ifndef TARGET_SPARC64 |
| 2161 | 2201 |
if (!supervisor(dc)) |
| 2162 | 2202 |
goto priv_insn; |
| 2163 |
tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
|
|
| 2203 |
gen_helper_rdpsr(cpu_dst);
|
|
| 2164 | 2204 |
#else |
| 2165 | 2205 |
CHECK_IU_FEATURE(dc, HYPV); |
| 2166 | 2206 |
if (!hypervisor(dc)) |
| ... | ... | |
| 2199 | 2239 |
switch (rs1) {
|
| 2200 | 2240 |
case 0: // tpc |
| 2201 | 2241 |
{
|
| 2202 |
TCGv r_tsptr; |
|
| 2242 |
TCGv_ptr r_tsptr;
|
|
| 2203 | 2243 |
|
| 2204 |
r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
|
|
| 2244 |
r_tsptr = tcg_temp_new_ptr();
|
|
| 2205 | 2245 |
tcg_gen_ld_ptr(r_tsptr, cpu_env, |
| 2206 | 2246 |
offsetof(CPUState, tsptr)); |
| 2207 |
tcg_gen_ld_tl(cpu_tmp32, r_tsptr,
|
|
| 2247 |
tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
|
|
| 2208 | 2248 |
offsetof(trap_state, tpc)); |
| 2209 |
tcg_temp_free(r_tsptr); |
|
| 2210 |
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
|
| 2249 |
tcg_temp_free_ptr(r_tsptr); |
|
| 2211 | 2250 |
} |
| 2212 | 2251 |
break; |
| 2213 | 2252 |
case 1: // tnpc |
| 2214 | 2253 |
{
|
| 2215 |
TCGv r_tsptr; |
|
| 2254 |
TCGv_ptr r_tsptr;
|
|
| 2216 | 2255 |
|
| 2217 |
r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
|
|
| 2256 |
r_tsptr = tcg_temp_new_ptr();
|
|
| 2218 | 2257 |
tcg_gen_ld_ptr(r_tsptr, cpu_env, |
| 2219 | 2258 |
offsetof(CPUState, tsptr)); |
| 2220 | 2259 |
tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
| 2221 | 2260 |
offsetof(trap_state, tnpc)); |
| 2222 |
tcg_temp_free(r_tsptr); |
|
| 2261 |
tcg_temp_free_ptr(r_tsptr);
|
|
| 2223 | 2262 |
} |
| 2224 | 2263 |
break; |
| 2225 | 2264 |
case 2: // tstate |
| 2226 | 2265 |
{
|
| 2227 |
TCGv r_tsptr; |
|
| 2266 |
TCGv_ptr r_tsptr;
|
|
| 2228 | 2267 |
|
| 2229 |
r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
|
|
| 2268 |
r_tsptr = tcg_temp_new_ptr();
|
|
| 2230 | 2269 |
tcg_gen_ld_ptr(r_tsptr, cpu_env, |
| 2231 | 2270 |
offsetof(CPUState, tsptr)); |
| 2232 | 2271 |
tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
| 2233 | 2272 |
offsetof(trap_state, tstate)); |
| 2234 |
tcg_temp_free(r_tsptr); |
|
| 2273 |
tcg_temp_free_ptr(r_tsptr);
|
|
| 2235 | 2274 |
} |
| 2236 | 2275 |
break; |
| 2237 | 2276 |
case 3: // tt |
| 2238 | 2277 |
{
|
| 2239 |
TCGv r_tsptr; |
|
| 2278 |
TCGv_ptr r_tsptr;
|
|
| 2240 | 2279 |
|
| 2241 |
r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
|
|
| 2280 |
r_tsptr = tcg_temp_new_ptr();
|
|
| 2242 | 2281 |
tcg_gen_ld_ptr(r_tsptr, cpu_env, |
| 2243 | 2282 |
offsetof(CPUState, tsptr)); |
| 2244 |
tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
|
|
| 2283 |
tcg_gen_ld_i32(cpu_tmp32, r_tsptr,
|
|
| 2245 | 2284 |
offsetof(trap_state, tt)); |
| 2246 |
tcg_temp_free(r_tsptr); |
|
| 2285 |
tcg_temp_free_ptr(r_tsptr); |
|
| 2286 |
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
|
| 2247 | 2287 |
} |
| 2248 | 2288 |
break; |
| 2249 | 2289 |
case 4: // tick |
| 2250 | 2290 |
{
|
| 2251 |
TCGv r_tickptr; |
|
| 2291 |
TCGv_ptr r_tickptr;
|
|
| 2252 | 2292 |
|
| 2253 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
|
|
| 2293 |
r_tickptr = tcg_temp_new_ptr();
|
|
| 2254 | 2294 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
| 2255 | 2295 |
offsetof(CPUState, tick)); |
| 2256 |
tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0, |
|
| 2257 |
r_tickptr); |
|
| 2296 |
gen_helper_tick_get_count(cpu_tmp0, r_tickptr); |
|
| 2258 | 2297 |
gen_movl_TN_reg(rd, cpu_tmp0); |
| 2259 |
tcg_temp_free(r_tickptr); |
|
| 2298 |
tcg_temp_free_ptr(r_tickptr);
|
|
| 2260 | 2299 |
} |
| 2261 | 2300 |
break; |
| 2262 | 2301 |
case 5: // tba |
| ... | ... | |
| 2278 | 2317 |
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
| 2279 | 2318 |
break; |
| 2280 | 2319 |
case 9: // cwp |
| 2281 |
tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
|
|
| 2320 |
gen_helper_rdcwp(cpu_tmp0);
|
|
| 2282 | 2321 |
break; |
| 2283 | 2322 |
case 10: // cansave |
| 2284 | 2323 |
tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
| ... | ... | |
| 2332 | 2371 |
} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
|
| 2333 | 2372 |
#ifdef TARGET_SPARC64 |
| 2334 | 2373 |
save_state(dc, cpu_cond); |
| 2335 |
tcg_gen_helper_0_0(helper_flushw);
|
|
| 2374 |
gen_helper_flushw();
|
|
| 2336 | 2375 |
#else |
| 2337 | 2376 |
if (!supervisor(dc)) |
| 2338 | 2377 |
goto priv_insn; |
| ... | ... | |
| 2352 | 2391 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
| 2353 | 2392 |
break; |
| 2354 | 2393 |
case 0x5: /* fnegs */ |
| 2355 |
tcg_gen_helper_1_1(helper_fnegs, cpu_fpr[rd], |
|
| 2356 |
cpu_fpr[rs2]); |
|
| 2394 |
gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]); |
|
| 2357 | 2395 |
break; |
| 2358 | 2396 |
case 0x9: /* fabss */ |
| 2359 |
tcg_gen_helper_1_1(helper_fabss, cpu_fpr[rd], |
|
| 2360 |
cpu_fpr[rs2]); |
|
| 2397 |
gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]); |
|
| 2361 | 2398 |
break; |
| 2362 | 2399 |
case 0x29: /* fsqrts */ |
| 2363 | 2400 |
CHECK_FPU_FEATURE(dc, FSQRT); |
| 2364 | 2401 |
gen_clear_float_exceptions(); |
| 2365 |
tcg_gen_helper_1_1(helper_fsqrts, cpu_tmp32, |
|
| 2366 |
cpu_fpr[rs2]); |
|
| 2367 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
|
| 2402 |
gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]); |
|
| 2403 |
gen_helper_check_ieee_exceptions(); |
|
| 2368 | 2404 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2369 | 2405 |
break; |
| 2370 | 2406 |
case 0x2a: /* fsqrtd */ |
| 2371 | 2407 |
CHECK_FPU_FEATURE(dc, FSQRT); |
| 2372 | 2408 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2373 | 2409 |
gen_clear_float_exceptions(); |
| 2374 |
tcg_gen_helper_0_0(helper_fsqrtd);
|
|
| 2375 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2410 |
gen_helper_fsqrtd();
|
|
| 2411 |
gen_helper_check_ieee_exceptions();
|
|
| 2376 | 2412 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2377 | 2413 |
break; |
| 2378 | 2414 |
case 0x2b: /* fsqrtq */ |
| 2379 | 2415 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2380 | 2416 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2381 | 2417 |
gen_clear_float_exceptions(); |
| 2382 |
tcg_gen_helper_0_0(helper_fsqrtq);
|
|
| 2383 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2418 |
gen_helper_fsqrtq();
|
|
| 2419 |
gen_helper_check_ieee_exceptions();
|
|
| 2384 | 2420 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2385 | 2421 |
break; |
| 2386 | 2422 |
case 0x41: /* fadds */ |
| 2387 | 2423 |
gen_clear_float_exceptions(); |
| 2388 |
tcg_gen_helper_1_2(helper_fadds, cpu_tmp32,
|
|
| 2389 |
cpu_fpr[rs1], cpu_fpr[rs2]);
|
|
| 2390 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2424 |
gen_helper_fadds(cpu_tmp32,
|
|
| 2425 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 2426 |
gen_helper_check_ieee_exceptions();
|
|
| 2391 | 2427 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2392 | 2428 |
break; |
| 2393 | 2429 |
case 0x42: |
| 2394 | 2430 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 2395 | 2431 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2396 | 2432 |
gen_clear_float_exceptions(); |
| 2397 |
tcg_gen_helper_0_0(helper_faddd);
|
|
| 2398 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2433 |
gen_helper_faddd();
|
|
| 2434 |
gen_helper_check_ieee_exceptions();
|
|
| 2399 | 2435 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2400 | 2436 |
break; |
| 2401 | 2437 |
case 0x43: /* faddq */ |
| ... | ... | |
| 2403 | 2439 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
| 2404 | 2440 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2405 | 2441 |
gen_clear_float_exceptions(); |
| 2406 |
tcg_gen_helper_0_0(helper_faddq);
|
|
| 2407 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2442 |
gen_helper_faddq();
|
|
| 2443 |
gen_helper_check_ieee_exceptions();
|
|
| 2408 | 2444 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2409 | 2445 |
break; |
| 2410 | 2446 |
case 0x45: /* fsubs */ |
| 2411 | 2447 |
gen_clear_float_exceptions(); |
| 2412 |
tcg_gen_helper_1_2(helper_fsubs, cpu_tmp32,
|
|
| 2413 |
cpu_fpr[rs1], cpu_fpr[rs2]);
|
|
| 2414 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2448 |
gen_helper_fsubs(cpu_tmp32,
|
|
| 2449 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 2450 |
gen_helper_check_ieee_exceptions();
|
|
| 2415 | 2451 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2416 | 2452 |
break; |
| 2417 | 2453 |
case 0x46: |
| 2418 | 2454 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 2419 | 2455 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2420 | 2456 |
gen_clear_float_exceptions(); |
| 2421 |
tcg_gen_helper_0_0(helper_fsubd);
|
|
| 2422 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2457 |
gen_helper_fsubd();
|
|
| 2458 |
gen_helper_check_ieee_exceptions();
|
|
| 2423 | 2459 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2424 | 2460 |
break; |
| 2425 | 2461 |
case 0x47: /* fsubq */ |
| ... | ... | |
| 2427 | 2463 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
| 2428 | 2464 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2429 | 2465 |
gen_clear_float_exceptions(); |
| 2430 |
tcg_gen_helper_0_0(helper_fsubq);
|
|
| 2431 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2466 |
gen_helper_fsubq();
|
|
| 2467 |
gen_helper_check_ieee_exceptions();
|
|
| 2432 | 2468 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2433 | 2469 |
break; |
| 2434 | 2470 |
case 0x49: /* fmuls */ |
| 2435 | 2471 |
CHECK_FPU_FEATURE(dc, FMUL); |
| 2436 | 2472 |
gen_clear_float_exceptions(); |
| 2437 |
tcg_gen_helper_1_2(helper_fmuls, cpu_tmp32,
|
|
| 2438 |
cpu_fpr[rs1], cpu_fpr[rs2]);
|
|
| 2439 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2473 |
gen_helper_fmuls(cpu_tmp32,
|
|
| 2474 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 2475 |
gen_helper_check_ieee_exceptions();
|
|
| 2440 | 2476 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2441 | 2477 |
break; |
| 2442 | 2478 |
case 0x4a: /* fmuld */ |
| ... | ... | |
| 2444 | 2480 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 2445 | 2481 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2446 | 2482 |
gen_clear_float_exceptions(); |
| 2447 |
tcg_gen_helper_0_0(helper_fmuld);
|
|
| 2448 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2483 |
gen_helper_fmuld();
|
|
| 2484 |
gen_helper_check_ieee_exceptions();
|
|
| 2449 | 2485 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2450 | 2486 |
break; |
| 2451 | 2487 |
case 0x4b: /* fmulq */ |
| ... | ... | |
| 2454 | 2490 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
| 2455 | 2491 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2456 | 2492 |
gen_clear_float_exceptions(); |
| 2457 |
tcg_gen_helper_0_0(helper_fmulq);
|
|
| 2458 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2493 |
gen_helper_fmulq();
|
|
| 2494 |
gen_helper_check_ieee_exceptions();
|
|
| 2459 | 2495 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2460 | 2496 |
break; |
| 2461 | 2497 |
case 0x4d: /* fdivs */ |
| 2462 | 2498 |
gen_clear_float_exceptions(); |
| 2463 |
tcg_gen_helper_1_2(helper_fdivs, cpu_tmp32,
|
|
| 2464 |
cpu_fpr[rs1], cpu_fpr[rs2]);
|
|
| 2465 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2499 |
gen_helper_fdivs(cpu_tmp32,
|
|
| 2500 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 2501 |
gen_helper_check_ieee_exceptions();
|
|
| 2466 | 2502 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2467 | 2503 |
break; |
| 2468 | 2504 |
case 0x4e: |
| 2469 | 2505 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 2470 | 2506 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2471 | 2507 |
gen_clear_float_exceptions(); |
| 2472 |
tcg_gen_helper_0_0(helper_fdivd);
|
|
| 2473 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2508 |
gen_helper_fdivd();
|
|
| 2509 |
gen_helper_check_ieee_exceptions();
|
|
| 2474 | 2510 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2475 | 2511 |
break; |
| 2476 | 2512 |
case 0x4f: /* fdivq */ |
| ... | ... | |
| 2478 | 2514 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
| 2479 | 2515 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2480 | 2516 |
gen_clear_float_exceptions(); |
| 2481 |
tcg_gen_helper_0_0(helper_fdivq);
|
|
| 2482 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2517 |
gen_helper_fdivq();
|
|
| 2518 |
gen_helper_check_ieee_exceptions();
|
|
| 2483 | 2519 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2484 | 2520 |
break; |
| 2485 | 2521 |
case 0x69: /* fsmuld */ |
| 2486 | 2522 |
CHECK_FPU_FEATURE(dc, FSMULD); |
| 2487 | 2523 |
gen_clear_float_exceptions(); |
| 2488 |
tcg_gen_helper_0_2(helper_fsmuld, cpu_fpr[rs1], |
|
| 2489 |
cpu_fpr[rs2]); |
|
| 2490 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
|
| 2524 |
gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 2525 |
gen_helper_check_ieee_exceptions(); |
|
| 2491 | 2526 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2492 | 2527 |
break; |
| 2493 | 2528 |
case 0x6e: /* fdmulq */ |
| ... | ... | |
| 2495 | 2530 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 2496 | 2531 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2497 | 2532 |
gen_clear_float_exceptions(); |
| 2498 |
tcg_gen_helper_0_0(helper_fdmulq);
|
|
| 2499 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2533 |
gen_helper_fdmulq();
|
|
| 2534 |
gen_helper_check_ieee_exceptions();
|
|
| 2500 | 2535 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2501 | 2536 |
break; |
| 2502 | 2537 |
case 0xc4: /* fitos */ |
| 2503 | 2538 |
gen_clear_float_exceptions(); |
| 2504 |
tcg_gen_helper_1_1(helper_fitos, cpu_tmp32, |
|
| 2505 |
cpu_fpr[rs2]); |
|
| 2506 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
|
| 2539 |
gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]); |
|
| 2540 |
gen_helper_check_ieee_exceptions(); |
|
| 2507 | 2541 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2508 | 2542 |
break; |
| 2509 | 2543 |
case 0xc6: /* fdtos */ |
| 2510 | 2544 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2511 | 2545 |
gen_clear_float_exceptions(); |
| 2512 |
tcg_gen_helper_1_0(helper_fdtos, cpu_tmp32);
|
|
| 2513 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2546 |
gen_helper_fdtos(cpu_tmp32);
|
|
| 2547 |
gen_helper_check_ieee_exceptions();
|
|
| 2514 | 2548 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2515 | 2549 |
break; |
| 2516 | 2550 |
case 0xc7: /* fqtos */ |
| 2517 | 2551 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2518 | 2552 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2519 | 2553 |
gen_clear_float_exceptions(); |
| 2520 |
tcg_gen_helper_1_0(helper_fqtos, cpu_tmp32);
|
|
| 2521 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2554 |
gen_helper_fqtos(cpu_tmp32);
|
|
| 2555 |
gen_helper_check_ieee_exceptions();
|
|
| 2522 | 2556 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2523 | 2557 |
break; |
| 2524 | 2558 |
case 0xc8: /* fitod */ |
| 2525 |
tcg_gen_helper_0_1(helper_fitod, cpu_fpr[rs2]);
|
|
| 2559 |
gen_helper_fitod(cpu_fpr[rs2]);
|
|
| 2526 | 2560 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2527 | 2561 |
break; |
| 2528 | 2562 |
case 0xc9: /* fstod */ |
| 2529 |
tcg_gen_helper_0_1(helper_fstod, cpu_fpr[rs2]);
|
|
| 2563 |
gen_helper_fstod(cpu_fpr[rs2]);
|
|
| 2530 | 2564 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2531 | 2565 |
break; |
| 2532 | 2566 |
case 0xcb: /* fqtod */ |
| 2533 | 2567 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2534 | 2568 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2535 | 2569 |
gen_clear_float_exceptions(); |
| 2536 |
tcg_gen_helper_0_0(helper_fqtod);
|
|
| 2537 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2570 |
gen_helper_fqtod();
|
|
| 2571 |
gen_helper_check_ieee_exceptions();
|
|
| 2538 | 2572 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2539 | 2573 |
break; |
| 2540 | 2574 |
case 0xcc: /* fitoq */ |
| 2541 | 2575 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2542 |
tcg_gen_helper_0_1(helper_fitoq, cpu_fpr[rs2]);
|
|
| 2576 |
gen_helper_fitoq(cpu_fpr[rs2]);
|
|
| 2543 | 2577 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2544 | 2578 |
break; |
| 2545 | 2579 |
case 0xcd: /* fstoq */ |
| 2546 | 2580 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2547 |
tcg_gen_helper_0_1(helper_fstoq, cpu_fpr[rs2]);
|
|
| 2581 |
gen_helper_fstoq(cpu_fpr[rs2]);
|
|
| 2548 | 2582 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2549 | 2583 |
break; |
| 2550 | 2584 |
case 0xce: /* fdtoq */ |
| 2551 | 2585 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2552 | 2586 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2553 |
tcg_gen_helper_0_0(helper_fdtoq);
|
|
| 2587 |
gen_helper_fdtoq();
|
|
| 2554 | 2588 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2555 | 2589 |
break; |
| 2556 | 2590 |
case 0xd1: /* fstoi */ |
| 2557 | 2591 |
gen_clear_float_exceptions(); |
| 2558 |
tcg_gen_helper_1_1(helper_fstoi, cpu_tmp32, |
|
| 2559 |
cpu_fpr[rs2]); |
|
| 2560 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
|
| 2592 |
gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]); |
|
| 2593 |
gen_helper_check_ieee_exceptions(); |
|
| 2561 | 2594 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2562 | 2595 |
break; |
| 2563 | 2596 |
case 0xd2: /* fdtoi */ |
| 2564 | 2597 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2565 | 2598 |
gen_clear_float_exceptions(); |
| 2566 |
tcg_gen_helper_1_0(helper_fdtoi, cpu_tmp32);
|
|
| 2567 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2599 |
gen_helper_fdtoi(cpu_tmp32);
|
|
| 2600 |
gen_helper_check_ieee_exceptions();
|
|
| 2568 | 2601 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2569 | 2602 |
break; |
| 2570 | 2603 |
case 0xd3: /* fqtoi */ |
| 2571 | 2604 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2572 | 2605 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2573 | 2606 |
gen_clear_float_exceptions(); |
| 2574 |
tcg_gen_helper_1_0(helper_fqtoi, cpu_tmp32);
|
|
| 2575 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2607 |
gen_helper_fqtoi(cpu_tmp32);
|
|
| 2608 |
gen_helper_check_ieee_exceptions();
|
|
| 2576 | 2609 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2577 | 2610 |
break; |
| 2578 | 2611 |
#ifdef TARGET_SPARC64 |
| ... | ... | |
| 2595 | 2628 |
break; |
| 2596 | 2629 |
case 0x6: /* V9 fnegd */ |
| 2597 | 2630 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2598 |
tcg_gen_helper_0_0(helper_fnegd);
|
|
| 2631 |
gen_helper_fnegd();
|
|
| 2599 | 2632 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2600 | 2633 |
break; |
| 2601 | 2634 |
case 0x7: /* V9 fnegq */ |
| 2602 | 2635 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2603 | 2636 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2604 |
tcg_gen_helper_0_0(helper_fnegq);
|
|
| 2637 |
gen_helper_fnegq();
|
|
| 2605 | 2638 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2606 | 2639 |
break; |
| 2607 | 2640 |
case 0xa: /* V9 fabsd */ |
| 2608 | 2641 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2609 |
tcg_gen_helper_0_0(helper_fabsd);
|
|
| 2642 |
gen_helper_fabsd();
|
|
| 2610 | 2643 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2611 | 2644 |
break; |
| 2612 | 2645 |
case 0xb: /* V9 fabsq */ |
| 2613 | 2646 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2614 | 2647 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2615 |
tcg_gen_helper_0_0(helper_fabsq);
|
|
| 2648 |
gen_helper_fabsq();
|
|
| 2616 | 2649 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2617 | 2650 |
break; |
| 2618 | 2651 |
case 0x81: /* V9 fstox */ |
| 2619 | 2652 |
gen_clear_float_exceptions(); |
| 2620 |
tcg_gen_helper_0_1(helper_fstox, cpu_fpr[rs2]);
|
|
| 2621 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2653 |
gen_helper_fstox(cpu_fpr[rs2]);
|
|
| 2654 |
gen_helper_check_ieee_exceptions();
|
|
| 2622 | 2655 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2623 | 2656 |
break; |
| 2624 | 2657 |
case 0x82: /* V9 fdtox */ |
| 2625 | 2658 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2626 | 2659 |
gen_clear_float_exceptions(); |
| 2627 |
tcg_gen_helper_0_0(helper_fdtox);
|
|
| 2628 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2660 |
gen_helper_fdtox();
|
|
| 2661 |
gen_helper_check_ieee_exceptions();
|
|
| 2629 | 2662 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2630 | 2663 |
break; |
| 2631 | 2664 |
case 0x83: /* V9 fqtox */ |
| 2632 | 2665 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2633 | 2666 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2634 | 2667 |
gen_clear_float_exceptions(); |
| 2635 |
tcg_gen_helper_0_0(helper_fqtox);
|
|
| 2636 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2668 |
gen_helper_fqtox();
|
|
| 2669 |
gen_helper_check_ieee_exceptions();
|
|
| 2637 | 2670 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2638 | 2671 |
break; |
| 2639 | 2672 |
case 0x84: /* V9 fxtos */ |
| 2640 | 2673 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2641 | 2674 |
gen_clear_float_exceptions(); |
| 2642 |
tcg_gen_helper_1_0(helper_fxtos, cpu_tmp32);
|
|
| 2643 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
|
|
| 2675 |
gen_helper_fxtos(cpu_tmp32);
|
|
| 2676 |
gen_helper_check_ieee_exceptions();
|
|
| 2644 | 2677 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2645 | 2678 |
break; |
| 2646 | 2679 |
case 0x88: /* V9 fxtod */ |
| 2647 | 2680 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2648 | 2681 |
gen_clear_float_exceptions(); |
| 2649 |
tcg_gen_helper_0_0(helper_fxtod); |
|
| 2650 |
tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
|
| 2682 |
gen_helper_fxtod(); |
|
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