Revision a7d3970d target-arm/translate.c
| b/target-arm/translate.c | ||
|---|---|---|
| 9454 | 9454 |
break; |
| 9455 | 9455 |
|
| 9456 | 9456 |
case 12: |
| 9457 |
{
|
|
| 9457 | 9458 |
/* load/store multiple */ |
| 9459 |
TCGv loaded_var; |
|
| 9460 |
TCGV_UNUSED(loaded_var); |
|
| 9458 | 9461 |
rn = (insn >> 8) & 0x7; |
| 9459 | 9462 |
addr = load_reg(s, rn); |
| 9460 | 9463 |
for (i = 0; i < 8; i++) {
|
| ... | ... | |
| 9462 | 9465 |
if (insn & (1 << 11)) {
|
| 9463 | 9466 |
/* load */ |
| 9464 | 9467 |
tmp = gen_ld32(addr, IS_USER(s)); |
| 9465 |
store_reg(s, i, tmp); |
|
| 9468 |
if (i == rn) {
|
|
| 9469 |
loaded_var = tmp; |
|
| 9470 |
} else {
|
|
| 9471 |
store_reg(s, i, tmp); |
|
| 9472 |
} |
|
| 9466 | 9473 |
} else {
|
| 9467 | 9474 |
/* store */ |
| 9468 | 9475 |
tmp = load_reg(s, i); |
| ... | ... | |
| 9472 | 9479 |
tcg_gen_addi_i32(addr, addr, 4); |
| 9473 | 9480 |
} |
| 9474 | 9481 |
} |
| 9475 |
/* Base register writeback. */ |
|
| 9476 | 9482 |
if ((insn & (1 << rn)) == 0) {
|
| 9483 |
/* base reg not in list: base register writeback */ |
|
| 9477 | 9484 |
store_reg(s, rn, addr); |
| 9478 | 9485 |
} else {
|
| 9486 |
/* base reg in list: if load, complete it now */ |
|
| 9487 |
if (insn & (1 << 11)) {
|
|
| 9488 |
store_reg(s, rn, loaded_var); |
|
| 9489 |
} |
|
| 9479 | 9490 |
tcg_temp_free_i32(addr); |
| 9480 | 9491 |
} |
| 9481 | 9492 |
break; |
| 9482 |
|
|
| 9493 |
} |
|
| 9483 | 9494 |
case 13: |
| 9484 | 9495 |
/* conditional branch or swi */ |
| 9485 | 9496 |
cond = (insn >> 8) & 0xf; |
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