Revision a8170e5e hw/escc.c
| b/hw/escc.c | ||
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| 463 | 463 |
qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
| 464 | 464 |
} |
| 465 | 465 |
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| 466 |
static void escc_mem_write(void *opaque, target_phys_addr_t addr,
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| 466 |
static void escc_mem_write(void *opaque, hwaddr addr,
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| 467 | 467 |
uint64_t val, unsigned size) |
| 468 | 468 |
{
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| 469 | 469 |
SerialState *serial = opaque; |
| ... | ... | |
| 565 | 565 |
} |
| 566 | 566 |
} |
| 567 | 567 |
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| 568 |
static uint64_t escc_mem_read(void *opaque, target_phys_addr_t addr,
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static uint64_t escc_mem_read(void *opaque, hwaddr addr,
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| 569 | 569 |
unsigned size) |
| 570 | 570 |
{
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| 571 | 571 |
SerialState *serial = opaque; |
| ... | ... | |
| 683 | 683 |
} |
| 684 | 684 |
}; |
| 685 | 685 |
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| 686 |
MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
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| 686 |
MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
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| 687 | 687 |
CharDriverState *chrA, CharDriverState *chrB, |
| 688 | 688 |
int clock, int it_shift) |
| 689 | 689 |
{
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| ... | ... | |
| 846 | 846 |
put_queue(s, 0); |
| 847 | 847 |
} |
| 848 | 848 |
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| 849 |
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
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| 849 |
void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
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| 850 | 850 |
int disabled, int clock, int it_shift) |
| 851 | 851 |
{
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| 852 | 852 |
DeviceState *dev; |
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