Revision a8170e5e hw/etraxfs_dma.c
| b/hw/etraxfs_dma.c | ||
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&& ctrl->channels[c].client; |
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} |
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static inline int fs_channel(target_phys_addr_t addr)
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static inline int fs_channel(hwaddr addr)
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{
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/* Every channel has a 0x2000 ctrl register map. */ |
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return addr >> 13; |
| ... | ... | |
| 221 | 221 |
#ifdef USE_THIS_DEAD_CODE |
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static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) |
| 223 | 223 |
{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
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hwaddr addr = channel_reg(ctrl, c, RW_GROUP);
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/* Load and decode. FIXME: handle endianness. */ |
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cpu_physical_memory_read (addr, |
| ... | ... | |
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static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) |
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
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hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
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/* Load and decode. FIXME: handle endianness. */ |
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cpu_physical_memory_read (addr, |
| ... | ... | |
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static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) |
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
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hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
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/* Load and decode. FIXME: handle endianness. */ |
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D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
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| ... | ... | |
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static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) |
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
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hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
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/* Encode and store. FIXME: handle endianness. */ |
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D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
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| ... | ... | |
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static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) |
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
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hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
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/* Encode and store. FIXME: handle endianness. */ |
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D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
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| ... | ... | |
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return 0; |
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} |
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static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
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static uint32_t dma_rinvalid (void *opaque, hwaddr addr)
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{
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hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
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return 0; |
| 580 | 580 |
} |
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static uint64_t |
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dma_read(void *opaque, target_phys_addr_t addr, unsigned int size)
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dma_read(void *opaque, hwaddr addr, unsigned int size)
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{
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struct fs_dma_ctrl *ctrl = opaque; |
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int c; |
| ... | ... | |
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} |
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static void |
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dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
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dma_winvalid (void *opaque, hwaddr addr, uint32_t value)
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{
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hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
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} |
| ... | ... | |
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} |
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static void |
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dma_write(void *opaque, target_phys_addr_t addr,
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dma_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size) |
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{
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struct fs_dma_ctrl *ctrl = opaque; |
| ... | ... | |
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qemu_bh_schedule_idle(etraxfs_dmac->bh); |
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} |
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void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
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void *etraxfs_dmac_init(hwaddr base, int nr_channels)
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{
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struct fs_dma_ctrl *ctrl = NULL; |
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