Revision a8170e5e hw/fdc.c
| b/hw/fdc.c | ||
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| 626 | 626 |
} |
| 627 | 627 |
} |
| 628 | 628 |
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static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
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| 629 |
static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
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| 630 | 630 |
unsigned ize) |
| 631 | 631 |
{
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| 632 | 632 |
return fdctrl_read(opaque, (uint32_t)reg); |
| 633 | 633 |
} |
| 634 | 634 |
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| 635 |
static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
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| 635 |
static void fdctrl_write_mem (void *opaque, hwaddr reg,
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| 636 | 636 |
uint64_t value, unsigned size) |
| 637 | 637 |
{
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| 638 | 638 |
fdctrl_write(opaque, (uint32_t)reg, value); |
| ... | ... | |
| 2032 | 2032 |
} |
| 2033 | 2033 |
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| 2034 | 2034 |
void fdctrl_init_sysbus(qemu_irq irq, int dma_chann, |
| 2035 |
target_phys_addr_t mmio_base, DriveInfo **fds)
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hwaddr mmio_base, DriveInfo **fds)
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| 2036 | 2036 |
{
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| 2037 | 2037 |
FDCtrl *fdctrl; |
| 2038 | 2038 |
DeviceState *dev; |
| ... | ... | |
| 2053 | 2053 |
sysbus_mmio_map(&sys->busdev, 0, mmio_base); |
| 2054 | 2054 |
} |
| 2055 | 2055 |
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| 2056 |
void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
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void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
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| 2057 | 2057 |
DriveInfo **fds, qemu_irq *fdc_tc) |
| 2058 | 2058 |
{
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| 2059 | 2059 |
DeviceState *dev; |
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