Revision a8170e5e hw/gt64xxx.c
| b/hw/gt64xxx.c | ||
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#define GT_PCI1_SERR1MASK (0xca8 >> 2) |
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#define PCI_MAPPING_ENTRY(regname) \ |
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target_phys_addr_t regname ##_start; \
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target_phys_addr_t regname ##_length; \
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hwaddr regname ##_start; \
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hwaddr regname ##_length; \
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MemoryRegion regname ##_mem |
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#define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120" |
| ... | ... | |
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/* Adjust range to avoid touching space which isn't mappable via PCI */ |
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/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 |
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0x1fc00000 - 0x1fd00000 */ |
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static void check_reserved_space (target_phys_addr_t *start,
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target_phys_addr_t *length)
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static void check_reserved_space (hwaddr *start,
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hwaddr *length)
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{
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target_phys_addr_t begin = *start;
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target_phys_addr_t end = *start + *length;
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hwaddr begin = *start;
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hwaddr end = *start + *length;
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if (end >= 0x1e000000LL && end < 0x1f100000LL) |
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end = 0x1e000000LL; |
| ... | ... | |
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static void gt64120_isd_mapping(GT64120State *s) |
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{
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target_phys_addr_t start = s->regs[GT_ISD] << 21;
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target_phys_addr_t length = 0x1000;
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hwaddr start = s->regs[GT_ISD] << 21;
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hwaddr length = 0x1000;
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if (s->ISD_length) {
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memory_region_del_subregion(get_system_memory(), &s->ISD_mem); |
| ... | ... | |
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} |
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} |
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static void gt64120_writel (void *opaque, target_phys_addr_t addr,
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static void gt64120_writel (void *opaque, hwaddr addr,
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uint64_t val, unsigned size) |
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{
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GT64120State *s = opaque; |
| ... | ... | |
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} |
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static uint64_t gt64120_readl (void *opaque, |
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target_phys_addr_t addr, unsigned size)
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hwaddr addr, unsigned size)
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{
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GT64120State *s = opaque; |
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PCIHostState *phb = PCI_HOST_BRIDGE(s); |
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