Revision a8170e5e hw/ide/mmio.c
b/hw/ide/mmio.c | ||
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47 | 47 |
ide_bus_reset(&s->bus); |
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} |
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static uint64_t mmio_ide_read(void *opaque, target_phys_addr_t addr,
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static uint64_t mmio_ide_read(void *opaque, hwaddr addr,
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51 | 51 |
unsigned size) |
52 | 52 |
{ |
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MMIOState *s = opaque; |
... | ... | |
58 | 58 |
return ide_data_readw(&s->bus, 0); |
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} |
60 | 60 |
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static void mmio_ide_write(void *opaque, target_phys_addr_t addr,
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static void mmio_ide_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size) |
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{ |
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MMIOState *s = opaque; |
... | ... | |
75 | 75 |
.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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static uint64_t mmio_ide_status_read(void *opaque, target_phys_addr_t addr,
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static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr,
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79 | 79 |
unsigned size) |
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{ |
81 | 81 |
MMIOState *s= opaque; |
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return ide_status_read(&s->bus, 0); |
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} |
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static void mmio_ide_cmd_write(void *opaque, target_phys_addr_t addr,
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static void mmio_ide_cmd_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size) |
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{ |
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MMIOState *s = opaque; |
... | ... | |
107 | 107 |
} |
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}; |
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void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
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void mmio_ide_init (hwaddr membase, hwaddr membase2,
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MemoryRegion *address_space, |
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qemu_irq irq, int shift, |
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DriveInfo *hd0, DriveInfo *hd1) |
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