/hw/kvm/pci-assign.c - Diff - qemu - Greek Research and Technology Network's projects

Revision a8170e5e hw/kvm/pci-assign.c

b/hw/kvm/pci-assign.c
133	133	int msi_virq_nr;
134	134	int *msi_virq;
135	135	MSIXTableEntry *msix_table;
136		target_phys_addr_t msix_table_addr;
	136	hwaddr msix_table_addr;
137	137	uint16_t msix_max;
138	138	MemoryRegion mmio;
139	139	char *configfd_name;
...	...
147	147	static void assigned_dev_unregister_msix_mmio(AssignedDevice *dev);
148	148
149	149	static uint64_t assigned_dev_ioport_rw(AssignedDevRegion *dev_region,
150		target_phys_addr_t addr, int size,
	150	hwaddr addr, int size,
151	151	uint64_t *data)
152	152	{
153	153	uint64_t val = 0;
...	...
206	206	return val;
207	207	}
208	208
209		static void assigned_dev_ioport_write(void *opaque, target_phys_addr_t addr,
	209	static void assigned_dev_ioport_write(void *opaque, hwaddr addr,
210	210	uint64_t data, unsigned size)
211	211	{
212	212	assigned_dev_ioport_rw(opaque, addr, size, &data);
213	213	}
214	214
215	215	static uint64_t assigned_dev_ioport_read(void *opaque,
216		target_phys_addr_t addr, unsigned size)
	216	hwaddr addr, unsigned size)
217	217	{
218	218	return assigned_dev_ioport_rw(opaque, addr, size, NULL);
219	219	}
220	220
221		static uint32_t slow_bar_readb(void *opaque, target_phys_addr_t addr)
	221	static uint32_t slow_bar_readb(void *opaque, hwaddr addr)
222	222	{
223	223	AssignedDevRegion *d = opaque;
224	224	uint8_t *in = d->u.r_virtbase + addr;
...	...
230	230	return r;
231	231	}
232	232
233		static uint32_t slow_bar_readw(void *opaque, target_phys_addr_t addr)
	233	static uint32_t slow_bar_readw(void *opaque, hwaddr addr)
234	234	{
235	235	AssignedDevRegion *d = opaque;
236	236	uint16_t in = (uint16_t )(d->u.r_virtbase + addr);
...	...
242	242	return r;
243	243	}
244	244
245		static uint32_t slow_bar_readl(void *opaque, target_phys_addr_t addr)
	245	static uint32_t slow_bar_readl(void *opaque, hwaddr addr)
246	246	{
247	247	AssignedDevRegion *d = opaque;
248	248	uint32_t in = (uint32_t )(d->u.r_virtbase + addr);
...	...
254	254	return r;
255	255	}
256	256
257		static void slow_bar_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
	257	static void slow_bar_writeb(void *opaque, hwaddr addr, uint32_t val)
258	258	{
259	259	AssignedDevRegion *d = opaque;
260	260	uint8_t *out = d->u.r_virtbase + addr;
...	...
263	263	*out = val;
264	264	}
265	265
266		static void slow_bar_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
	266	static void slow_bar_writew(void *opaque, hwaddr addr, uint32_t val)
267	267	{
268	268	AssignedDevRegion *d = opaque;
269	269	uint16_t out = (uint16_t )(d->u.r_virtbase + addr);
...	...
272	272	*out = val;
273	273	}
274	274
275		static void slow_bar_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	275	static void slow_bar_writel(void *opaque, hwaddr addr, uint32_t val)
276	276	{
277	277	AssignedDevRegion *d = opaque;
278	278	uint32_t out = (uint32_t )(d->u.r_virtbase + addr);
...	...
1499	1499	}
1500	1500
1501	1501	static uint64_t
1502		assigned_dev_msix_mmio_read(void *opaque, target_phys_addr_t addr,
	1502	assigned_dev_msix_mmio_read(void *opaque, hwaddr addr,
1503	1503	unsigned size)
1504	1504	{
1505	1505	AssignedDevice *adev = opaque;
...	...
1510	1510	return val;
1511	1511	}
1512	1512
1513		static void assigned_dev_msix_mmio_write(void *opaque, target_phys_addr_t addr,
	1513	static void assigned_dev_msix_mmio_write(void *opaque, hwaddr addr,
1514	1514	uint64_t val, unsigned size)
1515	1515	{
1516	1516	AssignedDevice *adev = opaque;

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Revision a8170e5e hw/kvm/pci-assign.c