Revision a8170e5e hw/lm32_boards.c
| b/hw/lm32_boards.c | ||
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| 32 | 32 |
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typedef struct {
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| 34 | 34 |
LM32CPU *cpu; |
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target_phys_addr_t bootstrap_pc;
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target_phys_addr_t flash_base;
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target_phys_addr_t hwsetup_base;
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target_phys_addr_t initrd_base;
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hwaddr bootstrap_pc;
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hwaddr flash_base;
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hwaddr hwsetup_base;
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hwaddr initrd_base;
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size_t initrd_size; |
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target_phys_addr_t cmdline_base;
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hwaddr cmdline_base;
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} ResetInfo; |
| 42 | 42 |
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static void cpu_irq_handler(void *opaque, int irq, int level) |
| ... | ... | |
| 83 | 83 |
int i; |
| 84 | 84 |
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/* memory map */ |
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target_phys_addr_t flash_base = 0x04000000;
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hwaddr flash_base = 0x04000000;
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size_t flash_sector_size = 256 * 1024; |
| 88 | 88 |
size_t flash_size = 32 * 1024 * 1024; |
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target_phys_addr_t ram_base = 0x08000000;
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hwaddr ram_base = 0x08000000;
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| 90 | 90 |
size_t ram_size = 64 * 1024 * 1024; |
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target_phys_addr_t timer0_base = 0x80002000;
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target_phys_addr_t uart0_base = 0x80006000;
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target_phys_addr_t timer1_base = 0x8000a000;
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hwaddr timer0_base = 0x80002000;
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hwaddr uart0_base = 0x80006000;
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hwaddr timer1_base = 0x8000a000;
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int uart0_irq = 0; |
| 95 | 95 |
int timer0_irq = 1; |
| 96 | 96 |
int timer1_irq = 3; |
| ... | ... | |
| 174 | 174 |
int i; |
| 175 | 175 |
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/* memory map */ |
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target_phys_addr_t flash_base = 0x04000000;
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hwaddr flash_base = 0x04000000;
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size_t flash_sector_size = 256 * 1024; |
| 179 | 179 |
size_t flash_size = 32 * 1024 * 1024; |
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target_phys_addr_t ram_base = 0x08000000;
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hwaddr ram_base = 0x08000000;
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size_t ram_size = 64 * 1024 * 1024; |
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target_phys_addr_t uart0_base = 0x80000000;
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target_phys_addr_t timer0_base = 0x80002000;
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target_phys_addr_t timer1_base = 0x80010000;
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target_phys_addr_t timer2_base = 0x80012000;
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hwaddr uart0_base = 0x80000000;
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hwaddr timer0_base = 0x80002000;
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hwaddr timer1_base = 0x80010000;
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hwaddr timer2_base = 0x80012000;
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| 186 | 186 |
int uart0_irq = 0; |
| 187 | 187 |
int timer0_irq = 1; |
| 188 | 188 |
int timer1_irq = 20; |
| 189 | 189 |
int timer2_irq = 21; |
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target_phys_addr_t hwsetup_base = 0x0bffe000;
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target_phys_addr_t cmdline_base = 0x0bfff000;
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target_phys_addr_t initrd_base = 0x08400000;
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hwaddr hwsetup_base = 0x0bffe000;
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hwaddr cmdline_base = 0x0bfff000;
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hwaddr initrd_base = 0x08400000;
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size_t initrd_max = 0x01000000; |
| 194 | 194 |
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reset_info = g_malloc0(sizeof(ResetInfo)); |
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