Archipelago » qemu

/* OMAP2 l4 Interconnect */

struct omap_l4_s;

struct omap_l4_region_s {

    size_t size;

    int access;

};

    struct omap_l4_s *bus;

    int regions;

    const struct omap_l4_region_s *start;

    uint32_t component;

    uint32_t control;

    uint32_t status;

};

struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,

struct omap_target_agent_s;

struct omap_target_agent_s *omap_l4ta_get(

    const struct omap_l4_region_s *regions,

    const struct omap_l4_agent_info_s *agents,

    int cs);

                                         int region, MemoryRegion *mr);

                                       int region);

                                       int region);

/* OMAP2 SDRAM controller */

struct omap_sdrc_s;

struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,

void omap_sdrc_reset(struct omap_sdrc_s *s);

/* OMAP2 general purpose memory controller */

struct omap_gpmc_s;

struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,

                                   qemu_irq irq, qemu_irq drq);

void omap_gpmc_reset(struct omap_gpmc_s *s);

void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);

};

struct soc_dma_s;

                MemoryRegion *sysmem,

                qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,

                enum omap_dma_model model);

                MemoryRegion *sysmem,

                struct omap_mpu_state_s *mpu, int fifo,

                int chans, omap_clk iclk, omap_clk fclk);

/* Only used in OMAP DMA 3.x gigacells */

struct omap_dma_lcd_channel_s {

    enum omap_dma_port src;

    /* Used in OMAP DMA 3.2 gigacell */

    unsigned char brust_f1;

    int dual;

    int current_frame;

    qemu_irq irq;

    struct omap_mpu_state_s *mpu;

} *omap_dma_get_lcdch(struct soc_dma_s *s);

void omap_synctimer_reset(struct omap_synctimer_s *s);

struct omap_uart_s;

                qemu_irq irq, omap_clk fclk, omap_clk iclk,

                qemu_irq txdma, qemu_irq rxdma,

                const char *label, CharDriverState *chr);

struct omap_lcd_panel_s;

void omap_lcdc_reset(struct omap_lcd_panel_s *s);

struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,

                                        qemu_irq irq,

                                        struct omap_dma_lcd_channel_s *dma,

                                        omap_clk clk);

void omap_dss_reset(struct omap_dss_s *s);

struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,

                MemoryRegion *sysmem,

                qemu_irq irq, qemu_irq drq,

                omap_clk fck1, omap_clk fck2, omap_clk ck54m,

                omap_clk ick1, omap_clk ick2);

/* omap_mmc.c */

struct omap_mmc_s;

                MemoryRegion *sysmem,

                BlockDriverState *bd,

                qemu_irq irq, qemu_irq dma[], omap_clk clk);

    struct omap_dma_port_if_s {

        uint32_t (*read[3])(struct omap_mpu_state_s *s,

        void (*write[3])(struct omap_mpu_state_s *s,

        int (*addr_valid)(struct omap_mpu_state_s *s,

    } port[__omap_dma_port_last];

    unsigned long sdram_size;

                unsigned long sdram_size,

                const char *core);

                uint32_t value);

                uint32_t value);

                uint32_t value);

void omap_mpu_wakeup(void *opaque, int irq, int req);