/hw/omap1.c - Diff - qemu - Greek Research and Technology Network's projects

Revision a8170e5e hw/omap1.c

b/hw/omap1.c
26	26	#include "sysbus.h"
27	27
28	28	/* Should signal the TCMI/GPMC */
29		uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
	29	uint32_t omap_badwidth_read8(void *opaque, hwaddr addr)
30	30	{
31	31	uint8_t ret;
32	32
...	...
35	35	return ret;
36	36	}
37	37
38		void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
	38	void omap_badwidth_write8(void *opaque, hwaddr addr,
39	39	uint32_t value)
40	40	{
41	41	uint8_t val8 = value;
...	...
44	44	cpu_physical_memory_write(addr, (void *) &val8, 1);
45	45	}
46	46
47		uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
	47	uint32_t omap_badwidth_read16(void *opaque, hwaddr addr)
48	48	{
49	49	uint16_t ret;
50	50
...	...
53	53	return ret;
54	54	}
55	55
56		void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
	56	void omap_badwidth_write16(void *opaque, hwaddr addr,
57	57	uint32_t value)
58	58	{
59	59	uint16_t val16 = value;
...	...
62	62	cpu_physical_memory_write(addr, (void *) &val16, 2);
63	63	}
64	64
65		uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
	65	uint32_t omap_badwidth_read32(void *opaque, hwaddr addr)
66	66	{
67	67	uint32_t ret;
68	68
...	...
71	71	return ret;
72	72	}
73	73
74		void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
	74	void omap_badwidth_write32(void *opaque, hwaddr addr,
75	75	uint32_t value)
76	76	{
77	77	OMAP_32B_REG(addr);
...	...
176	176	timer->rate = omap_clk_getrate(timer->clk);
177	177	}
178	178
179		static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr,
	179	static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
180	180	unsigned size)
181	181	{
182	182	struct omap_mpu_timer_s s = (struct omap_mpu_timer_s ) opaque;
...	...
200	200	return 0;
201	201	}
202	202
203		static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
	203	static void omap_mpu_timer_write(void *opaque, hwaddr addr,
204	204	uint64_t value, unsigned size)
205	205	{
206	206	struct omap_mpu_timer_s s = (struct omap_mpu_timer_s ) opaque;
...	...
251	251	}
252	252
253	253	static struct omap_mpu_timer_s omap_mpu_timer_init(MemoryRegion system_memory,
254		target_phys_addr_t base,
	254	hwaddr base,
255	255	qemu_irq irq, omap_clk clk)
256	256	{
257	257	struct omap_mpu_timer_s s = (struct omap_mpu_timer_s )
...	...
282	282	int reset;
283	283	};
284	284
285		static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr,
	285	static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
286	286	unsigned size)
287	287	{
288	288	struct omap_watchdog_timer_s s = (struct omap_watchdog_timer_s ) opaque;
...	...
307	307	return 0;
308	308	}
309	309
310		static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
	310	static void omap_wd_timer_write(void *opaque, hwaddr addr,
311	311	uint64_t value, unsigned size)
312	312	{
313	313	struct omap_watchdog_timer_s s = (struct omap_watchdog_timer_s ) opaque;
...	...
380	380	}
381	381
382	382	static struct omap_watchdog_timer_s omap_wd_timer_init(MemoryRegion memory,
383		target_phys_addr_t base,
	383	hwaddr base,
384	384	qemu_irq irq, omap_clk clk)
385	385	{
386	386	struct omap_watchdog_timer_s s = (struct omap_watchdog_timer_s )
...	...
405	405	MemoryRegion iomem;
406	406	};
407	407
408		static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,
	408	static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
409	409	unsigned size)
410	410	{
411	411	struct omap_32khz_timer_s s = (struct omap_32khz_timer_s ) opaque;
...	...
432	432	return 0;
433	433	}
434	434
435		static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
	435	static void omap_os_timer_write(void *opaque, hwaddr addr,
436	436	uint64_t value, unsigned size)
437	437	{
438	438	struct omap_32khz_timer_s s = (struct omap_32khz_timer_s ) opaque;
...	...
486	486	}
487	487
488	488	static struct omap_32khz_timer_s omap_os_timer_init(MemoryRegion memory,
489		target_phys_addr_t base,
	489	hwaddr base,
490	490	qemu_irq irq, omap_clk clk)
491	491	{
492	492	struct omap_32khz_timer_s s = (struct omap_32khz_timer_s )
...	...
506	506	}
507	507
508	508	/* Ultra Low-Power Device Module */
509		static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr,
	509	static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
510	510	unsigned size)
511	511	{
512	512	struct omap_mpu_state_s s = (struct omap_mpu_state_s ) opaque;
...	...
573	573	omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
574	574	}
575	575
576		static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
	576	static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
577	577	uint64_t value, unsigned size)
578	578	{
579	579	struct omap_mpu_state_s s = (struct omap_mpu_state_s ) opaque;
...	...
726	726	}
727	727
728	728	static void omap_ulpd_pm_init(MemoryRegion *system_memory,
729		target_phys_addr_t base,
	729	hwaddr base,
730	730	struct omap_mpu_state_s *mpu)
731	731	{
732	732	memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
...	...
736	736	}
737	737
738	738	/* OMAP Pin Configuration */
739		static uint64_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr,
	739	static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
740	740	unsigned size)
741	741	{
742	742	struct omap_mpu_state_s s = (struct omap_mpu_state_s ) opaque;
...	...
843	843	omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
844	844	}
845	845
846		static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
	846	static void omap_pin_cfg_write(void *opaque, hwaddr addr,
847	847	uint64_t value, unsigned size)
848	848	{
849	849	struct omap_mpu_state_s s = (struct omap_mpu_state_s ) opaque;
...	...
944	944	}
945	945
946	946	static void omap_pin_cfg_init(MemoryRegion *system_memory,
947		target_phys_addr_t base,
	947	hwaddr base,
948	948	struct omap_mpu_state_s *mpu)
949	949	{
950	950	memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
...	...
954	954	}
955	955
956	956	/* Device Identification, Die Identification */
957		static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr,
	957	static uint64_t omap_id_read(void *opaque, hwaddr addr,
958	958	unsigned size)
959	959	{
960	960	struct omap_mpu_state_s s = (struct omap_mpu_state_s ) opaque;
...	...
1001	1001	return 0;
1002	1002	}
1003	1003
1004		static void omap_id_write(void *opaque, target_phys_addr_t addr,
	1004	static void omap_id_write(void *opaque, hwaddr addr,
1005	1005	uint64_t value, unsigned size)
1006	1006	{
1007	1007	if (size != 4) {
...	...
1035	1035	}
1036	1036
1037	1037	/* MPUI Control (Dummy) */
1038		static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr,
	1038	static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
1039	1039	unsigned size)
1040	1040	{
1041	1041	struct omap_mpu_state_s s = (struct omap_mpu_state_s ) opaque;
...	...
1068	1068	return 0;
1069	1069	}
1070	1070
1071		static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
	1071	static void omap_mpui_write(void *opaque, hwaddr addr,
1072	1072	uint64_t value, unsigned size)
1073	1073	{
1074	1074	struct omap_mpu_state_s s = (struct omap_mpu_state_s ) opaque;
...	...
1109	1109	s->mpui_ctrl = 0x0003ff1b;
1110	1110	}
1111	1111
1112		static void omap_mpui_init(MemoryRegion *memory, target_phys_addr_t base,
	1112	static void omap_mpui_init(MemoryRegion *memory, hwaddr base,
1113	1113	struct omap_mpu_state_s *mpu)
1114	1114	{
1115	1115	memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
...	...
1131	1131	uint16_t enh_control;
1132	1132	};
1133	1133
1134		static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr,
	1134	static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
1135	1135	unsigned size)
1136	1136	{
1137	1137	struct omap_tipb_bridge_s s = (struct omap_tipb_bridge_s ) opaque;
...	...
1161	1161	return 0;
1162	1162	}
1163	1163
1164		static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
	1164	static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
1165	1165	uint64_t value, unsigned size)
1166	1166	{
1167	1167	struct omap_tipb_bridge_s s = (struct omap_tipb_bridge_s ) opaque;
...	...
1215	1215	}
1216	1216
1217	1217	static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
1218		MemoryRegion *memory, target_phys_addr_t base,
	1218	MemoryRegion *memory, hwaddr base,
1219	1219	qemu_irq abort_irq, omap_clk clk)
1220	1220	{
1221	1221	struct omap_tipb_bridge_s s = (struct omap_tipb_bridge_s )
...	...
1232	1232	}
1233	1233
1234	1234	/* Dummy Traffic Controller's Memory Interface */
1235		static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr,
	1235	static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
1236	1236	unsigned size)
1237	1237	{
1238	1238	struct omap_mpu_state_s s = (struct omap_mpu_state_s ) opaque;
...	...
1270	1270	return 0;
1271	1271	}
1272	1272
1273		static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
	1273	static void omap_tcmi_write(void *opaque, hwaddr addr,
1274	1274	uint64_t value, unsigned size)
1275	1275	{
1276	1276	struct omap_mpu_state_s s = (struct omap_mpu_state_s ) opaque;
...	...
1330	1330	mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1331	1331	}
1332	1332
1333		static void omap_tcmi_init(MemoryRegion *memory, target_phys_addr_t base,
	1333	static void omap_tcmi_init(MemoryRegion *memory, hwaddr base,
1334	1334	struct omap_mpu_state_s *mpu)
1335	1335	{
1336	1336	memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu,
...	...
1346	1346	omap_clk dpll;
1347	1347	};
1348	1348
1349		static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr,
	1349	static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
1350	1350	unsigned size)
1351	1351	{
1352	1352	struct dpll_ctl_s s = (struct dpll_ctl_s ) opaque;
...	...
1362	1362	return 0;
1363	1363	}
1364	1364
1365		static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
	1365	static void omap_dpll_write(void *opaque, hwaddr addr,
1366	1366	uint64_t value, unsigned size)
1367	1367	{
1368	1368	struct dpll_ctl_s s = (struct dpll_ctl_s ) opaque;
...	...
1412	1412	}
1413	1413
1414	1414	static struct dpll_ctl_s omap_dpll_init(MemoryRegion memory,
1415		target_phys_addr_t base, omap_clk clk)
	1415	hwaddr base, omap_clk clk)
1416	1416	{
1417	1417	struct dpll_ctl_s s = g_malloc0(sizeof(s));
1418	1418	memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
...	...
1425	1425	}
1426	1426
1427	1427	/* MPU Clock/Reset/Power Mode Control */
1428		static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr,
	1428	static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
1429	1429	unsigned size)
1430	1430	{
1431	1431	struct omap_mpu_state_s s = (struct omap_mpu_state_s ) opaque;
...	...
1627	1627	}
1628	1628	}
1629	1629
1630		static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
	1630	static void omap_clkm_write(void *opaque, hwaddr addr,
1631	1631	uint64_t value, unsigned size)
1632	1632	{
1633	1633	struct omap_mpu_state_s s = (struct omap_mpu_state_s ) opaque;
...	...
1714	1714	.endianness = DEVICE_NATIVE_ENDIAN,
1715	1715	};
1716	1716
1717		static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr,
	1717	static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
1718	1718	unsigned size)
1719	1719	{
1720	1720	struct omap_mpu_state_s s = (struct omap_mpu_state_s ) opaque;
...	...
1758	1758	SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
1759	1759	}
1760	1760
1761		static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
	1761	static void omap_clkdsp_write(void *opaque, hwaddr addr,
1762	1762	uint64_t value, unsigned size)
1763	1763	{
1764	1764	struct omap_mpu_state_s s = (struct omap_mpu_state_s ) opaque;
...	...
1823	1823	s->clkm.dsp_rstct2 = 0x0000;
1824	1824	}
1825	1825
1826		static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base,
1827		target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
	1826	static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base,
	1827	hwaddr dsp_base, struct omap_mpu_state_s *s)
1828	1828	{
1829	1829	memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s,
1830	1830	"omap-clkm", 0x100);
...	...
1903	1903	s->row_latch = ~rows;
1904	1904	}
1905	1905
1906		static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr,
	1906	static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
1907	1907	unsigned size)
1908	1908	{
1909	1909	struct omap_mpuio_s s = (struct omap_mpuio_s ) opaque;
...	...
1963	1963	return 0;
1964	1964	}
1965	1965
1966		static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
	1966	static void omap_mpuio_write(void *opaque, hwaddr addr,
1967	1967	uint64_t value, unsigned size)
1968	1968	{
1969	1969	struct omap_mpuio_s s = (struct omap_mpuio_s ) opaque;
...	...
2072	2072	}
2073	2073
2074	2074	static struct omap_mpuio_s omap_mpuio_init(MemoryRegion memory,
2075		target_phys_addr_t base,
	2075	hwaddr base,
2076	2076	qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
2077	2077	omap_clk clk)
2078	2078	{
...	...
2159	2159	}
2160	2160	}
2161	2161
2162		static uint64_t omap_uwire_read(void *opaque, target_phys_addr_t addr,
	2162	static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
2163	2163	unsigned size)
2164	2164	{
2165	2165	struct omap_uwire_s s = (struct omap_uwire_s ) opaque;
...	...
2193	2193	return 0;
2194	2194	}
2195	2195
2196		static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
	2196	static void omap_uwire_write(void *opaque, hwaddr addr,
2197	2197	uint64_t value, unsigned size)
2198	2198	{
2199	2199	struct omap_uwire_s s = (struct omap_uwire_s ) opaque;
...	...
2263	2263	}
2264	2264
2265	2265	static struct omap_uwire_s omap_uwire_init(MemoryRegion system_memory,
2266		target_phys_addr_t base,
	2266	hwaddr base,
2267	2267	qemu_irq txirq, qemu_irq rxirq,
2268	2268	qemu_irq dma,
2269	2269	omap_clk clk)
...	...
2312	2312	}
2313	2313	}
2314	2314
2315		static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr,
	2315	static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
2316	2316	unsigned size)
2317	2317	{
2318	2318	struct omap_pwl_s s = (struct omap_pwl_s ) opaque;
...	...
2332	2332	return 0;
2333	2333	}
2334	2334
2335		static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
	2335	static void omap_pwl_write(void *opaque, hwaddr addr,
2336	2336	uint64_t value, unsigned size)
2337	2337	{
2338	2338	struct omap_pwl_s s = (struct omap_pwl_s ) opaque;
...	...
2381	2381	}
2382	2382
2383	2383	static struct omap_pwl_s omap_pwl_init(MemoryRegion system_memory,
2384		target_phys_addr_t base,
	2384	hwaddr base,
2385	2385	omap_clk clk)
2386	2386	{
2387	2387	struct omap_pwl_s s = g_malloc0(sizeof(s));
...	...
2405	2405	omap_clk clk;
2406	2406	};
2407	2407
2408		static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr,
	2408	static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
2409	2409	unsigned size)
2410	2410	{
2411	2411	struct omap_pwt_s s = (struct omap_pwt_s ) opaque;
...	...
2427	2427	return 0;
2428	2428	}
2429	2429
2430		static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
	2430	static void omap_pwt_write(void *opaque, hwaddr addr,
2431	2431	uint64_t value, unsigned size)
2432	2432	{
2433	2433	struct omap_pwt_s s = (struct omap_pwt_s ) opaque;
...	...
2488	2488	}
2489	2489
2490	2490	static struct omap_pwt_s omap_pwt_init(MemoryRegion system_memory,
2491		target_phys_addr_t base,
	2491	hwaddr base,
2492	2492	omap_clk clk)
2493	2493	{
2494	2494	struct omap_pwt_s s = g_malloc0(sizeof(s));
...	...
2536	2536	printf("%s: conversion failed\n", __FUNCTION__);
2537	2537	}
2538	2538
2539		static uint64_t omap_rtc_read(void *opaque, target_phys_addr_t addr,
	2539	static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
2540	2540	unsigned size)
2541	2541	{
2542	2542	struct omap_rtc_s s = (struct omap_rtc_s ) opaque;
...	...
2618	2618	return 0;
2619	2619	}
2620	2620
2621		static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
	2621	static void omap_rtc_write(void *opaque, hwaddr addr,
2622	2622	uint64_t value, unsigned size)
2623	2623	{
2624	2624	struct omap_rtc_s s = (struct omap_rtc_s ) opaque;
...	...
2901	2901	}
2902	2902
2903	2903	static struct omap_rtc_s omap_rtc_init(MemoryRegion system_memory,
2904		target_phys_addr_t base,
	2904	hwaddr base,
2905	2905	qemu_irq timerirq, qemu_irq alarmirq,
2906	2906	omap_clk clk)
2907	2907	{
...	...
3129	3129	omap_mcbsp_rx_stop(s);
3130	3130	}
3131	3131
3132		static uint64_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr,
	3132	static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
3133	3133	unsigned size)
3134	3134	{
3135	3135	struct omap_mcbsp_s s = (struct omap_mcbsp_s ) opaque;
...	...
3227	3227	return 0;
3228	3228	}
3229	3229
3230		static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
	3230	static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
3231	3231	uint32_t value)
3232	3232	{
3233	3233	struct omap_mcbsp_s s = (struct omap_mcbsp_s ) opaque;
...	...
3365	3365	OMAP_BAD_REG(addr);
3366	3366	}
3367	3367
3368		static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
	3368	static void omap_mcbsp_writew(void *opaque, hwaddr addr,
3369	3369	uint32_t value)
3370	3370	{
3371	3371	struct omap_mcbsp_s s = (struct omap_mcbsp_s ) opaque;
...	...
3396	3396	omap_badwidth_write16(opaque, addr, value);
3397	3397	}
3398	3398
3399		static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr,
	3399	static void omap_mcbsp_write(void *opaque, hwaddr addr,
3400	3400	uint64_t value, unsigned size)
3401	3401	{
3402	3402	switch (size) {
...	...
3432	3432	}
3433	3433
3434	3434	static struct omap_mcbsp_s omap_mcbsp_init(MemoryRegion system_memory,
3435		target_phys_addr_t base,
	3435	hwaddr base,
3436	3436	qemu_irq txirq, qemu_irq rxirq,
3437	3437	qemu_irq *dma, omap_clk clk)
3438	3438	{
...	...
3547	3547	omap_lpg_update(s);
3548	3548	}
3549	3549
3550		static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr,
	3550	static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
3551	3551	unsigned size)
3552	3552	{
3553	3553	struct omap_lpg_s s = (struct omap_lpg_s ) opaque;
...	...
3569	3569	return 0;
3570	3570	}
3571	3571
3572		static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
	3572	static void omap_lpg_write(void *opaque, hwaddr addr,
3573	3573	uint64_t value, unsigned size)
3574	3574	{
3575	3575	struct omap_lpg_s s = (struct omap_lpg_s ) opaque;
...	...
3613	3613	}
3614	3614
3615	3615	static struct omap_lpg_s omap_lpg_init(MemoryRegion system_memory,
3616		target_phys_addr_t base, omap_clk clk)
	3616	hwaddr base, omap_clk clk)
3617	3617	{
3618	3618	struct omap_lpg_s s = (struct omap_lpg_s )
3619	3619	g_malloc0(sizeof(struct omap_lpg_s));
...	...
3631	3631	}
3632	3632
3633	3633	/* MPUI Peripheral Bridge configuration */
3634		static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr,
	3634	static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr,
3635	3635	unsigned size)
3636	3636	{
3637	3637	if (size != 2) {
...	...
3645	3645	return 0;
3646	3646	}
3647	3647
3648		static void omap_mpui_io_write(void *opaque, target_phys_addr_t addr,
	3648	static void omap_mpui_io_write(void *opaque, hwaddr addr,
3649	3649	uint64_t value, unsigned size)
3650	3650	{
3651	3651	/* FIXME: infinite loop */
...	...
3706	3706	}
3707	3707
3708	3708	static const struct omap_map_s {
3709		target_phys_addr_t phys_dsp;
3710		target_phys_addr_t phys_mpu;
	3709	hwaddr phys_dsp;
	3710	hwaddr phys_mpu;
3711	3711	uint32_t size;
3712	3712	const char *name;
3713	3713	} omap15xx_dsp_mm[] = {
...	...
3778	3778
3779	3779	/* DMA ports for OMAP1 */
3780	3780	static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
3781		target_phys_addr_t addr)
	3781	hwaddr addr)
3782	3782	{
3783	3783	return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
3784	3784	}
3785	3785
3786	3786	static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
3787		target_phys_addr_t addr)
	3787	hwaddr addr)
3788	3788	{
3789	3789	return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE,
3790	3790	addr);
3791	3791	}
3792	3792
3793	3793	static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
3794		target_phys_addr_t addr)
	3794	hwaddr addr)
3795	3795	{
3796	3796	return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
3797	3797	}
3798	3798
3799	3799	static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
3800		target_phys_addr_t addr)
	3800	hwaddr addr)
3801	3801	{
3802	3802	return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr);
3803	3803	}
3804	3804
3805	3805	static int omap_validate_local_addr(struct omap_mpu_state_s *s,
3806		target_phys_addr_t addr)
	3806	hwaddr addr)
3807	3807	{
3808	3808	return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr);
3809	3809	}
3810	3810
3811	3811	static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
3812		target_phys_addr_t addr)
	3812	hwaddr addr)
3813	3813	{
3814	3814	return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
3815	3815	}

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Archipelago » qemu

Revision a8170e5e hw/omap1.c