Revision a8170e5e hw/omap_dma.c
b/hw/omap_dma.c | ||
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31 | 31 |
int endian_lock[2]; |
32 | 32 |
int translate[2]; |
33 | 33 |
enum omap_dma_port port[2]; |
34 |
target_phys_addr_t addr[2];
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34 |
hwaddr addr[2];
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35 | 35 |
omap_dma_addressing_t mode[2]; |
36 | 36 |
uint32_t elements; |
37 | 37 |
uint16_t frames; |
... | ... | |
78 | 78 |
struct omap_dma_channel_s *sibling; |
79 | 79 |
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80 | 80 |
struct omap_dma_reg_set_s { |
81 |
target_phys_addr_t src, dest;
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81 |
hwaddr src, dest;
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82 | 82 |
int frame; |
83 | 83 |
int element; |
84 | 84 |
int pck_element; |
... | ... | |
914 | 914 |
break; |
915 | 915 |
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916 | 916 |
case 0x06: /* SYS_DMA_CSR_CH0 */ |
917 |
OMAP_RO_REG((target_phys_addr_t) reg);
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917 |
OMAP_RO_REG((hwaddr) reg);
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918 | 918 |
break; |
919 | 919 |
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920 | 920 |
case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
... | ... | |
954 | 954 |
break; |
955 | 955 |
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956 | 956 |
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ |
957 |
OMAP_RO_REG((target_phys_addr_t) reg);
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957 |
OMAP_RO_REG((hwaddr) reg);
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958 | 958 |
break; |
959 | 959 |
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960 | 960 |
case 0x1c: /* DMA_CDEI */ |
... | ... | |
1446 | 1446 |
return 0; |
1447 | 1447 |
} |
1448 | 1448 |
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1449 |
static uint64_t omap_dma_read(void *opaque, target_phys_addr_t addr,
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1449 |
static uint64_t omap_dma_read(void *opaque, hwaddr addr,
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1450 | 1450 |
unsigned size) |
1451 | 1451 |
{ |
1452 | 1452 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
... | ... | |
1494 | 1494 |
return 0; |
1495 | 1495 |
} |
1496 | 1496 |
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1497 |
static void omap_dma_write(void *opaque, target_phys_addr_t addr,
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1497 |
static void omap_dma_write(void *opaque, hwaddr addr,
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1498 | 1498 |
uint64_t value, unsigned size) |
1499 | 1499 |
{ |
1500 | 1500 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
... | ... | |
1618 | 1618 |
} |
1619 | 1619 |
} |
1620 | 1620 |
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1621 |
struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
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1621 |
struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
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1622 | 1622 |
MemoryRegion *sysmem, |
1623 | 1623 |
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, |
1624 | 1624 |
enum omap_dma_model model) |
... | ... | |
1692 | 1692 |
qemu_irq_raise(s->irq[3]); |
1693 | 1693 |
} |
1694 | 1694 |
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1695 |
static uint64_t omap_dma4_read(void *opaque, target_phys_addr_t addr,
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1695 |
static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
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1696 | 1696 |
unsigned size) |
1697 | 1697 |
{ |
1698 | 1698 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
... | ... | |
1842 | 1842 |
} |
1843 | 1843 |
} |
1844 | 1844 |
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1845 |
static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
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1845 |
static void omap_dma4_write(void *opaque, hwaddr addr,
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1846 | 1846 |
uint64_t value, unsigned size) |
1847 | 1847 |
{ |
1848 | 1848 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
... | ... | |
1988 | 1988 |
break; |
1989 | 1989 |
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1990 | 1990 |
case 0x1c: /* DMA4_CSSA */ |
1991 |
ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
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1991 |
ch->addr[0] = (hwaddr) (uint32_t) value;
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1992 | 1992 |
ch->set_update = 1; |
1993 | 1993 |
break; |
1994 | 1994 |
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1995 | 1995 |
case 0x20: /* DMA4_CDSA */ |
1996 |
ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
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1996 |
ch->addr[1] = (hwaddr) (uint32_t) value;
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1997 | 1997 |
ch->set_update = 1; |
1998 | 1998 |
break; |
1999 | 1999 |
|
... | ... | |
2040 | 2040 |
.endianness = DEVICE_NATIVE_ENDIAN, |
2041 | 2041 |
}; |
2042 | 2042 |
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2043 |
struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
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2043 |
struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
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2044 | 2044 |
MemoryRegion *sysmem, |
2045 | 2045 |
struct omap_mpu_state_s *mpu, int fifo, |
2046 | 2046 |
int chans, omap_clk iclk, omap_clk fclk) |
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