/hw/openpic.c - Diff - qemu - Greek Research and Technology Network's projects

Revision a8170e5e hw/openpic.c

b/hw/openpic.c
178	178	return cpu_single_env->cpu_index;
179	179	}
180	180
181		static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
	181	static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
182	182	int idx);
183		static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
	183	static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
184	184	uint32_t val, int idx);
185	185
186	186	enum {
...	...
596	596	#endif
597	597	#endif /* 0 : Code provision for Intel model */
598	598
599		static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t val)
	599	static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val)
600	600	{
601	601	openpic_t *opp = opaque;
602	602	IRQ_dst_t *dst;
...	...
662	662	}
663	663	}
664	664
665		static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
	665	static uint32_t openpic_gbl_read (void *opaque, hwaddr addr)
666	666	{
667	667	openpic_t *opp = opaque;
668	668	uint32_t retval;
...	...
826	826	return retval;
827	827	}
828	828
829		static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
	829	static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
830	830	uint32_t val, int idx)
831	831	{
832	832	openpic_t *opp = opaque;
...	...
886	886	}
887	887	}
888	888
889		static void openpic_cpu_write(void *opaque, target_phys_addr_t addr, uint32_t val)
	889	static void openpic_cpu_write(void *opaque, hwaddr addr, uint32_t val)
890	890	{
891	891	openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
892	892	}
893	893
894		static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
	894	static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
895	895	int idx)
896	896	{
897	897	openpic_t *opp = opaque;
...	...
970	970	return retval;
971	971	}
972	972
973		static uint32_t openpic_cpu_read(void *opaque, target_phys_addr_t addr)
	973	static uint32_t openpic_cpu_read(void *opaque, hwaddr addr)
974	974	{
975	975	return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
976	976	}
977	977
978	978	static void openpic_buggy_write (void *opaque,
979		target_phys_addr_t addr, uint32_t val)
	979	hwaddr addr, uint32_t val)
980	980	{
981	981	printf("Invalid OPENPIC write access !\n");
982	982	}
983	983
984		static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
	984	static uint32_t openpic_buggy_read (void *opaque, hwaddr addr)
985	985	{
986	986	printf("Invalid OPENPIC read access !\n");
987	987
...	...
989	989	}
990	990
991	991	static void openpic_writel (void *opaque,
992		target_phys_addr_t addr, uint32_t val)
	992	hwaddr addr, uint32_t val)
993	993	{
994	994	openpic_t *opp = opaque;
995	995
...	...
1010	1010	}
1011	1011	}
1012	1012
1013		static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
	1013	static uint32_t openpic_readl (void *opaque,hwaddr addr)
1014	1014	{
1015	1015	openpic_t *opp = opaque;
1016	1016	uint32_t retval;
...	...
1034	1034	return retval;
1035	1035	}
1036	1036
1037		static uint64_t openpic_read(void *opaque, target_phys_addr_t addr,
	1037	static uint64_t openpic_read(void *opaque, hwaddr addr,
1038	1038	unsigned size)
1039	1039	{
1040	1040	openpic_t *opp = opaque;
...	...
1045	1045	}
1046	1046	}
1047	1047
1048		static void openpic_write(void *opaque, target_phys_addr_t addr,
	1048	static void openpic_write(void *opaque, hwaddr addr,
1049	1049	uint64_t data, unsigned size)
1050	1050	{
1051	1051	openpic_t *opp = opaque;
...	...
1300	1300	mpp->glbc = 0x00000000;
1301	1301	}
1302	1302
1303		static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t val)
	1303	static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val)
1304	1304	{
1305	1305	openpic_t *mpp = opaque;
1306	1306	int idx, cpu;
...	...
1333	1333	}
1334	1334	}
1335	1335
1336		static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr)
	1336	static uint32_t mpic_timer_read (void *opaque, hwaddr addr)
1337	1337	{
1338	1338	openpic_t *mpp = opaque;
1339	1339	uint32_t retval;
...	...
1368	1368	return retval;
1369	1369	}
1370	1370
1371		static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
	1371	static void mpic_src_ext_write (void *opaque, hwaddr addr,
1372	1372	uint32_t val)
1373	1373	{
1374	1374	openpic_t *mpp = opaque;
...	...
1390	1390	}
1391	1391	}
1392	1392
1393		static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr)
	1393	static uint32_t mpic_src_ext_read (void *opaque, hwaddr addr)
1394	1394	{
1395	1395	openpic_t *mpp = opaque;
1396	1396	uint32_t retval;
...	...
1416	1416	return retval;
1417	1417	}
1418	1418
1419		static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
	1419	static void mpic_src_int_write (void *opaque, hwaddr addr,
1420	1420	uint32_t val)
1421	1421	{
1422	1422	openpic_t *mpp = opaque;
...	...
1438	1438	}
1439	1439	}
1440	1440
1441		static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr)
	1441	static uint32_t mpic_src_int_read (void *opaque, hwaddr addr)
1442	1442	{
1443	1443	openpic_t *mpp = opaque;
1444	1444	uint32_t retval;
...	...
1464	1464	return retval;
1465	1465	}
1466	1466
1467		static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
	1467	static void mpic_src_msg_write (void *opaque, hwaddr addr,
1468	1468	uint32_t val)
1469	1469	{
1470	1470	openpic_t *mpp = opaque;
...	...
1486	1486	}
1487	1487	}
1488	1488
1489		static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr)
	1489	static uint32_t mpic_src_msg_read (void *opaque, hwaddr addr)
1490	1490	{
1491	1491	openpic_t *mpp = opaque;
1492	1492	uint32_t retval;
...	...
1512	1512	return retval;
1513	1513	}
1514	1514
1515		static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
	1515	static void mpic_src_msi_write (void *opaque, hwaddr addr,
1516	1516	uint32_t val)
1517	1517	{
1518	1518	openpic_t *mpp = opaque;
...	...
1533	1533	}
1534	1534	}
1535	1535	}
1536		static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
	1536	static uint32_t mpic_src_msi_read (void *opaque, hwaddr addr)
1537	1537	{
1538	1538	openpic_t *mpp = opaque;
1539	1539	uint32_t retval;
...	...
1657	1657	.endianness = DEVICE_BIG_ENDIAN,
1658	1658	};
1659	1659
1660		qemu_irq mpic_init (MemoryRegion address_space, target_phys_addr_t base,
	1660	qemu_irq mpic_init (MemoryRegion address_space, hwaddr base,
1661	1661	int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
1662	1662	{
1663	1663	openpic_t *mpp;
...	...
1665	1665	struct {
1666	1666	const char *name;
1667	1667	MemoryRegionOps const *ops;
1668		target_phys_addr_t start_addr;
	1668	hwaddr start_addr;
1669	1669	ram_addr_t size;
1670	1670	} const list[] = {
1671	1671	{"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},

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Revision a8170e5e hw/openpic.c