Revision a8170e5e hw/pcnet-pci.c
| b/hw/pcnet-pci.c | ||
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return val; |
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} |
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static uint64_t pcnet_ioport_read(void *opaque, target_phys_addr_t addr,
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static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
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unsigned size) |
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{
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PCNetState *d = opaque; |
| ... | ... | |
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return ((uint64_t)1 << (size * 8)) - 1; |
| 99 | 99 |
} |
| 100 | 100 |
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static void pcnet_ioport_write(void *opaque, target_phys_addr_t addr,
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static void pcnet_ioport_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size) |
| 103 | 103 |
{
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PCNetState *d = opaque; |
| ... | ... | |
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.endianness = DEVICE_NATIVE_ENDIAN, |
| 131 | 131 |
}; |
| 132 | 132 |
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static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
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{
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PCNetState *d = opaque; |
| 136 | 136 |
#ifdef PCNET_DEBUG_IO |
| ... | ... | |
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pcnet_aprom_writeb(d, addr & 0x0f, val); |
| 142 | 142 |
} |
| 143 | 143 |
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static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
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static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr)
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{
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PCNetState *d = opaque; |
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uint32_t val = -1; |
| ... | ... | |
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return val; |
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} |
| 156 | 156 |
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static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
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{
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PCNetState *d = opaque; |
| 160 | 160 |
#ifdef PCNET_DEBUG_IO |
| ... | ... | |
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} |
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} |
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static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
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static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr)
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{
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PCNetState *d = opaque; |
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uint32_t val = -1; |
| ... | ... | |
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return val; |
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} |
| 191 | 191 |
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static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
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{
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PCNetState *d = opaque; |
| 195 | 195 |
#ifdef PCNET_DEBUG_IO |
| ... | ... | |
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} |
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} |
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static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
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static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr)
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{
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PCNetState *d = opaque; |
| 213 | 213 |
uint32_t val; |
| ... | ... | |
| 252 | 252 |
.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
| 254 | 254 |
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static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
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static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
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uint8_t *buf, int len, int do_bswap) |
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{
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pci_dma_write(dma_opaque, addr, buf, len); |
| 259 | 259 |
} |
| 260 | 260 |
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static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
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static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
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uint8_t *buf, int len, int do_bswap) |
| 263 | 263 |
{
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pci_dma_read(dma_opaque, addr, buf, len); |
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