Revision a8170e5e hw/ppc/e500.c
| b/hw/ppc/e500.c | ||
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| 108 | 108 |
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static int ppce500_load_device_tree(CPUPPCState *env, |
| 110 | 110 |
PPCE500Params *params, |
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target_phys_addr_t addr,
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target_phys_addr_t initrd_base,
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target_phys_addr_t initrd_size)
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hwaddr addr,
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hwaddr initrd_base,
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hwaddr initrd_size)
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{
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int ret = -1; |
| 116 | 116 |
uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) };
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| ... | ... | |
| 346 | 346 |
} |
| 347 | 347 |
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/* Create -kernel TLB entries for BookE. */ |
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static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
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static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
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{
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return 63 - clz64(size >> 10); |
| 352 | 352 |
} |
| ... | ... | |
| 355 | 355 |
{
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struct boot_info *bi = env->load_info; |
| 357 | 357 |
ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); |
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target_phys_addr_t size, dt_end;
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hwaddr size, dt_end;
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int ps; |
| 360 | 360 |
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/* Our initial TLB entry needs to cover everything from 0 to |
| ... | ... | |
| 412 | 412 |
CPUPPCState *env = NULL; |
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uint64_t elf_entry; |
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uint64_t elf_lowaddr; |
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target_phys_addr_t entry=0;
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target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
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hwaddr entry=0;
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hwaddr loadaddr=UIMAGE_LOAD_BASE;
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| 417 | 417 |
target_long kernel_size=0; |
| 418 | 418 |
target_ulong dt_base = 0; |
| 419 | 419 |
target_ulong initrd_base = 0; |
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