Revision a8170e5e hw/ppc405.h
| b/hw/ppc405.h | ||
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| 61 | 61 |
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CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, |
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MemoryRegion ram_memories[4], |
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target_phys_addr_t ram_bases[4],
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target_phys_addr_t ram_sizes[4],
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hwaddr ram_bases[4],
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hwaddr ram_sizes[4],
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| 66 | 66 |
uint32_t sysclk, qemu_irq **picp, |
| 67 | 67 |
int do_init); |
| 68 | 68 |
CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, |
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MemoryRegion ram_memories[2], |
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target_phys_addr_t ram_bases[2],
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target_phys_addr_t ram_sizes[2],
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hwaddr ram_bases[2],
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hwaddr ram_sizes[2],
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uint32_t sysclk, qemu_irq **picp, |
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int do_init); |
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/* IBM STBxxx microcontrollers */ |
| 75 | 75 |
CPUPPCState *ppc_stb025_init (MemoryRegion ram_memories[2], |
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target_phys_addr_t ram_bases[2],
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target_phys_addr_t ram_sizes[2],
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hwaddr ram_bases[2],
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hwaddr ram_sizes[2],
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| 78 | 78 |
uint32_t sysclk, qemu_irq **picp, |
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ram_addr_t *offsetp); |
| 80 | 80 |
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