/hw/ppc405_boards.c - Diff - qemu - Greek Research and Technology Network's projects

Revision a8170e5e hw/ppc405_boards.c

b/hw/ppc405_boards.c
60	60	uint8_t reg1;
61	61	};
62	62
63		static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
	63	static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr)
64	64	{
65	65	ref405ep_fpga_t *fpga;
66	66	uint32_t ret;
...	...
82	82	}
83	83
84	84	static void ref405ep_fpga_writeb (void *opaque,
85		target_phys_addr_t addr, uint32_t value)
	85	hwaddr addr, uint32_t value)
86	86	{
87	87	ref405ep_fpga_t *fpga;
88	88
...	...
99	99	}
100	100	}
101	101
102		static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
	102	static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr)
103	103	{
104	104	uint32_t ret;
105	105
...	...
110	110	}
111	111
112	112	static void ref405ep_fpga_writew (void *opaque,
113		target_phys_addr_t addr, uint32_t value)
	113	hwaddr addr, uint32_t value)
114	114	{
115	115	ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
116	116	ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
117	117	}
118	118
119		static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
	119	static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr)
120	120	{
121	121	uint32_t ret;
122	122
...	...
129	129	}
130	130
131	131	static void ref405ep_fpga_writel (void *opaque,
132		target_phys_addr_t addr, uint32_t value)
	132	hwaddr addr, uint32_t value)
133	133	{
134	134	ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
135	135	ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
...	...
184	184	MemoryRegion *sram = g_new(MemoryRegion, 1);
185	185	ram_addr_t bdloc;
186	186	MemoryRegion ram_memories = g_malloc(2 sizeof(*ram_memories));
187		target_phys_addr_t ram_bases[2], ram_sizes[2];
	187	hwaddr ram_bases[2], ram_sizes[2];
188	188	target_ulong sram_size;
189	189	long bios_size;
190	190	//int phy_addr = 0;
...	...
389	389	uint8_t reg1;
390	390	};
391	391
392		static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
	392	static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr)
393	393	{
394	394	taihu_cpld_t *cpld;
395	395	uint32_t ret;
...	...
411	411	}
412	412
413	413	static void taihu_cpld_writeb (void *opaque,
414		target_phys_addr_t addr, uint32_t value)
	414	hwaddr addr, uint32_t value)
415	415	{
416	416	taihu_cpld_t *cpld;
417	417
...	...
428	428	}
429	429	}
430	430
431		static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
	431	static uint32_t taihu_cpld_readw (void *opaque, hwaddr addr)
432	432	{
433	433	uint32_t ret;
434	434
...	...
439	439	}
440	440
441	441	static void taihu_cpld_writew (void *opaque,
442		target_phys_addr_t addr, uint32_t value)
	442	hwaddr addr, uint32_t value)
443	443	{
444	444	taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
445	445	taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
446	446	}
447	447
448		static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
	448	static uint32_t taihu_cpld_readl (void *opaque, hwaddr addr)
449	449	{
450	450	uint32_t ret;
451	451
...	...
458	458	}
459	459
460	460	static void taihu_cpld_writel (void *opaque,
461		target_phys_addr_t addr, uint32_t value)
	461	hwaddr addr, uint32_t value)
462	462	{
463	463	taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
464	464	taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
...	...
504	504	MemoryRegion *sysmem = get_system_memory();
505	505	MemoryRegion *bios;
506	506	MemoryRegion ram_memories = g_malloc(2 sizeof(*ram_memories));
507		target_phys_addr_t ram_bases[2], ram_sizes[2];
	507	hwaddr ram_bases[2], ram_sizes[2];
508	508	long bios_size;
509	509	target_ulong kernel_base, initrd_base;
510	510	long kernel_size, initrd_size;

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Revision a8170e5e hw/ppc405_boards.c