Revision a8170e5e hw/pxa2xx_dma.c
| b/hw/pxa2xx_dma.c | ||
|---|---|---|
| 147 | 147 |
PXA2xxDMAState *s, int ch) |
| 148 | 148 |
{
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uint32_t desc[4]; |
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target_phys_addr_t daddr = s->chan[ch].descr & ~0xf;
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hwaddr daddr = s->chan[ch].descr & ~0xf;
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if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST)) |
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daddr += 32; |
| 153 | 153 |
|
| ... | ... | |
| 251 | 251 |
} |
| 252 | 252 |
} |
| 253 | 253 |
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static uint64_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset,
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static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
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| 255 | 255 |
unsigned size) |
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{
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PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; |
| ... | ... | |
| 310 | 310 |
return 7; |
| 311 | 311 |
} |
| 312 | 312 |
|
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static void pxa2xx_dma_write(void *opaque, target_phys_addr_t offset,
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static void pxa2xx_dma_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size) |
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{
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PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; |
| ... | ... | |
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return 0; |
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} |
| 475 | 475 |
|
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DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq)
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DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
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{
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DeviceState *dev; |
| 479 | 479 |
|
| ... | ... | |
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return dev; |
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} |
| 489 | 489 |
|
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DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq)
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DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq)
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| 491 | 491 |
{
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| 492 | 492 |
DeviceState *dev; |
| 493 | 493 |
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