Revision a8170e5e hw/pxa2xx_mmci.c
| b/hw/pxa2xx_mmci.c | ||
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pxa2xx_mmci_fifo_update(s); |
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} |
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static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
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static uint32_t pxa2xx_mmci_read(void *opaque, hwaddr offset)
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{
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PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
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uint32_t ret; |
| ... | ... | |
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} |
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static void pxa2xx_mmci_write(void *opaque, |
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target_phys_addr_t offset, uint32_t value)
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hwaddr offset, uint32_t value)
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{
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PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
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| ... | ... | |
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} |
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} |
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static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset)
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static uint32_t pxa2xx_mmci_readb(void *opaque, hwaddr offset)
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{
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PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
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s->ac_width = 1; |
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return pxa2xx_mmci_read(opaque, offset); |
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} |
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static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset)
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static uint32_t pxa2xx_mmci_readh(void *opaque, hwaddr offset)
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{
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PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
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s->ac_width = 2; |
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return pxa2xx_mmci_read(opaque, offset); |
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} |
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static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
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static uint32_t pxa2xx_mmci_readw(void *opaque, hwaddr offset)
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{
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PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
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s->ac_width = 4; |
| ... | ... | |
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} |
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static void pxa2xx_mmci_writeb(void *opaque, |
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target_phys_addr_t offset, uint32_t value)
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hwaddr offset, uint32_t value)
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{
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PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
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s->ac_width = 1; |
| ... | ... | |
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} |
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static void pxa2xx_mmci_writeh(void *opaque, |
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target_phys_addr_t offset, uint32_t value)
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hwaddr offset, uint32_t value)
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{
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PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
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s->ac_width = 2; |
| ... | ... | |
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} |
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static void pxa2xx_mmci_writew(void *opaque, |
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target_phys_addr_t offset, uint32_t value)
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hwaddr offset, uint32_t value)
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{
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PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; |
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s->ac_width = 4; |
| ... | ... | |
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} |
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PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem, |
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target_phys_addr_t base,
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hwaddr base,
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BlockDriverState *bd, qemu_irq irq, |
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qemu_irq rx_dma, qemu_irq tx_dma) |
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{
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