Revision a8170e5e hw/smc91c111.c
| b/hw/smc91c111.c | ||
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| 276 | 276 |
#define SET_LOW(name, val) s->name = (s->name & 0xff00) | val |
| 277 | 277 |
#define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8) |
| 278 | 278 |
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static void smc91c111_writeb(void *opaque, target_phys_addr_t offset,
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static void smc91c111_writeb(void *opaque, hwaddr offset,
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uint32_t value) |
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{
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smc91c111_state *s = (smc91c111_state *)opaque; |
| ... | ... | |
| 451 | 451 |
hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset);
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| 452 | 452 |
} |
| 453 | 453 |
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static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
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static uint32_t smc91c111_readb(void *opaque, hwaddr offset)
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{
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smc91c111_state *s = (smc91c111_state *)opaque; |
| 457 | 457 |
|
| ... | ... | |
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return 0; |
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} |
| 597 | 597 |
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static void smc91c111_writew(void *opaque, target_phys_addr_t offset,
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static void smc91c111_writew(void *opaque, hwaddr offset,
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uint32_t value) |
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{
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smc91c111_writeb(opaque, offset, value & 0xff); |
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smc91c111_writeb(opaque, offset + 1, value >> 8); |
| 603 | 603 |
} |
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static void smc91c111_writel(void *opaque, target_phys_addr_t offset,
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static void smc91c111_writel(void *opaque, hwaddr offset,
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uint32_t value) |
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{
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/* 32-bit writes to offset 0xc only actually write to the bank select |
| ... | ... | |
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smc91c111_writew(opaque, offset + 2, value >> 16); |
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} |
| 614 | 614 |
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static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset)
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static uint32_t smc91c111_readw(void *opaque, hwaddr offset)
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{
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uint32_t val; |
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val = smc91c111_readb(opaque, offset); |
| ... | ... | |
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return val; |
| 621 | 621 |
} |
| 622 | 622 |
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static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset)
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static uint32_t smc91c111_readl(void *opaque, hwaddr offset)
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{
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uint32_t val; |
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val = smc91c111_readw(opaque, offset); |
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