Revision a8170e5e hw/sun4m.c
b/hw/sun4m.c | ||
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87 | 87 |
#define ESCC_CLOCK 4915200 |
88 | 88 |
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89 | 89 |
struct sun4m_hwdef { |
90 |
target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
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91 |
target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
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92 |
target_phys_addr_t serial_base, fd_base;
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93 |
target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
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94 |
target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
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95 |
target_phys_addr_t bpp_base, dbri_base, sx_base;
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90 |
hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
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91 |
hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
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92 |
hwaddr serial_base, fd_base;
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93 |
hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
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94 |
hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
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95 |
hwaddr bpp_base, dbri_base, sx_base;
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96 | 96 |
struct { |
97 |
target_phys_addr_t reg_base, vram_base;
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97 |
hwaddr reg_base, vram_base;
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98 | 98 |
} vsimm[MAX_VSIMMS]; |
99 |
target_phys_addr_t ecc_base;
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99 |
hwaddr ecc_base;
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100 | 100 |
uint64_t max_mem; |
101 | 101 |
const char * const default_cpu_model; |
102 | 102 |
uint32_t ecc_version; |
... | ... | |
108 | 108 |
#define MAX_IOUNITS 5 |
109 | 109 |
|
110 | 110 |
struct sun4d_hwdef { |
111 |
target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
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target_phys_addr_t counter_base, nvram_base, ms_kb_base;
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target_phys_addr_t serial_base;
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114 |
target_phys_addr_t espdma_base, esp_base;
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115 |
target_phys_addr_t ledma_base, le_base;
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116 |
target_phys_addr_t tcx_base;
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117 |
target_phys_addr_t sbi_base;
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111 |
hwaddr iounit_bases[MAX_IOUNITS], slavio_base;
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112 |
hwaddr counter_base, nvram_base, ms_kb_base;
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113 |
hwaddr serial_base;
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114 |
hwaddr espdma_base, esp_base;
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115 |
hwaddr ledma_base, le_base;
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116 |
hwaddr tcx_base;
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117 |
hwaddr sbi_base;
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118 | 118 |
uint64_t max_mem; |
119 | 119 |
const char * const default_cpu_model; |
120 | 120 |
uint32_t iounit_version; |
... | ... | |
123 | 123 |
}; |
124 | 124 |
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125 | 125 |
struct sun4c_hwdef { |
126 |
target_phys_addr_t iommu_base, slavio_base;
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127 |
target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
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target_phys_addr_t serial_base, fd_base;
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target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
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target_phys_addr_t tcx_base, aux1_base;
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126 |
hwaddr iommu_base, slavio_base;
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hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
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hwaddr serial_base, fd_base;
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hwaddr idreg_base, dma_base, esp_base, le_base;
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130 |
hwaddr tcx_base, aux1_base;
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131 | 131 |
uint64_t max_mem; |
132 | 132 |
const char * const default_cpu_model; |
133 | 133 |
uint32_t iommu_version; |
... | ... | |
373 | 373 |
return kernel_size; |
374 | 374 |
} |
375 | 375 |
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376 |
static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
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376 |
static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
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377 | 377 |
{ |
378 | 378 |
DeviceState *dev; |
379 | 379 |
SysBusDevice *s; |
... | ... | |
388 | 388 |
return s; |
389 | 389 |
} |
390 | 390 |
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391 |
static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
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391 |
static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
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392 | 392 |
void *iommu, qemu_irq *dev_irq, int is_ledma) |
393 | 393 |
{ |
394 | 394 |
DeviceState *dev; |
... | ... | |
406 | 406 |
return s; |
407 | 407 |
} |
408 | 408 |
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409 |
static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
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409 |
static void lance_init(NICInfo *nd, hwaddr leaddr,
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410 | 410 |
void *dma_opaque, qemu_irq irq) |
411 | 411 |
{ |
412 | 412 |
DeviceState *dev; |
... | ... | |
426 | 426 |
qdev_connect_gpio_out(dma_opaque, 0, reset); |
427 | 427 |
} |
428 | 428 |
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429 |
static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
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430 |
target_phys_addr_t addrg,
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429 |
static DeviceState *slavio_intctl_init(hwaddr addr,
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430 |
hwaddr addrg,
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431 | 431 |
qemu_irq **parent_irq) |
432 | 432 |
{ |
433 | 433 |
DeviceState *dev; |
... | ... | |
455 | 455 |
#define SYS_TIMER_OFFSET 0x10000ULL |
456 | 456 |
#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
457 | 457 |
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458 |
static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
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458 |
static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
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459 | 459 |
qemu_irq *cpu_irqs, unsigned int num_cpus) |
460 | 460 |
{ |
461 | 461 |
DeviceState *dev; |
... | ... | |
470 | 470 |
sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); |
471 | 471 |
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472 | 472 |
for (i = 0; i < MAX_CPUS; i++) { |
473 |
sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
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sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
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474 | 474 |
sysbus_connect_irq(s, i + 1, cpu_irqs[i]); |
475 | 475 |
} |
476 | 476 |
} |
... | ... | |
492 | 492 |
#define MISC_MDM 0x01b00000 |
493 | 493 |
#define MISC_SYS 0x01f00000 |
494 | 494 |
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495 |
static void slavio_misc_init(target_phys_addr_t base,
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496 |
target_phys_addr_t aux1_base,
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497 |
target_phys_addr_t aux2_base, qemu_irq irq,
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495 |
static void slavio_misc_init(hwaddr base,
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496 |
hwaddr aux1_base,
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497 |
hwaddr aux2_base, qemu_irq irq,
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498 | 498 |
qemu_irq fdc_tc) |
499 | 499 |
{ |
500 | 500 |
DeviceState *dev; |
... | ... | |
532 | 532 |
qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); |
533 | 533 |
} |
534 | 534 |
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535 |
static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
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535 |
static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
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536 | 536 |
{ |
537 | 537 |
DeviceState *dev; |
538 | 538 |
SysBusDevice *s; |
... | ... | |
548 | 548 |
} |
549 | 549 |
} |
550 | 550 |
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551 |
static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
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551 |
static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
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552 | 552 |
{ |
553 | 553 |
DeviceState *dev; |
554 | 554 |
SysBusDevice *s; |
... | ... | |
561 | 561 |
sysbus_connect_irq(s, 0, cpu_halt); |
562 | 562 |
} |
563 | 563 |
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564 |
static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
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564 |
static void tcx_init(hwaddr addr, int vram_size, int width,
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565 | 565 |
int height, int depth) |
566 | 566 |
{ |
567 | 567 |
DeviceState *dev; |
... | ... | |
597 | 597 |
/* NCR89C100/MACIO Internal ID register */ |
598 | 598 |
static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
599 | 599 |
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600 |
static void idreg_init(target_phys_addr_t addr)
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600 |
static void idreg_init(hwaddr addr)
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601 | 601 |
{ |
602 | 602 |
DeviceState *dev; |
603 | 603 |
SysBusDevice *s; |
... | ... | |
646 | 646 |
} AFXState; |
647 | 647 |
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648 | 648 |
/* SS-5 TCX AFX register */ |
649 |
static void afx_init(target_phys_addr_t addr)
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649 |
static void afx_init(hwaddr addr)
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650 | 650 |
{ |
651 | 651 |
DeviceState *dev; |
652 | 652 |
SysBusDevice *s; |
... | ... | |
690 | 690 |
/* Boot PROM (OpenBIOS) */ |
691 | 691 |
static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
692 | 692 |
{ |
693 |
target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
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693 |
hwaddr *base_addr = (hwaddr *)opaque;
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694 | 694 |
return addr + *base_addr - PROM_VADDR; |
695 | 695 |
} |
696 | 696 |
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697 |
static void prom_init(target_phys_addr_t addr, const char *bios_name)
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697 |
static void prom_init(hwaddr addr, const char *bios_name)
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698 | 698 |
{ |
699 | 699 |
DeviceState *dev; |
700 | 700 |
SysBusDevice *s; |
... | ... | |
777 | 777 |
return 0; |
778 | 778 |
} |
779 | 779 |
|
780 |
static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
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780 |
static void ram_init(hwaddr addr, ram_addr_t RAM_size,
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781 | 781 |
uint64_t max_mem) |
782 | 782 |
{ |
783 | 783 |
DeviceState *dev; |
... | ... | |
1544 | 1544 |
}, |
1545 | 1545 |
}; |
1546 | 1546 |
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1547 |
static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
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1547 |
static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq)
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1548 | 1548 |
{ |
1549 | 1549 |
DeviceState *dev; |
1550 | 1550 |
SysBusDevice *s; |
... | ... | |
1605 | 1605 |
} |
1606 | 1606 |
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1607 | 1607 |
for (i = 0; i < MAX_IOUNITS; i++) |
1608 |
if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
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1608 |
if (hwdef->iounit_bases[i] != (hwaddr)-1)
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1609 | 1609 |
iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1610 | 1610 |
hwdef->iounit_version, |
1611 | 1611 |
sbi_irq[0]); |
... | ... | |
1744 | 1744 |
}, |
1745 | 1745 |
}; |
1746 | 1746 |
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1747 |
static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
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1747 |
static DeviceState *sun4c_intctl_init(hwaddr addr,
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1748 | 1748 |
qemu_irq *parent_irq) |
1749 | 1749 |
{ |
1750 | 1750 |
DeviceState *dev; |
... | ... | |
1825 | 1825 |
slavio_irq[1], serial_hds[0], serial_hds[1], |
1826 | 1826 |
ESCC_CLOCK, 1); |
1827 | 1827 |
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1828 |
if (hwdef->fd_base != (target_phys_addr_t)-1) {
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1828 |
if (hwdef->fd_base != (hwaddr)-1) {
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1829 | 1829 |
/* there is zero or one floppy drive */ |
1830 | 1830 |
memset(fd, 0, sizeof(fd)); |
1831 | 1831 |
fd[0] = drive_get(IF_FLOPPY, 0, 0); |
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