Revision a8170e5e target-ppc/mmu_helper.c
| b/target-ppc/mmu_helper.c | ||
|---|---|---|
| 215 | 215 |
pp = pte1 & 0x00000003; |
| 216 | 216 |
} |
| 217 | 217 |
if (ptem == ctx->ptem) {
|
| 218 |
if (ctx->raddr != (target_phys_addr_t)-1ULL) {
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|
| 218 |
if (ctx->raddr != (hwaddr)-1ULL) {
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|
| 219 | 219 |
/* all matches should have equal RPN, WIMG & PP */ |
| 220 | 220 |
if ((ctx->raddr & mmask) != (pte1 & mmask)) {
|
| 221 | 221 |
qemu_log("Bad RPN/WIMG/PP\n");
|
| ... | ... | |
| 556 | 556 |
return ret; |
| 557 | 557 |
} |
| 558 | 558 |
|
| 559 |
static inline target_phys_addr_t get_pteg_offset(CPUPPCState *env,
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|
| 560 |
target_phys_addr_t hash,
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|
| 559 |
static inline hwaddr get_pteg_offset(CPUPPCState *env,
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|
| 560 |
hwaddr hash,
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|
| 561 | 561 |
int pte_size) |
| 562 | 562 |
{
|
| 563 | 563 |
return (hash * pte_size * 8) & env->htab_mask; |
| ... | ... | |
| 567 | 567 |
static inline int find_pte2(CPUPPCState *env, mmu_ctx_t *ctx, int is_64b, int h, |
| 568 | 568 |
int rw, int type, int target_page_bits) |
| 569 | 569 |
{
|
| 570 |
target_phys_addr_t pteg_off;
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|
| 570 |
hwaddr pteg_off;
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|
| 571 | 571 |
target_ulong pte0, pte1; |
| 572 | 572 |
int i, good = -1; |
| 573 | 573 |
int ret, r; |
| ... | ... | |
| 817 | 817 |
static inline int get_segment(CPUPPCState *env, mmu_ctx_t *ctx, |
| 818 | 818 |
target_ulong eaddr, int rw, int type) |
| 819 | 819 |
{
|
| 820 |
target_phys_addr_t hash;
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|
| 820 |
hwaddr hash;
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|
| 821 | 821 |
target_ulong vsid; |
| 822 | 822 |
int ds, pr, target_page_bits; |
| 823 | 823 |
int ret, ret2; |
| ... | ... | |
| 896 | 896 |
ctx->hash[1] = ~hash; |
| 897 | 897 |
|
| 898 | 898 |
/* Initialize real address with an invalid value */ |
| 899 |
ctx->raddr = (target_phys_addr_t)-1ULL;
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|
| 899 |
ctx->raddr = (hwaddr)-1ULL;
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|
| 900 | 900 |
if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx || |
| 901 | 901 |
env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
|
| 902 | 902 |
/* Software TLB search */ |
| ... | ... | |
| 926 | 926 |
} |
| 927 | 927 |
#if defined(DUMP_PAGE_TABLES) |
| 928 | 928 |
if (qemu_log_enabled()) {
|
| 929 |
target_phys_addr_t curaddr;
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|
| 929 |
hwaddr curaddr;
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|
| 930 | 930 |
uint32_t a0, a1, a2, a3; |
| 931 | 931 |
|
| 932 | 932 |
qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
|
| ... | ... | |
| 1009 | 1009 |
|
| 1010 | 1010 |
/* Generic TLB check function for embedded PowerPC implementations */ |
| 1011 | 1011 |
static int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb, |
| 1012 |
target_phys_addr_t *raddrp,
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| 1012 |
hwaddr *raddrp,
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| 1013 | 1013 |
target_ulong address, uint32_t pid, int ext, |
| 1014 | 1014 |
int i) |
| 1015 | 1015 |
{
|
| ... | ... | |
| 1045 | 1045 |
uint32_t pid) |
| 1046 | 1046 |
{
|
| 1047 | 1047 |
ppcemb_tlb_t *tlb; |
| 1048 |
target_phys_addr_t raddr;
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| 1048 |
hwaddr raddr;
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| 1049 | 1049 |
int i, ret; |
| 1050 | 1050 |
|
| 1051 | 1051 |
/* Default return value is no match */ |
| ... | ... | |
| 1079 | 1079 |
{
|
| 1080 | 1080 |
#if !defined(FLUSH_ALL_TLBS) |
| 1081 | 1081 |
ppcemb_tlb_t *tlb; |
| 1082 |
target_phys_addr_t raddr;
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| 1082 |
hwaddr raddr;
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| 1083 | 1083 |
target_ulong page, end; |
| 1084 | 1084 |
int i; |
| 1085 | 1085 |
|
| ... | ... | |
| 1104 | 1104 |
int access_type) |
| 1105 | 1105 |
{
|
| 1106 | 1106 |
ppcemb_tlb_t *tlb; |
| 1107 |
target_phys_addr_t raddr;
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| 1107 |
hwaddr raddr;
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| 1108 | 1108 |
int i, ret, zsel, zpr, pr; |
| 1109 | 1109 |
|
| 1110 | 1110 |
ret = -1; |
| 1111 |
raddr = (target_phys_addr_t)-1ULL;
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|
| 1111 |
raddr = (hwaddr)-1ULL;
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|
| 1112 | 1112 |
pr = msr_pr; |
| 1113 | 1113 |
for (i = 0; i < env->nb_tlb; i++) {
|
| 1114 | 1114 |
tlb = &env->tlb.tlbe[i]; |
| ... | ... | |
| 1175 | 1175 |
} |
| 1176 | 1176 |
|
| 1177 | 1177 |
static inline int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb, |
| 1178 |
target_phys_addr_t *raddr, int *prot,
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| 1178 |
hwaddr *raddr, int *prot,
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| 1179 | 1179 |
target_ulong address, int rw, |
| 1180 | 1180 |
int access_type, int i) |
| 1181 | 1181 |
{
|
| ... | ... | |
| 1249 | 1249 |
int access_type) |
| 1250 | 1250 |
{
|
| 1251 | 1251 |
ppcemb_tlb_t *tlb; |
| 1252 |
target_phys_addr_t raddr;
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| 1252 |
hwaddr raddr;
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| 1253 | 1253 |
int i, ret; |
| 1254 | 1254 |
|
| 1255 | 1255 |
ret = -1; |
| 1256 |
raddr = (target_phys_addr_t)-1ULL;
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| 1256 |
raddr = (hwaddr)-1ULL;
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| 1257 | 1257 |
for (i = 0; i < env->nb_tlb; i++) {
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| 1258 | 1258 |
tlb = &env->tlb.tlbe[i]; |
| 1259 | 1259 |
ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, rw, |
| ... | ... | |
| 1297 | 1297 |
tlb_flush(env, 1); |
| 1298 | 1298 |
} |
| 1299 | 1299 |
|
| 1300 |
target_phys_addr_t booke206_tlb_to_page_size(CPUPPCState *env,
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|
| 1300 |
hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
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|
| 1301 | 1301 |
ppcmas_tlb_t *tlb) |
| 1302 | 1302 |
{
|
| 1303 | 1303 |
int tlbm_size; |
| ... | ... | |
| 1309 | 1309 |
|
| 1310 | 1310 |
/* TLB check function for MAS based SoftTLBs */ |
| 1311 | 1311 |
int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, |
| 1312 |
target_phys_addr_t *raddrp,
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|
| 1312 |
hwaddr *raddrp,
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|
| 1313 | 1313 |
target_ulong address, uint32_t pid) |
| 1314 | 1314 |
{
|
| 1315 | 1315 |
target_ulong mask; |
| ... | ... | |
| 1345 | 1345 |
} |
| 1346 | 1346 |
|
| 1347 | 1347 |
static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb, |
| 1348 |
target_phys_addr_t *raddr, int *prot,
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|
| 1348 |
hwaddr *raddr, int *prot,
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|
| 1349 | 1349 |
target_ulong address, int rw, |
| 1350 | 1350 |
int access_type) |
| 1351 | 1351 |
{
|
| ... | ... | |
| 1435 | 1435 |
int access_type) |
| 1436 | 1436 |
{
|
| 1437 | 1437 |
ppcmas_tlb_t *tlb; |
| 1438 |
target_phys_addr_t raddr;
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|
| 1438 |
hwaddr raddr;
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|
| 1439 | 1439 |
int i, j, ret; |
| 1440 | 1440 |
|
| 1441 | 1441 |
ret = -1; |
| 1442 |
raddr = (target_phys_addr_t)-1ULL;
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|
| 1442 |
raddr = (hwaddr)-1ULL;
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|
| 1443 | 1443 |
|
| 1444 | 1444 |
for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
|
| 1445 | 1445 |
int ways = booke206_tlb_ways(env, i); |
| ... | ... | |
| 1496 | 1496 |
|
| 1497 | 1497 |
entry = &env->tlb.tlbe[0]; |
| 1498 | 1498 |
for (i = 0; i < env->nb_tlb; i++, entry++) {
|
| 1499 |
target_phys_addr_t ea, pa;
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|
| 1499 |
hwaddr ea, pa;
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|
| 1500 | 1500 |
target_ulong mask; |
| 1501 | 1501 |
uint64_t size = (uint64_t)entry->size; |
| 1502 | 1502 |
char size_buf[20]; |
| ... | ... | |
| 1509 | 1509 |
mask = ~(entry->size - 1); |
| 1510 | 1510 |
ea = entry->EPN & mask; |
| 1511 | 1511 |
pa = entry->RPN & mask; |
| 1512 |
#if (TARGET_PHYS_ADDR_BITS >= 36) |
|
| 1512 |
#if (TARGET_PHYS_ADDR_SPACE_BITS >= 36)
|
|
| 1513 | 1513 |
/* Extend the physical address to 36 bits */ |
| 1514 |
pa |= (target_phys_addr_t)(entry->RPN & 0xF) << 32;
|
|
| 1514 |
pa |= (hwaddr)(entry->RPN & 0xF) << 32;
|
|
| 1515 | 1515 |
#endif |
| 1516 | 1516 |
size /= 1024; |
| 1517 | 1517 |
if (size >= 1024) {
|
| ... | ... | |
| 1539 | 1539 |
|
| 1540 | 1540 |
entry = &env->tlb.tlbm[offset]; |
| 1541 | 1541 |
for (i = 0; i < tlbsize; i++, entry++) {
|
| 1542 |
target_phys_addr_t ea, pa, size;
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|
| 1542 |
hwaddr ea, pa, size;
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|
| 1543 | 1543 |
int tsize; |
| 1544 | 1544 |
|
| 1545 | 1545 |
if (!(entry->mas1 & MAS1_VALID)) {
|
| ... | ... | |
| 1785 | 1785 |
return ret; |
| 1786 | 1786 |
} |
| 1787 | 1787 |
|
| 1788 |
target_phys_addr_t cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
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|
| 1788 |
hwaddr cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
|
|
| 1789 | 1789 |
{
|
| 1790 | 1790 |
mmu_ctx_t ctx; |
| 1791 | 1791 |
|
| ... | ... | |
| 3145 | 3145 |
{
|
| 3146 | 3146 |
ppcmas_tlb_t *tlb = NULL; |
| 3147 | 3147 |
int i, j; |
| 3148 |
target_phys_addr_t raddr;
|
|
| 3148 |
hwaddr raddr;
|
|
| 3149 | 3149 |
uint32_t spid, sas; |
| 3150 | 3150 |
|
| 3151 | 3151 |
spid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID_MASK) >> MAS6_SPID_SHIFT; |
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