Revision a8170e5e target-sparc/mmu_helper.c
| b/target-sparc/mmu_helper.c | ||
|---|---|---|
| 76 | 76 |
} |
| 77 | 77 |
}; |
| 78 | 78 |
|
| 79 |
static int get_physical_address(CPUSPARCState *env, target_phys_addr_t *physical,
|
|
| 79 |
static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
|
|
| 80 | 80 |
int *prot, int *access_index, |
| 81 | 81 |
target_ulong address, int rw, int mmu_idx, |
| 82 | 82 |
target_ulong *page_size) |
| 83 | 83 |
{
|
| 84 | 84 |
int access_perms = 0; |
| 85 |
target_phys_addr_t pde_ptr;
|
|
| 85 |
hwaddr pde_ptr;
|
|
| 86 | 86 |
uint32_t pde; |
| 87 | 87 |
int error_code = 0, is_dirty, is_user; |
| 88 | 88 |
unsigned long page_offset; |
| ... | ... | |
| 192 | 192 |
|
| 193 | 193 |
/* Even if large ptes, we map only one 4KB page in the cache to |
| 194 | 194 |
avoid filling it too fast */ |
| 195 |
*physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
|
|
| 195 |
*physical = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset;
|
|
| 196 | 196 |
return error_code; |
| 197 | 197 |
} |
| 198 | 198 |
|
| ... | ... | |
| 200 | 200 |
int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw, |
| 201 | 201 |
int mmu_idx) |
| 202 | 202 |
{
|
| 203 |
target_phys_addr_t paddr;
|
|
| 203 |
hwaddr paddr;
|
|
| 204 | 204 |
target_ulong vaddr; |
| 205 | 205 |
target_ulong page_size; |
| 206 | 206 |
int error_code = 0, prot, access_index; |
| ... | ... | |
| 244 | 244 |
|
| 245 | 245 |
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) |
| 246 | 246 |
{
|
| 247 |
target_phys_addr_t pde_ptr;
|
|
| 247 |
hwaddr pde_ptr;
|
|
| 248 | 248 |
uint32_t pde; |
| 249 | 249 |
|
| 250 | 250 |
/* Context base + context number */ |
| 251 |
pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
|
|
| 251 |
pde_ptr = (hwaddr)(env->mmuregs[1] << 4) +
|
|
| 252 | 252 |
(env->mmuregs[2] << 2); |
| 253 | 253 |
pde = ldl_phys(pde_ptr); |
| 254 | 254 |
|
| ... | ... | |
| 312 | 312 |
{
|
| 313 | 313 |
target_ulong va, va1, va2; |
| 314 | 314 |
unsigned int n, m, o; |
| 315 |
target_phys_addr_t pde_ptr, pa;
|
|
| 315 |
hwaddr pde_ptr, pa;
|
|
| 316 | 316 |
uint32_t pde; |
| 317 | 317 |
|
| 318 | 318 |
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
| 319 | 319 |
pde = ldl_phys(pde_ptr); |
| 320 | 320 |
(*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
| 321 |
(target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
|
|
| 321 |
(hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
|
|
| 322 | 322 |
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
|
| 323 | 323 |
pde = mmu_probe(env, va, 2); |
| 324 | 324 |
if (pde) {
|
| ... | ... | |
| 431 | 431 |
#else /* !TARGET_SPARC64 */ |
| 432 | 432 |
|
| 433 | 433 |
/* 41 bit physical address space */ |
| 434 |
static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x)
|
|
| 434 |
static inline hwaddr ultrasparc_truncate_physical(uint64_t x)
|
|
| 435 | 435 |
{
|
| 436 | 436 |
return x & 0x1ffffffffffULL; |
| 437 | 437 |
} |
| ... | ... | |
| 445 | 445 |
entry size */ |
| 446 | 446 |
static inline int ultrasparc_tag_match(SparcTLBEntry *tlb, |
| 447 | 447 |
uint64_t address, uint64_t context, |
| 448 |
target_phys_addr_t *physical)
|
|
| 448 |
hwaddr *physical)
|
|
| 449 | 449 |
{
|
| 450 | 450 |
uint64_t mask; |
| 451 | 451 |
|
| ... | ... | |
| 478 | 478 |
} |
| 479 | 479 |
|
| 480 | 480 |
static int get_physical_address_data(CPUSPARCState *env, |
| 481 |
target_phys_addr_t *physical, int *prot,
|
|
| 481 |
hwaddr *physical, int *prot,
|
|
| 482 | 482 |
target_ulong address, int rw, int mmu_idx) |
| 483 | 483 |
{
|
| 484 | 484 |
unsigned int i; |
| ... | ... | |
| 597 | 597 |
} |
| 598 | 598 |
|
| 599 | 599 |
static int get_physical_address_code(CPUSPARCState *env, |
| 600 |
target_phys_addr_t *physical, int *prot,
|
|
| 600 |
hwaddr *physical, int *prot,
|
|
| 601 | 601 |
target_ulong address, int mmu_idx) |
| 602 | 602 |
{
|
| 603 | 603 |
unsigned int i; |
| ... | ... | |
| 665 | 665 |
return 1; |
| 666 | 666 |
} |
| 667 | 667 |
|
| 668 |
static int get_physical_address(CPUSPARCState *env, target_phys_addr_t *physical,
|
|
| 668 |
static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
|
|
| 669 | 669 |
int *prot, int *access_index, |
| 670 | 670 |
target_ulong address, int rw, int mmu_idx, |
| 671 | 671 |
target_ulong *page_size) |
| ... | ... | |
| 703 | 703 |
int mmu_idx) |
| 704 | 704 |
{
|
| 705 | 705 |
target_ulong vaddr; |
| 706 |
target_phys_addr_t paddr;
|
|
| 706 |
hwaddr paddr;
|
|
| 707 | 707 |
target_ulong page_size; |
| 708 | 708 |
int error_code = 0, prot, access_index; |
| 709 | 709 |
|
| ... | ... | |
| 810 | 810 |
|
| 811 | 811 |
#endif /* TARGET_SPARC64 */ |
| 812 | 812 |
|
| 813 |
static int cpu_sparc_get_phys_page(CPUSPARCState *env, target_phys_addr_t *phys,
|
|
| 813 |
static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
|
|
| 814 | 814 |
target_ulong addr, int rw, int mmu_idx) |
| 815 | 815 |
{
|
| 816 | 816 |
target_ulong page_size; |
| ... | ... | |
| 821 | 821 |
} |
| 822 | 822 |
|
| 823 | 823 |
#if defined(TARGET_SPARC64) |
| 824 |
target_phys_addr_t cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
|
|
| 824 |
hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
|
|
| 825 | 825 |
int mmu_idx) |
| 826 | 826 |
{
|
| 827 |
target_phys_addr_t phys_addr;
|
|
| 827 |
hwaddr phys_addr;
|
|
| 828 | 828 |
|
| 829 | 829 |
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 4, mmu_idx) != 0) {
|
| 830 | 830 |
return -1; |
| ... | ... | |
| 833 | 833 |
} |
| 834 | 834 |
#endif |
| 835 | 835 |
|
| 836 |
target_phys_addr_t cpu_get_phys_page_debug(CPUSPARCState *env, target_ulong addr)
|
|
| 836 |
hwaddr cpu_get_phys_page_debug(CPUSPARCState *env, target_ulong addr)
|
|
| 837 | 837 |
{
|
| 838 |
target_phys_addr_t phys_addr;
|
|
| 838 |
hwaddr phys_addr;
|
|
| 839 | 839 |
int mmu_idx = cpu_mmu_index(env); |
| 840 | 840 |
MemoryRegionSection section; |
| 841 | 841 |
|
Also available in: Unified diff