root / hw / ide / pci.c @ a8170e5e
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/*
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* QEMU IDE Emulation: PCI Bus support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <hw/hw.h> |
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#include <hw/pc.h> |
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#include <hw/pci.h> |
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#include <hw/isa.h> |
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#include "block.h" |
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#include "dma.h" |
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#include <hw/ide/pci.h> |
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#define BMDMA_PAGE_SIZE 4096 |
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static void bmdma_start_dma(IDEDMA *dma, IDEState *s, |
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BlockDriverCompletionFunc *dma_cb) |
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{ |
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); |
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bm->unit = s->unit; |
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bm->dma_cb = dma_cb; |
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bm->cur_prd_last = 0;
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bm->cur_prd_addr = 0;
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bm->cur_prd_len = 0;
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bm->sector_num = ide_get_sector(s); |
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bm->nsector = s->nsector; |
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if (bm->status & BM_STATUS_DMAING) {
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bm->dma_cb(bmdma_active_if(bm), 0);
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} |
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} |
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/* return 0 if buffer completed */
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static int bmdma_prepare_buf(IDEDMA *dma, int is_write) |
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{ |
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); |
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IDEState *s = bmdma_active_if(bm); |
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struct {
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uint32_t addr; |
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uint32_t size; |
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} prd; |
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int l, len;
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pci_dma_sglist_init(&s->sg, &bm->pci_dev->dev, |
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s->nsector / (BMDMA_PAGE_SIZE / 512) + 1); |
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s->io_buffer_size = 0;
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for(;;) {
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if (bm->cur_prd_len == 0) { |
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/* end of table (with a fail safe of one page) */
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if (bm->cur_prd_last ||
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(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE) |
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return s->io_buffer_size != 0; |
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pci_dma_read(&bm->pci_dev->dev, bm->cur_addr, &prd, 8);
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bm->cur_addr += 8;
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prd.addr = le32_to_cpu(prd.addr); |
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prd.size = le32_to_cpu(prd.size); |
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len = prd.size & 0xfffe;
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if (len == 0) |
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len = 0x10000;
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bm->cur_prd_len = len; |
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bm->cur_prd_addr = prd.addr; |
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bm->cur_prd_last = (prd.size & 0x80000000);
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} |
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l = bm->cur_prd_len; |
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if (l > 0) { |
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qemu_sglist_add(&s->sg, bm->cur_prd_addr, l); |
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bm->cur_prd_addr += l; |
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bm->cur_prd_len -= l; |
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s->io_buffer_size += l; |
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} |
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} |
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return 1; |
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} |
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|
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/* return 0 if buffer completed */
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static int bmdma_rw_buf(IDEDMA *dma, int is_write) |
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{ |
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); |
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IDEState *s = bmdma_active_if(bm); |
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struct {
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uint32_t addr; |
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uint32_t size; |
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} prd; |
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int l, len;
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for(;;) {
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l = s->io_buffer_size - s->io_buffer_index; |
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if (l <= 0) |
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break;
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if (bm->cur_prd_len == 0) { |
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/* end of table (with a fail safe of one page) */
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if (bm->cur_prd_last ||
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(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE) |
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return 0; |
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pci_dma_read(&bm->pci_dev->dev, bm->cur_addr, &prd, 8);
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bm->cur_addr += 8;
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prd.addr = le32_to_cpu(prd.addr); |
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prd.size = le32_to_cpu(prd.size); |
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len = prd.size & 0xfffe;
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if (len == 0) |
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len = 0x10000;
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bm->cur_prd_len = len; |
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bm->cur_prd_addr = prd.addr; |
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bm->cur_prd_last = (prd.size & 0x80000000);
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} |
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if (l > bm->cur_prd_len)
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l = bm->cur_prd_len; |
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if (l > 0) { |
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if (is_write) {
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pci_dma_write(&bm->pci_dev->dev, bm->cur_prd_addr, |
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s->io_buffer + s->io_buffer_index, l); |
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} else {
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pci_dma_read(&bm->pci_dev->dev, bm->cur_prd_addr, |
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s->io_buffer + s->io_buffer_index, l); |
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} |
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bm->cur_prd_addr += l; |
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bm->cur_prd_len -= l; |
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s->io_buffer_index += l; |
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} |
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} |
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return 1; |
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} |
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static int bmdma_set_unit(IDEDMA *dma, int unit) |
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{ |
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); |
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bm->unit = unit; |
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return 0; |
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} |
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static int bmdma_add_status(IDEDMA *dma, int status) |
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{ |
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); |
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bm->status |= status; |
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return 0; |
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} |
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static int bmdma_set_inactive(IDEDMA *dma) |
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{ |
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); |
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bm->status &= ~BM_STATUS_DMAING; |
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bm->dma_cb = NULL;
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bm->unit = -1;
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return 0; |
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} |
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static void bmdma_restart_dma(BMDMAState *bm, enum ide_dma_cmd dma_cmd) |
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{ |
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IDEState *s = bmdma_active_if(bm); |
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ide_set_sector(s, bm->sector_num); |
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s->io_buffer_index = 0;
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s->io_buffer_size = 0;
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s->nsector = bm->nsector; |
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s->dma_cmd = dma_cmd; |
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bm->cur_addr = bm->addr; |
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bm->dma_cb = ide_dma_cb; |
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bmdma_start_dma(&bm->dma, s, bm->dma_cb); |
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} |
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/* TODO This should be common IDE code */
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static void bmdma_restart_bh(void *opaque) |
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{ |
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BMDMAState *bm = opaque; |
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IDEBus *bus = bm->bus; |
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bool is_read;
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int error_status;
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qemu_bh_delete(bm->bh); |
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bm->bh = NULL;
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if (bm->unit == (uint8_t) -1) { |
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return;
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} |
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is_read = (bus->error_status & BM_STATUS_RETRY_READ) != 0;
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/* The error status must be cleared before resubmitting the request: The
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* request may fail again, and this case can only be distinguished if the
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* called function can set a new error status. */
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error_status = bus->error_status; |
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bus->error_status = 0;
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if (error_status & BM_STATUS_DMA_RETRY) {
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if (error_status & BM_STATUS_RETRY_TRIM) {
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bmdma_restart_dma(bm, IDE_DMA_TRIM); |
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} else {
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bmdma_restart_dma(bm, is_read ? IDE_DMA_READ : IDE_DMA_WRITE); |
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} |
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} else if (error_status & BM_STATUS_PIO_RETRY) { |
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if (is_read) {
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ide_sector_read(bmdma_active_if(bm)); |
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} else {
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ide_sector_write(bmdma_active_if(bm)); |
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} |
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} else if (error_status & BM_STATUS_RETRY_FLUSH) { |
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ide_flush_cache(bmdma_active_if(bm)); |
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} |
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} |
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static void bmdma_restart_cb(void *opaque, int running, RunState state) |
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{ |
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IDEDMA *dma = opaque; |
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); |
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if (!running)
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return;
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if (!bm->bh) {
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bm->bh = qemu_bh_new(bmdma_restart_bh, &bm->dma); |
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qemu_bh_schedule(bm->bh); |
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} |
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} |
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static void bmdma_cancel(BMDMAState *bm) |
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{ |
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if (bm->status & BM_STATUS_DMAING) {
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/* cancel DMA request */
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bmdma_set_inactive(&bm->dma); |
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} |
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} |
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static int bmdma_reset(IDEDMA *dma) |
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{ |
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); |
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#ifdef DEBUG_IDE
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printf("ide: dma_reset\n");
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#endif
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bmdma_cancel(bm); |
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bm->cmd = 0;
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bm->status = 0;
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bm->addr = 0;
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bm->cur_addr = 0;
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bm->cur_prd_last = 0;
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bm->cur_prd_addr = 0;
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bm->cur_prd_len = 0;
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bm->sector_num = 0;
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bm->nsector = 0;
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return 0; |
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} |
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static int bmdma_start_transfer(IDEDMA *dma) |
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{ |
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return 0; |
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} |
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static void bmdma_irq(void *opaque, int n, int level) |
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{ |
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BMDMAState *bm = opaque; |
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if (!level) {
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/* pass through lower */
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qemu_set_irq(bm->irq, level); |
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return;
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} |
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bm->status |= BM_STATUS_INT; |
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/* trigger the real irq */
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qemu_set_irq(bm->irq, level); |
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} |
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void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
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{ |
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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/* Ignore writes to SSBM if it keeps the old value */
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if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
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if (!(val & BM_CMD_START)) {
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/*
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* We can't cancel Scatter Gather DMA in the middle of the
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* operation or a partial (not full) DMA transfer would reach
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* the storage so we wait for completion instead (we beahve
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* like if the DMA was completed by the time the guest trying
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* to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
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* set).
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*
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* In the future we'll be able to safely cancel the I/O if the
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* whole DMA operation will be submitted to disk with a single
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* aio operation with preadv/pwritev.
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*/
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if (bm->bus->dma->aiocb) {
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bdrv_drain_all(); |
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assert(bm->bus->dma->aiocb == NULL);
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assert((bm->status & BM_STATUS_DMAING) == 0);
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} |
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} else {
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bm->cur_addr = bm->addr; |
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if (!(bm->status & BM_STATUS_DMAING)) {
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bm->status |= BM_STATUS_DMAING; |
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/* start dma transfer if possible */
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if (bm->dma_cb)
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bm->dma_cb(bmdma_active_if(bm), 0);
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} |
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} |
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} |
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bm->cmd = val & 0x09;
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} |
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static uint64_t bmdma_addr_read(void *opaque, hwaddr addr, |
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unsigned width)
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{ |
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BMDMAState *bm = opaque; |
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uint32_t mask = (1ULL << (width * 8)) - 1; |
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uint64_t data; |
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data = (bm->addr >> (addr * 8)) & mask;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, (unsigned)data); |
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#endif
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return data;
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} |
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|
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static void bmdma_addr_write(void *opaque, hwaddr addr, |
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uint64_t data, unsigned width)
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{ |
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BMDMAState *bm = opaque; |
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int shift = addr * 8; |
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uint32_t mask = (1ULL << (width * 8)) - 1; |
350 |
|
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, (unsigned)data); |
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#endif
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bm->addr &= ~(mask << shift); |
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bm->addr |= ((data & mask) << shift) & ~3;
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} |
357 |
|
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MemoryRegionOps bmdma_addr_ioport_ops = { |
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.read = bmdma_addr_read, |
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.write = bmdma_addr_write, |
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.endianness = DEVICE_LITTLE_ENDIAN, |
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}; |
363 |
|
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static bool ide_bmdma_current_needed(void *opaque) |
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{ |
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BMDMAState *bm = opaque; |
367 |
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return (bm->cur_prd_len != 0); |
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} |
370 |
|
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static bool ide_bmdma_status_needed(void *opaque) |
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{ |
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BMDMAState *bm = opaque; |
374 |
|
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/* Older versions abused some bits in the status register for internal
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* error state. If any of these bits are set, we must add a subsection to
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* transfer the real status register */
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uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS; |
379 |
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return ((bm->status & abused_bits) != 0); |
381 |
} |
382 |
|
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static void ide_bmdma_pre_save(void *opaque) |
384 |
{ |
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BMDMAState *bm = opaque; |
386 |
uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS; |
387 |
|
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bm->migration_compat_status = |
389 |
(bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits); |
390 |
} |
391 |
|
392 |
/* This function accesses bm->bus->error_status which is loaded only after
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* BMDMA itself. This is why the function is called from ide_pci_post_load
|
394 |
* instead of being registered with VMState where it would run too early. */
|
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static int ide_bmdma_post_load(void *opaque, int version_id) |
396 |
{ |
397 |
BMDMAState *bm = opaque; |
398 |
uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS; |
399 |
|
400 |
if (bm->status == 0) { |
401 |
bm->status = bm->migration_compat_status & ~abused_bits; |
402 |
bm->bus->error_status |= bm->migration_compat_status & abused_bits; |
403 |
} |
404 |
|
405 |
return 0; |
406 |
} |
407 |
|
408 |
static const VMStateDescription vmstate_bmdma_current = { |
409 |
.name = "ide bmdma_current",
|
410 |
.version_id = 1,
|
411 |
.minimum_version_id = 1,
|
412 |
.minimum_version_id_old = 1,
|
413 |
.fields = (VMStateField []) { |
414 |
VMSTATE_UINT32(cur_addr, BMDMAState), |
415 |
VMSTATE_UINT32(cur_prd_last, BMDMAState), |
416 |
VMSTATE_UINT32(cur_prd_addr, BMDMAState), |
417 |
VMSTATE_UINT32(cur_prd_len, BMDMAState), |
418 |
VMSTATE_END_OF_LIST() |
419 |
} |
420 |
}; |
421 |
|
422 |
const VMStateDescription vmstate_bmdma_status = {
|
423 |
.name ="ide bmdma/status",
|
424 |
.version_id = 1,
|
425 |
.minimum_version_id = 1,
|
426 |
.minimum_version_id_old = 1,
|
427 |
.fields = (VMStateField []) { |
428 |
VMSTATE_UINT8(status, BMDMAState), |
429 |
VMSTATE_END_OF_LIST() |
430 |
} |
431 |
}; |
432 |
|
433 |
static const VMStateDescription vmstate_bmdma = { |
434 |
.name = "ide bmdma",
|
435 |
.version_id = 3,
|
436 |
.minimum_version_id = 0,
|
437 |
.minimum_version_id_old = 0,
|
438 |
.pre_save = ide_bmdma_pre_save, |
439 |
.fields = (VMStateField []) { |
440 |
VMSTATE_UINT8(cmd, BMDMAState), |
441 |
VMSTATE_UINT8(migration_compat_status, BMDMAState), |
442 |
VMSTATE_UINT32(addr, BMDMAState), |
443 |
VMSTATE_INT64(sector_num, BMDMAState), |
444 |
VMSTATE_UINT32(nsector, BMDMAState), |
445 |
VMSTATE_UINT8(unit, BMDMAState), |
446 |
VMSTATE_END_OF_LIST() |
447 |
}, |
448 |
.subsections = (VMStateSubsection []) { |
449 |
{ |
450 |
.vmsd = &vmstate_bmdma_current, |
451 |
.needed = ide_bmdma_current_needed, |
452 |
}, { |
453 |
.vmsd = &vmstate_bmdma_status, |
454 |
.needed = ide_bmdma_status_needed, |
455 |
}, { |
456 |
/* empty */
|
457 |
} |
458 |
} |
459 |
}; |
460 |
|
461 |
static int ide_pci_post_load(void *opaque, int version_id) |
462 |
{ |
463 |
PCIIDEState *d = opaque; |
464 |
int i;
|
465 |
|
466 |
for(i = 0; i < 2; i++) { |
467 |
/* current versions always store 0/1, but older version
|
468 |
stored bigger values. We only need last bit */
|
469 |
d->bmdma[i].unit &= 1;
|
470 |
ide_bmdma_post_load(&d->bmdma[i], -1);
|
471 |
} |
472 |
|
473 |
return 0; |
474 |
} |
475 |
|
476 |
const VMStateDescription vmstate_ide_pci = {
|
477 |
.name = "ide",
|
478 |
.version_id = 3,
|
479 |
.minimum_version_id = 0,
|
480 |
.minimum_version_id_old = 0,
|
481 |
.post_load = ide_pci_post_load, |
482 |
.fields = (VMStateField []) { |
483 |
VMSTATE_PCI_DEVICE(dev, PCIIDEState), |
484 |
VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0, |
485 |
vmstate_bmdma, BMDMAState), |
486 |
VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
|
487 |
VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
|
488 |
VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
|
489 |
VMSTATE_END_OF_LIST() |
490 |
} |
491 |
}; |
492 |
|
493 |
void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
|
494 |
{ |
495 |
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); |
496 |
static const int bus[4] = { 0, 0, 1, 1 }; |
497 |
static const int unit[4] = { 0, 1, 0, 1 }; |
498 |
int i;
|
499 |
|
500 |
for (i = 0; i < 4; i++) { |
501 |
if (hd_table[i] == NULL) |
502 |
continue;
|
503 |
ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]); |
504 |
} |
505 |
} |
506 |
|
507 |
static const struct IDEDMAOps bmdma_ops = { |
508 |
.start_dma = bmdma_start_dma, |
509 |
.start_transfer = bmdma_start_transfer, |
510 |
.prepare_buf = bmdma_prepare_buf, |
511 |
.rw_buf = bmdma_rw_buf, |
512 |
.set_unit = bmdma_set_unit, |
513 |
.add_status = bmdma_add_status, |
514 |
.set_inactive = bmdma_set_inactive, |
515 |
.restart_cb = bmdma_restart_cb, |
516 |
.reset = bmdma_reset, |
517 |
}; |
518 |
|
519 |
void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
|
520 |
{ |
521 |
qemu_irq *irq; |
522 |
|
523 |
if (bus->dma == &bm->dma) {
|
524 |
return;
|
525 |
} |
526 |
|
527 |
bm->dma.ops = &bmdma_ops; |
528 |
bus->dma = &bm->dma; |
529 |
bm->irq = bus->irq; |
530 |
irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
|
531 |
bus->irq = *irq; |
532 |
bm->pci_dev = d; |
533 |
} |