root / hw / imx_timer.c @ a8170e5e
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/*
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* IMX31 Timer
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*
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* Copyright (c) 2008 OK Labs
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* Copyright (c) 2011 NICTA Pty Ltd
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* Originally written by Hans Jiang
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* Updated by Peter Chubb
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*
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* This code is licensed under GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*
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*/
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#include "hw.h" |
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#include "qemu-timer.h" |
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#include "ptimer.h" |
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#include "sysbus.h" |
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#include "imx.h" |
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//#define DEBUG_TIMER 1
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#ifdef DEBUG_TIMER
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# define DPRINTF(fmt, args...) \
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do { printf("imx_timer: " fmt , ##args); } while (0) |
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#else
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# define DPRINTF(fmt, args...) do {} while (0) |
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#endif
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/*
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* Define to 1 for messages about attempts to
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* access unimplemented registers or similar.
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*/
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#define DEBUG_IMPLEMENTATION 1 |
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#if DEBUG_IMPLEMENTATION
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# define IPRINTF(fmt, args...) \
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do { fprintf(stderr, "imx_timer: " fmt, ##args); } while (0) |
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#else
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# define IPRINTF(fmt, args...) do {} while (0) |
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#endif
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/*
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* GPT : General purpose timer
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*
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* This timer counts up continuously while it is enabled, resetting itself
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* to 0 when it reaches TIMER_MAX (in freerun mode) or when it
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* reaches the value of ocr1 (in periodic mode). WE simulate this using a
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* QEMU ptimer counting down from ocr1 and reloading from ocr1 in
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* periodic mode, or counting from ocr1 to zero, then TIMER_MAX - ocr1.
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* waiting_rov is set when counting from TIMER_MAX.
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*
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* In the real hardware, there are three comparison registers that can
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* trigger interrupts, and compare channel 1 can be used to
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* force-reset the timer. However, this is a `bare-bones'
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* implementation: only what Linux 3.x uses has been implemented
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* (free-running timer from 0 to OCR1 or TIMER_MAX) .
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*/
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#define TIMER_MAX 0XFFFFFFFFUL |
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/* Control register. Not all of these bits have any effect (yet) */
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#define GPT_CR_EN (1 << 0) /* GPT Enable */ |
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#define GPT_CR_ENMOD (1 << 1) /* GPT Enable Mode */ |
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#define GPT_CR_DBGEN (1 << 2) /* GPT Debug mode enable */ |
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#define GPT_CR_WAITEN (1 << 3) /* GPT Wait Mode Enable */ |
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#define GPT_CR_DOZEN (1 << 4) /* GPT Doze mode enable */ |
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#define GPT_CR_STOPEN (1 << 5) /* GPT Stop Mode Enable */ |
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#define GPT_CR_CLKSRC_SHIFT (6) |
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#define GPT_CR_CLKSRC_MASK (0x7) |
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#define GPT_CR_FRR (1 << 9) /* Freerun or Restart */ |
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#define GPT_CR_SWR (1 << 15) /* Software Reset */ |
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#define GPT_CR_IM1 (3 << 16) /* Input capture channel 1 mode (2 bits) */ |
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#define GPT_CR_IM2 (3 << 18) /* Input capture channel 2 mode (2 bits) */ |
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#define GPT_CR_OM1 (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */ |
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#define GPT_CR_OM2 (7 << 23) /* Output Compare Channel 2 Mode (3 bits) */ |
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#define GPT_CR_OM3 (7 << 26) /* Output Compare Channel 3 Mode (3 bits) */ |
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#define GPT_CR_FO1 (1 << 29) /* Force Output Compare Channel 1 */ |
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#define GPT_CR_FO2 (1 << 30) /* Force Output Compare Channel 2 */ |
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#define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */ |
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#define GPT_SR_OF1 (1 << 0) |
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#define GPT_SR_ROV (1 << 5) |
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#define GPT_IR_OF1IE (1 << 0) |
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#define GPT_IR_ROVIE (1 << 5) |
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typedef struct { |
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SysBusDevice busdev; |
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ptimer_state *timer; |
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MemoryRegion iomem; |
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DeviceState *ccm; |
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uint32_t cr; |
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uint32_t pr; |
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uint32_t sr; |
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uint32_t ir; |
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uint32_t ocr1; |
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uint32_t cnt; |
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uint32_t waiting_rov; |
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qemu_irq irq; |
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} IMXTimerGState; |
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static const VMStateDescription vmstate_imx_timerg = { |
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.name = "imx-timerg",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) { |
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VMSTATE_UINT32(cr, IMXTimerGState), |
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VMSTATE_UINT32(pr, IMXTimerGState), |
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VMSTATE_UINT32(sr, IMXTimerGState), |
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VMSTATE_UINT32(ir, IMXTimerGState), |
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VMSTATE_UINT32(ocr1, IMXTimerGState), |
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VMSTATE_UINT32(cnt, IMXTimerGState), |
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VMSTATE_UINT32(waiting_rov, IMXTimerGState), |
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VMSTATE_PTIMER(timer, IMXTimerGState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const IMXClk imx_timerg_clocks[] = { |
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NOCLK, /* 000 No clock source */
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IPG, /* 001 ipg_clk, 532MHz*/
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IPG, /* 010 ipg_clk_highfreq */
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NOCLK, /* 011 not defined */
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CLK_32k, /* 100 ipg_clk_32k */
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NOCLK, /* 101 not defined */
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NOCLK, /* 110 not defined */
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NOCLK, /* 111 not defined */
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}; |
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static void imx_timerg_set_freq(IMXTimerGState *s) |
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{ |
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int clksrc;
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uint32_t freq; |
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clksrc = (s->cr >> GPT_CR_CLKSRC_SHIFT) & GPT_CR_CLKSRC_MASK; |
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freq = imx_clock_frequency(s->ccm, imx_timerg_clocks[clksrc]) / (1 + s->pr);
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DPRINTF("Setting gtimer clksrc %d to frequency %d\n", clksrc, freq);
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if (freq) {
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ptimer_set_freq(s->timer, freq); |
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} |
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} |
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static void imx_timerg_update(IMXTimerGState *s) |
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{ |
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uint32_t flags = s->sr & s->ir & (GPT_SR_OF1 | GPT_SR_ROV); |
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DPRINTF("g-timer SR: %s %s IR=%s %s, %s\n",
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s->sr & GPT_SR_OF1 ? "OF1" : "", |
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s->sr & GPT_SR_ROV ? "ROV" : "", |
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s->ir & GPT_SR_OF1 ? "OF1" : "", |
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s->ir & GPT_SR_ROV ? "ROV" : "", |
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s->cr & GPT_CR_EN ? "CR_EN" : "Not Enabled"); |
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qemu_set_irq(s->irq, (s->cr & GPT_CR_EN) && flags); |
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} |
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static uint32_t imx_timerg_update_counts(IMXTimerGState *s)
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{ |
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uint64_t target = s->waiting_rov ? TIMER_MAX : s->ocr1; |
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uint64_t cnt = ptimer_get_count(s->timer); |
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s->cnt = target - cnt; |
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return s->cnt;
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} |
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static void imx_timerg_reload(IMXTimerGState *s, uint32_t timeout) |
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{ |
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uint64_t diff_cnt; |
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if (!(s->cr & GPT_CR_FRR)) {
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IPRINTF("IMX_timerg_reload --- called in reset-mode\n");
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return;
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} |
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/*
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* For small timeouts, qemu sometimes runs too slow.
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* Better deliver a late interrupt than none.
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*
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* In Reset mode (FRR bit clear)
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* the ptimer reloads itself from OCR1;
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* in free-running mode we need to fake
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* running from 0 to ocr1 to TIMER_MAX
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*/
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if (timeout > s->cnt) {
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diff_cnt = timeout - s->cnt; |
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} else {
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diff_cnt = 0;
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} |
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ptimer_set_count(s->timer, diff_cnt); |
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} |
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static uint64_t imx_timerg_read(void *opaque, hwaddr offset, |
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unsigned size)
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{ |
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IMXTimerGState *s = (IMXTimerGState *)opaque; |
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DPRINTF("g-read(offset=%x)", offset >> 2); |
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switch (offset >> 2) { |
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case 0: /* Control Register */ |
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DPRINTF(" cr = %x\n", s->cr);
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return s->cr;
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case 1: /* prescaler */ |
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DPRINTF(" pr = %x\n", s->pr);
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return s->pr;
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case 2: /* Status Register */ |
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DPRINTF(" sr = %x\n", s->sr);
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return s->sr;
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case 3: /* Interrupt Register */ |
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DPRINTF(" ir = %x\n", s->ir);
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return s->ir;
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case 4: /* Output Compare Register 1 */ |
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DPRINTF(" ocr1 = %x\n", s->ocr1);
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return s->ocr1;
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case 9: /* cnt */ |
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imx_timerg_update_counts(s); |
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DPRINTF(" cnt = %x\n", s->cnt);
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return s->cnt;
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} |
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IPRINTF("imx_timerg_read: Bad offset %x\n",
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(int)offset >> 2); |
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return 0; |
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} |
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static void imx_timerg_reset(DeviceState *dev) |
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{ |
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IMXTimerGState *s = container_of(dev, IMXTimerGState, busdev.qdev); |
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/*
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* Soft reset doesn't touch some bits; hard reset clears them
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*/
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s->cr &= ~(GPT_CR_EN|GPT_CR_DOZEN|GPT_CR_WAITEN|GPT_CR_DBGEN); |
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s->sr = 0;
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s->pr = 0;
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s->ir = 0;
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s->cnt = 0;
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s->ocr1 = TIMER_MAX; |
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ptimer_stop(s->timer); |
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ptimer_set_limit(s->timer, TIMER_MAX, 1);
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imx_timerg_set_freq(s); |
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} |
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static void imx_timerg_write(void *opaque, hwaddr offset, |
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uint64_t value, unsigned size)
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{ |
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IMXTimerGState *s = (IMXTimerGState *)opaque; |
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DPRINTF("g-write(offset=%x, value = 0x%x)\n", (unsigned int)offset >> 2, |
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(unsigned int)value); |
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switch (offset >> 2) { |
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case 0: { |
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uint32_t oldcr = s->cr; |
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/* CR */
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if (value & GPT_CR_SWR) { /* force reset */ |
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value &= ~GPT_CR_SWR; |
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imx_timerg_reset(&s->busdev.qdev); |
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imx_timerg_update(s); |
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} |
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s->cr = value & ~0x7c00;
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imx_timerg_set_freq(s); |
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if ((oldcr ^ value) & GPT_CR_EN) {
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if (value & GPT_CR_EN) {
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if (value & GPT_CR_ENMOD) {
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ptimer_set_count(s->timer, s->ocr1); |
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s->cnt = 0;
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} |
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ptimer_run(s->timer, |
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(value & GPT_CR_FRR) && (s->ocr1 != TIMER_MAX)); |
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} else {
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ptimer_stop(s->timer); |
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}; |
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} |
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return;
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} |
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case 1: /* Prescaler */ |
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s->pr = value & 0xfff;
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imx_timerg_set_freq(s); |
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return;
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case 2: /* SR */ |
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/*
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* No point in implementing the status register bits to do with
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* external interrupt sources.
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*/
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value &= GPT_SR_OF1 | GPT_SR_ROV; |
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s->sr &= ~value; |
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imx_timerg_update(s); |
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return;
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case 3: /* IR -- interrupt register */ |
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s->ir = value & 0x3f;
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imx_timerg_update(s); |
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return;
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case 4: /* OCR1 -- output compare register */ |
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/* In non-freerun mode, reset count when this register is written */
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if (!(s->cr & GPT_CR_FRR)) {
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s->waiting_rov = 0;
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ptimer_set_limit(s->timer, value, 1);
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} else {
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imx_timerg_update_counts(s); |
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if (value > s->cnt) {
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s->waiting_rov = 0;
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imx_timerg_reload(s, value); |
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} else {
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s->waiting_rov = 1;
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imx_timerg_reload(s, TIMER_MAX - s->cnt); |
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} |
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} |
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s->ocr1 = value; |
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return;
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default:
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IPRINTF("imx_timerg_write: Bad offset %x\n",
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(int)offset >> 2); |
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} |
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} |
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static void imx_timerg_timeout(void *opaque) |
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{ |
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IMXTimerGState *s = (IMXTimerGState *)opaque; |
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DPRINTF("imx_timerg_timeout, waiting rov=%d\n", s->waiting_rov);
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if (s->cr & GPT_CR_FRR) {
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/*
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* Free running timer from 0 -> TIMERMAX
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* Generates interrupt at TIMER_MAX and at cnt==ocr1
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* If ocr1 == TIMER_MAX, then no need to reload timer.
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*/
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if (s->ocr1 == TIMER_MAX) {
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DPRINTF("s->ocr1 == TIMER_MAX, FRR\n");
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s->sr |= GPT_SR_OF1 | GPT_SR_ROV; |
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imx_timerg_update(s); |
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return;
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} |
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if (s->waiting_rov) {
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/*
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* We were waiting for cnt==TIMER_MAX
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*/
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s->sr |= GPT_SR_ROV; |
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s->waiting_rov = 0;
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s->cnt = 0;
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imx_timerg_reload(s, s->ocr1); |
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} else {
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/* Must have got a cnt==ocr1 timeout. */
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s->sr |= GPT_SR_OF1; |
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s->cnt = s->ocr1; |
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s->waiting_rov = 1;
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imx_timerg_reload(s, TIMER_MAX); |
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} |
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imx_timerg_update(s); |
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return;
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} |
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s->sr |= GPT_SR_OF1; |
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imx_timerg_update(s); |
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} |
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static const MemoryRegionOps imx_timerg_ops = { |
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.read = imx_timerg_read, |
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.write = imx_timerg_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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|
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static int imx_timerg_init(SysBusDevice *dev) |
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{ |
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IMXTimerGState *s = FROM_SYSBUS(IMXTimerGState, dev); |
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QEMUBH *bh; |
384 |
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sysbus_init_irq(dev, &s->irq); |
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memory_region_init_io(&s->iomem, &imx_timerg_ops, |
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s, "imxg-timer",
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0x00001000);
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sysbus_init_mmio(dev, &s->iomem); |
390 |
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bh = qemu_bh_new(imx_timerg_timeout, s); |
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s->timer = ptimer_init(bh); |
393 |
|
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/* Hard reset resets extra bits in CR */
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s->cr = 0;
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return 0; |
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} |
398 |
|
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|
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|
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/*
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* EPIT: Enhanced periodic interrupt timer
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*/
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|
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#define CR_EN (1 << 0) |
406 |
#define CR_ENMOD (1 << 1) |
407 |
#define CR_OCIEN (1 << 2) |
408 |
#define CR_RLD (1 << 3) |
409 |
#define CR_PRESCALE_SHIFT (4) |
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#define CR_PRESCALE_MASK (0xfff) |
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#define CR_SWR (1 << 16) |
412 |
#define CR_IOVW (1 << 17) |
413 |
#define CR_DBGEN (1 << 18) |
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#define CR_EPIT (1 << 19) |
415 |
#define CR_DOZEN (1 << 20) |
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#define CR_STOPEN (1 << 21) |
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#define CR_CLKSRC_SHIFT (24) |
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#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT) |
419 |
|
420 |
|
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/*
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* Exact clock frequencies vary from board to board.
|
423 |
* These are typical.
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*/
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static const IMXClk imx_timerp_clocks[] = { |
426 |
0, /* disabled */ |
427 |
IPG, /* ipg_clk, ~532MHz */
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428 |
IPG, /* ipg_clk_highfreq */
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CLK_32k, /* ipg_clk_32k -- ~32kHz */
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}; |
431 |
|
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typedef struct { |
433 |
SysBusDevice busdev; |
434 |
ptimer_state *timer; |
435 |
MemoryRegion iomem; |
436 |
DeviceState *ccm; |
437 |
|
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uint32_t cr; |
439 |
uint32_t lr; |
440 |
uint32_t cmp; |
441 |
|
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uint32_t freq; |
443 |
int int_level;
|
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qemu_irq irq; |
445 |
} IMXTimerPState; |
446 |
|
447 |
/*
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* Update interrupt status
|
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*/
|
450 |
static void imx_timerp_update(IMXTimerPState *s) |
451 |
{ |
452 |
if (s->int_level && (s->cr & CR_OCIEN)) {
|
453 |
qemu_irq_raise(s->irq); |
454 |
} else {
|
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qemu_irq_lower(s->irq); |
456 |
} |
457 |
} |
458 |
|
459 |
static void imx_timerp_reset(DeviceState *dev) |
460 |
{ |
461 |
IMXTimerPState *s = container_of(dev, IMXTimerPState, busdev.qdev); |
462 |
|
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s->cr = 0;
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s->lr = TIMER_MAX; |
465 |
s->int_level = 0;
|
466 |
s->cmp = 0;
|
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ptimer_stop(s->timer); |
468 |
ptimer_set_count(s->timer, TIMER_MAX); |
469 |
} |
470 |
|
471 |
static uint64_t imx_timerp_read(void *opaque, hwaddr offset, |
472 |
unsigned size)
|
473 |
{ |
474 |
IMXTimerPState *s = (IMXTimerPState *)opaque; |
475 |
|
476 |
DPRINTF("p-read(offset=%x)", offset >> 2); |
477 |
switch (offset >> 2) { |
478 |
case 0: /* Control Register */ |
479 |
DPRINTF("cr %x\n", s->cr);
|
480 |
return s->cr;
|
481 |
|
482 |
case 1: /* Status Register */ |
483 |
DPRINTF("int_level %x\n", s->int_level);
|
484 |
return s->int_level;
|
485 |
|
486 |
case 2: /* LR - ticks*/ |
487 |
DPRINTF("lr %x\n", s->lr);
|
488 |
return s->lr;
|
489 |
|
490 |
case 3: /* CMP */ |
491 |
DPRINTF("cmp %x\n", s->cmp);
|
492 |
return s->cmp;
|
493 |
|
494 |
case 4: /* CNT */ |
495 |
return ptimer_get_count(s->timer);
|
496 |
} |
497 |
IPRINTF("imx_timerp_read: Bad offset %x\n",
|
498 |
(int)offset >> 2); |
499 |
return 0; |
500 |
} |
501 |
|
502 |
static void set_timerp_freq(IMXTimerPState *s) |
503 |
{ |
504 |
int clksrc;
|
505 |
unsigned prescaler;
|
506 |
uint32_t freq; |
507 |
|
508 |
clksrc = (s->cr & CR_CLKSRC_MASK) >> CR_CLKSRC_SHIFT; |
509 |
prescaler = 1 + ((s->cr >> CR_PRESCALE_SHIFT) & CR_PRESCALE_MASK);
|
510 |
freq = imx_clock_frequency(s->ccm, imx_timerp_clocks[clksrc]) / prescaler; |
511 |
|
512 |
s->freq = freq; |
513 |
DPRINTF("Setting ptimer frequency to %u\n", freq);
|
514 |
|
515 |
if (freq) {
|
516 |
ptimer_set_freq(s->timer, freq); |
517 |
} |
518 |
} |
519 |
|
520 |
static void imx_timerp_write(void *opaque, hwaddr offset, |
521 |
uint64_t value, unsigned size)
|
522 |
{ |
523 |
IMXTimerPState *s = (IMXTimerPState *)opaque; |
524 |
DPRINTF("p-write(offset=%x, value = %x)\n", (unsigned int)offset >> 2, |
525 |
(unsigned int)value); |
526 |
|
527 |
switch (offset >> 2) { |
528 |
case 0: /* CR */ |
529 |
if (value & CR_SWR) {
|
530 |
imx_timerp_reset(&s->busdev.qdev); |
531 |
value &= ~CR_SWR; |
532 |
} |
533 |
s->cr = value & 0x03ffffff;
|
534 |
set_timerp_freq(s); |
535 |
|
536 |
if (s->freq && (s->cr & CR_EN)) {
|
537 |
if (!(s->cr & CR_ENMOD)) {
|
538 |
ptimer_set_count(s->timer, s->lr); |
539 |
} |
540 |
ptimer_run(s->timer, 0);
|
541 |
} else {
|
542 |
ptimer_stop(s->timer); |
543 |
} |
544 |
break;
|
545 |
|
546 |
case 1: /* SR - ACK*/ |
547 |
s->int_level = 0;
|
548 |
imx_timerp_update(s); |
549 |
break;
|
550 |
|
551 |
case 2: /* LR - set ticks */ |
552 |
s->lr = value; |
553 |
ptimer_set_limit(s->timer, value, !!(s->cr & CR_IOVW)); |
554 |
break;
|
555 |
|
556 |
case 3: /* CMP */ |
557 |
s->cmp = value; |
558 |
if (value) {
|
559 |
IPRINTF( |
560 |
"Values for EPIT comparison other than zero not supported\n"
|
561 |
); |
562 |
} |
563 |
break;
|
564 |
|
565 |
default:
|
566 |
IPRINTF("imx_timerp_write: Bad offset %x\n",
|
567 |
(int)offset >> 2); |
568 |
} |
569 |
} |
570 |
|
571 |
static void imx_timerp_tick(void *opaque) |
572 |
{ |
573 |
IMXTimerPState *s = (IMXTimerPState *)opaque; |
574 |
|
575 |
DPRINTF("imxp tick\n");
|
576 |
if (!(s->cr & CR_RLD)) {
|
577 |
ptimer_set_count(s->timer, TIMER_MAX); |
578 |
} |
579 |
s->int_level = 1;
|
580 |
imx_timerp_update(s); |
581 |
} |
582 |
|
583 |
void imx_timerp_create(const hwaddr addr, |
584 |
qemu_irq irq, |
585 |
DeviceState *ccm) |
586 |
{ |
587 |
IMXTimerPState *pp; |
588 |
DeviceState *dev; |
589 |
|
590 |
dev = sysbus_create_simple("imx_timerp", addr, irq);
|
591 |
pp = container_of(dev, IMXTimerPState, busdev.qdev); |
592 |
pp->ccm = ccm; |
593 |
} |
594 |
|
595 |
static const MemoryRegionOps imx_timerp_ops = { |
596 |
.read = imx_timerp_read, |
597 |
.write = imx_timerp_write, |
598 |
.endianness = DEVICE_NATIVE_ENDIAN, |
599 |
}; |
600 |
|
601 |
static const VMStateDescription vmstate_imx_timerp = { |
602 |
.name = "imx-timerp",
|
603 |
.version_id = 1,
|
604 |
.minimum_version_id = 1,
|
605 |
.minimum_version_id_old = 1,
|
606 |
.fields = (VMStateField[]) { |
607 |
VMSTATE_UINT32(cr, IMXTimerPState), |
608 |
VMSTATE_UINT32(lr, IMXTimerPState), |
609 |
VMSTATE_UINT32(cmp, IMXTimerPState), |
610 |
VMSTATE_UINT32(freq, IMXTimerPState), |
611 |
VMSTATE_INT32(int_level, IMXTimerPState), |
612 |
VMSTATE_PTIMER(timer, IMXTimerPState), |
613 |
VMSTATE_END_OF_LIST() |
614 |
} |
615 |
}; |
616 |
|
617 |
static int imx_timerp_init(SysBusDevice *dev) |
618 |
{ |
619 |
IMXTimerPState *s = FROM_SYSBUS(IMXTimerPState, dev); |
620 |
QEMUBH *bh; |
621 |
|
622 |
DPRINTF("imx_timerp_init\n");
|
623 |
|
624 |
sysbus_init_irq(dev, &s->irq); |
625 |
memory_region_init_io(&s->iomem, &imx_timerp_ops, |
626 |
s, "imxp-timer",
|
627 |
0x00001000);
|
628 |
sysbus_init_mmio(dev, &s->iomem); |
629 |
|
630 |
bh = qemu_bh_new(imx_timerp_tick, s); |
631 |
s->timer = ptimer_init(bh); |
632 |
|
633 |
return 0; |
634 |
} |
635 |
|
636 |
|
637 |
void imx_timerg_create(const hwaddr addr, |
638 |
qemu_irq irq, |
639 |
DeviceState *ccm) |
640 |
{ |
641 |
IMXTimerGState *pp; |
642 |
DeviceState *dev; |
643 |
|
644 |
dev = sysbus_create_simple("imx_timerg", addr, irq);
|
645 |
pp = container_of(dev, IMXTimerGState, busdev.qdev); |
646 |
pp->ccm = ccm; |
647 |
} |
648 |
|
649 |
static void imx_timerg_class_init(ObjectClass *klass, void *data) |
650 |
{ |
651 |
DeviceClass *dc = DEVICE_CLASS(klass); |
652 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
653 |
k->init = imx_timerg_init; |
654 |
dc->vmsd = &vmstate_imx_timerg; |
655 |
dc->reset = imx_timerg_reset; |
656 |
dc->desc = "i.MX general timer";
|
657 |
} |
658 |
|
659 |
static void imx_timerp_class_init(ObjectClass *klass, void *data) |
660 |
{ |
661 |
DeviceClass *dc = DEVICE_CLASS(klass); |
662 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
663 |
k->init = imx_timerp_init; |
664 |
dc->vmsd = &vmstate_imx_timerp; |
665 |
dc->reset = imx_timerp_reset; |
666 |
dc->desc = "i.MX periodic timer";
|
667 |
} |
668 |
|
669 |
static const TypeInfo imx_timerp_info = { |
670 |
.name = "imx_timerp",
|
671 |
.parent = TYPE_SYS_BUS_DEVICE, |
672 |
.instance_size = sizeof(IMXTimerPState),
|
673 |
.class_init = imx_timerp_class_init, |
674 |
}; |
675 |
|
676 |
static const TypeInfo imx_timerg_info = { |
677 |
.name = "imx_timerg",
|
678 |
.parent = TYPE_SYS_BUS_DEVICE, |
679 |
.instance_size = sizeof(IMXTimerGState),
|
680 |
.class_init = imx_timerg_class_init, |
681 |
}; |
682 |
|
683 |
static void imx_timer_register_types(void) |
684 |
{ |
685 |
type_register_static(&imx_timerp_info); |
686 |
type_register_static(&imx_timerg_info); |
687 |
} |
688 |
|
689 |
type_init(imx_timer_register_types) |