root / hw / kvm / pci-assign.c @ a8170e5e
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/*
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* Copyright (c) 2007, Neocleus Corporation.
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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*
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* Assign a PCI device from the host to a guest VM.
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*
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* This implementation uses the classic device assignment interface of KVM
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* and is only available on x86 hosts. It is expected to be obsoleted by VFIO
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* based device assignment.
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*
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* Adapted for KVM (qemu-kvm) by Qumranet. QEMU version was based on qemu-kvm
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* revision 4144fe9d48. See its repository for the history.
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*
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* Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com)
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* Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com)
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* Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com)
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* Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com)
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* Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com)
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*/
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#include <stdio.h> |
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#include <unistd.h> |
| 25 |
#include <sys/io.h> |
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#include <sys/mman.h> |
| 27 |
#include <sys/types.h> |
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#include <sys/stat.h> |
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#include "hw/hw.h" |
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#include "hw/pc.h" |
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#include "qemu-error.h" |
| 32 |
#include "console.h" |
| 33 |
#include "hw/loader.h" |
| 34 |
#include "monitor.h" |
| 35 |
#include "range.h" |
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#include "sysemu.h" |
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#include "hw/pci.h" |
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#include "hw/msi.h" |
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#include "kvm_i386.h" |
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|
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#define MSIX_PAGE_SIZE 0x1000 |
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|
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/* From linux/ioport.h */
|
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#define IORESOURCE_IO 0x00000100 /* Resource type */ |
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#define IORESOURCE_MEM 0x00000200 |
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#define IORESOURCE_IRQ 0x00000400 |
| 47 |
#define IORESOURCE_DMA 0x00000800 |
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#define IORESOURCE_PREFETCH 0x00002000 /* No side effects */ |
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|
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//#define DEVICE_ASSIGNMENT_DEBUG
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|
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#ifdef DEVICE_ASSIGNMENT_DEBUG
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#define DEBUG(fmt, ...) \
|
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do { \
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fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__); \
|
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} while (0) |
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#else
|
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#define DEBUG(fmt, ...)
|
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#endif
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|
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typedef struct PCIRegion { |
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int type; /* Memory or port I/O */ |
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int valid;
|
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uint64_t base_addr; |
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uint64_t size; /* size of the region */
|
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int resource_fd;
|
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} PCIRegion; |
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|
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typedef struct PCIDevRegions { |
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uint8_t bus, dev, func; /* Bus inside domain, device and function */
|
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int irq; /* IRQ number */ |
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uint16_t region_number; /* number of active regions */
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|
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/* Port I/O or MMIO Regions */
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PCIRegion regions[PCI_NUM_REGIONS - 1];
|
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int config_fd;
|
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} PCIDevRegions; |
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|
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typedef struct AssignedDevRegion { |
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MemoryRegion container; |
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MemoryRegion real_iomem; |
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union {
|
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uint8_t *r_virtbase; /* mmapped access address for memory regions */
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uint32_t r_baseport; /* the base guest port for I/O regions */
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} u; |
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pcibus_t e_size; /* emulated size of region in bytes */
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pcibus_t r_size; /* real size of region in bytes */
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PCIRegion *region; |
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} AssignedDevRegion; |
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|
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#define ASSIGNED_DEVICE_PREFER_MSI_BIT 0 |
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#define ASSIGNED_DEVICE_SHARE_INTX_BIT 1 |
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|
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#define ASSIGNED_DEVICE_PREFER_MSI_MASK (1 << ASSIGNED_DEVICE_PREFER_MSI_BIT) |
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#define ASSIGNED_DEVICE_SHARE_INTX_MASK (1 << ASSIGNED_DEVICE_SHARE_INTX_BIT) |
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|
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typedef struct MSIXTableEntry { |
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uint32_t addr_lo; |
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uint32_t addr_hi; |
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uint32_t data; |
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uint32_t ctrl; |
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} MSIXTableEntry; |
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|
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typedef enum AssignedIRQType { |
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ASSIGNED_IRQ_NONE = 0,
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ASSIGNED_IRQ_INTX_HOST_INTX, |
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ASSIGNED_IRQ_INTX_HOST_MSI, |
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ASSIGNED_IRQ_MSI, |
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ASSIGNED_IRQ_MSIX |
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} AssignedIRQType; |
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|
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typedef struct AssignedDevice { |
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PCIDevice dev; |
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PCIHostDeviceAddress host; |
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uint32_t dev_id; |
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uint32_t features; |
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int intpin;
|
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AssignedDevRegion v_addrs[PCI_NUM_REGIONS - 1];
|
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PCIDevRegions real_device; |
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PCIINTxRoute intx_route; |
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AssignedIRQType assigned_irq_type; |
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struct {
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#define ASSIGNED_DEVICE_CAP_MSI (1 << 0) |
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#define ASSIGNED_DEVICE_CAP_MSIX (1 << 1) |
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uint32_t available; |
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#define ASSIGNED_DEVICE_MSI_ENABLED (1 << 0) |
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#define ASSIGNED_DEVICE_MSIX_ENABLED (1 << 1) |
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#define ASSIGNED_DEVICE_MSIX_MASKED (1 << 2) |
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uint32_t state; |
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} cap; |
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uint8_t emulate_config_read[PCI_CONFIG_SPACE_SIZE]; |
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uint8_t emulate_config_write[PCI_CONFIG_SPACE_SIZE]; |
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int msi_virq_nr;
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int *msi_virq;
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MSIXTableEntry *msix_table; |
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hwaddr msix_table_addr; |
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uint16_t msix_max; |
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MemoryRegion mmio; |
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char *configfd_name;
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int32_t bootindex; |
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} AssignedDevice; |
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|
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static void assigned_dev_update_irq_routing(PCIDevice *dev); |
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|
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static void assigned_dev_load_option_rom(AssignedDevice *dev); |
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|
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static void assigned_dev_unregister_msix_mmio(AssignedDevice *dev); |
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|
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static uint64_t assigned_dev_ioport_rw(AssignedDevRegion *dev_region,
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hwaddr addr, int size,
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uint64_t *data) |
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{
|
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uint64_t val = 0;
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int fd = dev_region->region->resource_fd;
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|
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if (fd >= 0) { |
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if (data) {
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DEBUG("pwrite data=%" PRIx64 ", size=%d, e_phys=" TARGET_FMT_plx |
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", addr="TARGET_FMT_plx"\n", *data, size, addr, addr); |
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if (pwrite(fd, data, size, addr) != size) {
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error_report("%s - pwrite failed %s",
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__func__, strerror(errno)); |
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} |
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} else {
|
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if (pread(fd, &val, size, addr) != size) {
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error_report("%s - pread failed %s",
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__func__, strerror(errno)); |
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val = (1UL << (size * 8)) - 1; |
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} |
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DEBUG("pread val=%" PRIx64 ", size=%d, e_phys=" TARGET_FMT_plx |
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", addr=" TARGET_FMT_plx "\n", val, size, addr, addr); |
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} |
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} else {
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uint32_t port = addr + dev_region->u.r_baseport; |
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|
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if (data) {
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DEBUG("out data=%" PRIx64 ", size=%d, e_phys=" TARGET_FMT_plx |
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", host=%x\n", *data, size, addr, port);
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switch (size) {
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case 1: |
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outb(*data, port); |
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break;
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case 2: |
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outw(*data, port); |
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break;
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case 4: |
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outl(*data, port); |
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break;
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} |
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} else {
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switch (size) {
|
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case 1: |
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val = inb(port); |
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break;
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case 2: |
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val = inw(port); |
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break;
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case 4: |
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val = inl(port); |
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break;
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} |
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DEBUG("in data=%" PRIx64 ", size=%d, e_phys=" TARGET_FMT_plx |
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", host=%x\n", val, size, addr, port);
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} |
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} |
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return val;
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} |
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|
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static void assigned_dev_ioport_write(void *opaque, hwaddr addr, |
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uint64_t data, unsigned size)
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{
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assigned_dev_ioport_rw(opaque, addr, size, &data); |
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} |
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|
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static uint64_t assigned_dev_ioport_read(void *opaque, |
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hwaddr addr, unsigned size)
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{
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return assigned_dev_ioport_rw(opaque, addr, size, NULL); |
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} |
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|
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static uint32_t slow_bar_readb(void *opaque, hwaddr addr) |
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{
|
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AssignedDevRegion *d = opaque; |
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uint8_t *in = d->u.r_virtbase + addr; |
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uint32_t r; |
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|
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r = *in; |
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DEBUG("slow_bar_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r); |
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|
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return r;
|
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} |
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|
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static uint32_t slow_bar_readw(void *opaque, hwaddr addr) |
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{
|
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AssignedDevRegion *d = opaque; |
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uint16_t *in = (uint16_t *)(d->u.r_virtbase + addr); |
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uint32_t r; |
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|
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r = *in; |
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DEBUG("slow_bar_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r); |
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|
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return r;
|
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} |
| 244 |
|
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static uint32_t slow_bar_readl(void *opaque, hwaddr addr) |
| 246 |
{
|
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AssignedDevRegion *d = opaque; |
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uint32_t *in = (uint32_t *)(d->u.r_virtbase + addr); |
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uint32_t r; |
| 250 |
|
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r = *in; |
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DEBUG("slow_bar_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r); |
| 253 |
|
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return r;
|
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} |
| 256 |
|
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static void slow_bar_writeb(void *opaque, hwaddr addr, uint32_t val) |
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{
|
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AssignedDevRegion *d = opaque; |
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uint8_t *out = d->u.r_virtbase + addr; |
| 261 |
|
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DEBUG("slow_bar_writeb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr, val); |
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*out = val; |
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} |
| 265 |
|
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static void slow_bar_writew(void *opaque, hwaddr addr, uint32_t val) |
| 267 |
{
|
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AssignedDevRegion *d = opaque; |
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uint16_t *out = (uint16_t *)(d->u.r_virtbase + addr); |
| 270 |
|
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DEBUG("slow_bar_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr, val); |
| 272 |
*out = val; |
| 273 |
} |
| 274 |
|
| 275 |
static void slow_bar_writel(void *opaque, hwaddr addr, uint32_t val) |
| 276 |
{
|
| 277 |
AssignedDevRegion *d = opaque; |
| 278 |
uint32_t *out = (uint32_t *)(d->u.r_virtbase + addr); |
| 279 |
|
| 280 |
DEBUG("slow_bar_writel addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, val); |
| 281 |
*out = val; |
| 282 |
} |
| 283 |
|
| 284 |
static const MemoryRegionOps slow_bar_ops = { |
| 285 |
.old_mmio = {
|
| 286 |
.read = { slow_bar_readb, slow_bar_readw, slow_bar_readl, },
|
| 287 |
.write = { slow_bar_writeb, slow_bar_writew, slow_bar_writel, },
|
| 288 |
}, |
| 289 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 290 |
}; |
| 291 |
|
| 292 |
static void assigned_dev_iomem_setup(PCIDevice *pci_dev, int region_num, |
| 293 |
pcibus_t e_size) |
| 294 |
{
|
| 295 |
AssignedDevice *r_dev = DO_UPCAST(AssignedDevice, dev, pci_dev); |
| 296 |
AssignedDevRegion *region = &r_dev->v_addrs[region_num]; |
| 297 |
PCIRegion *real_region = &r_dev->real_device.regions[region_num]; |
| 298 |
|
| 299 |
if (e_size > 0) { |
| 300 |
memory_region_init(®ion->container, "assigned-dev-container",
|
| 301 |
e_size); |
| 302 |
memory_region_add_subregion(®ion->container, 0, ®ion->real_iomem);
|
| 303 |
|
| 304 |
/* deal with MSI-X MMIO page */
|
| 305 |
if (real_region->base_addr <= r_dev->msix_table_addr &&
|
| 306 |
real_region->base_addr + real_region->size > |
| 307 |
r_dev->msix_table_addr) {
|
| 308 |
uint64_t offset = r_dev->msix_table_addr - real_region->base_addr; |
| 309 |
|
| 310 |
memory_region_add_subregion_overlap(®ion->container, |
| 311 |
offset, |
| 312 |
&r_dev->mmio, |
| 313 |
1);
|
| 314 |
} |
| 315 |
} |
| 316 |
} |
| 317 |
|
| 318 |
static const MemoryRegionOps assigned_dev_ioport_ops = { |
| 319 |
.read = assigned_dev_ioport_read, |
| 320 |
.write = assigned_dev_ioport_write, |
| 321 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 322 |
}; |
| 323 |
|
| 324 |
static void assigned_dev_ioport_setup(PCIDevice *pci_dev, int region_num, |
| 325 |
pcibus_t size) |
| 326 |
{
|
| 327 |
AssignedDevice *r_dev = DO_UPCAST(AssignedDevice, dev, pci_dev); |
| 328 |
AssignedDevRegion *region = &r_dev->v_addrs[region_num]; |
| 329 |
|
| 330 |
region->e_size = size; |
| 331 |
memory_region_init(®ion->container, "assigned-dev-container", size);
|
| 332 |
memory_region_init_io(®ion->real_iomem, &assigned_dev_ioport_ops, |
| 333 |
r_dev->v_addrs + region_num, |
| 334 |
"assigned-dev-iomem", size);
|
| 335 |
memory_region_add_subregion(®ion->container, 0, ®ion->real_iomem);
|
| 336 |
} |
| 337 |
|
| 338 |
static uint32_t assigned_dev_pci_read(PCIDevice *d, int pos, int len) |
| 339 |
{
|
| 340 |
AssignedDevice *pci_dev = DO_UPCAST(AssignedDevice, dev, d); |
| 341 |
uint32_t val; |
| 342 |
ssize_t ret; |
| 343 |
int fd = pci_dev->real_device.config_fd;
|
| 344 |
|
| 345 |
again:
|
| 346 |
ret = pread(fd, &val, len, pos); |
| 347 |
if (ret != len) {
|
| 348 |
if ((ret < 0) && (errno == EINTR || errno == EAGAIN)) { |
| 349 |
goto again;
|
| 350 |
} |
| 351 |
|
| 352 |
hw_error("pci read failed, ret = %zd errno = %d\n", ret, errno);
|
| 353 |
} |
| 354 |
|
| 355 |
return val;
|
| 356 |
} |
| 357 |
|
| 358 |
static uint8_t assigned_dev_pci_read_byte(PCIDevice *d, int pos) |
| 359 |
{
|
| 360 |
return (uint8_t)assigned_dev_pci_read(d, pos, 1); |
| 361 |
} |
| 362 |
|
| 363 |
static void assigned_dev_pci_write(PCIDevice *d, int pos, uint32_t val, int len) |
| 364 |
{
|
| 365 |
AssignedDevice *pci_dev = DO_UPCAST(AssignedDevice, dev, d); |
| 366 |
ssize_t ret; |
| 367 |
int fd = pci_dev->real_device.config_fd;
|
| 368 |
|
| 369 |
again:
|
| 370 |
ret = pwrite(fd, &val, len, pos); |
| 371 |
if (ret != len) {
|
| 372 |
if ((ret < 0) && (errno == EINTR || errno == EAGAIN)) { |
| 373 |
goto again;
|
| 374 |
} |
| 375 |
|
| 376 |
hw_error("pci write failed, ret = %zd errno = %d\n", ret, errno);
|
| 377 |
} |
| 378 |
} |
| 379 |
|
| 380 |
static void assigned_dev_emulate_config_read(AssignedDevice *dev, |
| 381 |
uint32_t offset, uint32_t len) |
| 382 |
{
|
| 383 |
memset(dev->emulate_config_read + offset, 0xff, len);
|
| 384 |
} |
| 385 |
|
| 386 |
static void assigned_dev_direct_config_read(AssignedDevice *dev, |
| 387 |
uint32_t offset, uint32_t len) |
| 388 |
{
|
| 389 |
memset(dev->emulate_config_read + offset, 0, len);
|
| 390 |
} |
| 391 |
|
| 392 |
static void assigned_dev_direct_config_write(AssignedDevice *dev, |
| 393 |
uint32_t offset, uint32_t len) |
| 394 |
{
|
| 395 |
memset(dev->emulate_config_write + offset, 0, len);
|
| 396 |
} |
| 397 |
|
| 398 |
static uint8_t pci_find_cap_offset(PCIDevice *d, uint8_t cap, uint8_t start)
|
| 399 |
{
|
| 400 |
int id;
|
| 401 |
int max_cap = 48; |
| 402 |
int pos = start ? start : PCI_CAPABILITY_LIST;
|
| 403 |
int status;
|
| 404 |
|
| 405 |
status = assigned_dev_pci_read_byte(d, PCI_STATUS); |
| 406 |
if ((status & PCI_STATUS_CAP_LIST) == 0) { |
| 407 |
return 0; |
| 408 |
} |
| 409 |
|
| 410 |
while (max_cap--) {
|
| 411 |
pos = assigned_dev_pci_read_byte(d, pos); |
| 412 |
if (pos < 0x40) { |
| 413 |
break;
|
| 414 |
} |
| 415 |
|
| 416 |
pos &= ~3;
|
| 417 |
id = assigned_dev_pci_read_byte(d, pos + PCI_CAP_LIST_ID); |
| 418 |
|
| 419 |
if (id == 0xff) { |
| 420 |
break;
|
| 421 |
} |
| 422 |
if (id == cap) {
|
| 423 |
return pos;
|
| 424 |
} |
| 425 |
|
| 426 |
pos += PCI_CAP_LIST_NEXT; |
| 427 |
} |
| 428 |
return 0; |
| 429 |
} |
| 430 |
|
| 431 |
static int assigned_dev_register_regions(PCIRegion *io_regions, |
| 432 |
unsigned long regions_num, |
| 433 |
AssignedDevice *pci_dev) |
| 434 |
{
|
| 435 |
uint32_t i; |
| 436 |
PCIRegion *cur_region = io_regions; |
| 437 |
|
| 438 |
for (i = 0; i < regions_num; i++, cur_region++) { |
| 439 |
if (!cur_region->valid) {
|
| 440 |
continue;
|
| 441 |
} |
| 442 |
|
| 443 |
/* handle memory io regions */
|
| 444 |
if (cur_region->type & IORESOURCE_MEM) {
|
| 445 |
int t = cur_region->type & IORESOURCE_PREFETCH
|
| 446 |
? PCI_BASE_ADDRESS_MEM_PREFETCH |
| 447 |
: PCI_BASE_ADDRESS_SPACE_MEMORY; |
| 448 |
|
| 449 |
/* map physical memory */
|
| 450 |
pci_dev->v_addrs[i].u.r_virtbase = mmap(NULL, cur_region->size,
|
| 451 |
PROT_WRITE | PROT_READ, |
| 452 |
MAP_SHARED, |
| 453 |
cur_region->resource_fd, |
| 454 |
(off_t)0);
|
| 455 |
|
| 456 |
if (pci_dev->v_addrs[i].u.r_virtbase == MAP_FAILED) {
|
| 457 |
pci_dev->v_addrs[i].u.r_virtbase = NULL;
|
| 458 |
error_report("%s: Error: Couldn't mmap 0x%" PRIx64 "!", |
| 459 |
__func__, cur_region->base_addr); |
| 460 |
return -1; |
| 461 |
} |
| 462 |
|
| 463 |
pci_dev->v_addrs[i].r_size = cur_region->size; |
| 464 |
pci_dev->v_addrs[i].e_size = 0;
|
| 465 |
|
| 466 |
/* add offset */
|
| 467 |
pci_dev->v_addrs[i].u.r_virtbase += |
| 468 |
(cur_region->base_addr & 0xFFF);
|
| 469 |
|
| 470 |
if (cur_region->size & 0xFFF) { |
| 471 |
error_report("PCI region %d at address 0x%" PRIx64 " has " |
| 472 |
"size 0x%" PRIx64 ", which is not a multiple of " |
| 473 |
"4K. You might experience some performance hit "
|
| 474 |
"due to that.",
|
| 475 |
i, cur_region->base_addr, cur_region->size); |
| 476 |
memory_region_init_io(&pci_dev->v_addrs[i].real_iomem, |
| 477 |
&slow_bar_ops, &pci_dev->v_addrs[i], |
| 478 |
"assigned-dev-slow-bar",
|
| 479 |
cur_region->size); |
| 480 |
} else {
|
| 481 |
void *virtbase = pci_dev->v_addrs[i].u.r_virtbase;
|
| 482 |
char name[32]; |
| 483 |
snprintf(name, sizeof(name), "%s.bar%d", |
| 484 |
object_get_typename(OBJECT(pci_dev)), i); |
| 485 |
memory_region_init_ram_ptr(&pci_dev->v_addrs[i].real_iomem, |
| 486 |
name, cur_region->size, |
| 487 |
virtbase); |
| 488 |
vmstate_register_ram(&pci_dev->v_addrs[i].real_iomem, |
| 489 |
&pci_dev->dev.qdev); |
| 490 |
} |
| 491 |
|
| 492 |
assigned_dev_iomem_setup(&pci_dev->dev, i, cur_region->size); |
| 493 |
pci_register_bar((PCIDevice *) pci_dev, i, t, |
| 494 |
&pci_dev->v_addrs[i].container); |
| 495 |
continue;
|
| 496 |
} else {
|
| 497 |
/* handle port io regions */
|
| 498 |
uint32_t val; |
| 499 |
int ret;
|
| 500 |
|
| 501 |
/* Test kernel support for ioport resource read/write. Old
|
| 502 |
* kernels return EIO. New kernels only allow 1/2/4 byte reads
|
| 503 |
* so should return EINVAL for a 3 byte read */
|
| 504 |
ret = pread(pci_dev->v_addrs[i].region->resource_fd, &val, 3, 0); |
| 505 |
if (ret >= 0) { |
| 506 |
error_report("Unexpected return from I/O port read: %d", ret);
|
| 507 |
abort(); |
| 508 |
} else if (errno != EINVAL) { |
| 509 |
error_report("Kernel doesn't support ioport resource "
|
| 510 |
"access, hiding this region.");
|
| 511 |
close(pci_dev->v_addrs[i].region->resource_fd); |
| 512 |
cur_region->valid = 0;
|
| 513 |
continue;
|
| 514 |
} |
| 515 |
|
| 516 |
pci_dev->v_addrs[i].u.r_baseport = cur_region->base_addr; |
| 517 |
pci_dev->v_addrs[i].r_size = cur_region->size; |
| 518 |
pci_dev->v_addrs[i].e_size = 0;
|
| 519 |
|
| 520 |
assigned_dev_ioport_setup(&pci_dev->dev, i, cur_region->size); |
| 521 |
pci_register_bar((PCIDevice *) pci_dev, i, |
| 522 |
PCI_BASE_ADDRESS_SPACE_IO, |
| 523 |
&pci_dev->v_addrs[i].container); |
| 524 |
} |
| 525 |
} |
| 526 |
|
| 527 |
/* success */
|
| 528 |
return 0; |
| 529 |
} |
| 530 |
|
| 531 |
static int get_real_id(const char *devpath, const char *idname, uint16_t *val) |
| 532 |
{
|
| 533 |
FILE *f; |
| 534 |
char name[128]; |
| 535 |
long id;
|
| 536 |
|
| 537 |
snprintf(name, sizeof(name), "%s%s", devpath, idname); |
| 538 |
f = fopen(name, "r");
|
| 539 |
if (f == NULL) { |
| 540 |
error_report("%s: %s: %m", __func__, name);
|
| 541 |
return -1; |
| 542 |
} |
| 543 |
if (fscanf(f, "%li\n", &id) == 1) { |
| 544 |
*val = id; |
| 545 |
} else {
|
| 546 |
return -1; |
| 547 |
} |
| 548 |
fclose(f); |
| 549 |
|
| 550 |
return 0; |
| 551 |
} |
| 552 |
|
| 553 |
static int get_real_vendor_id(const char *devpath, uint16_t *val) |
| 554 |
{
|
| 555 |
return get_real_id(devpath, "vendor", val); |
| 556 |
} |
| 557 |
|
| 558 |
static int get_real_device_id(const char *devpath, uint16_t *val) |
| 559 |
{
|
| 560 |
return get_real_id(devpath, "device", val); |
| 561 |
} |
| 562 |
|
| 563 |
static int get_real_device(AssignedDevice *pci_dev, uint16_t r_seg, |
| 564 |
uint8_t r_bus, uint8_t r_dev, uint8_t r_func) |
| 565 |
{
|
| 566 |
char dir[128], name[128]; |
| 567 |
int fd, r = 0, v; |
| 568 |
FILE *f; |
| 569 |
uint64_t start, end, size, flags; |
| 570 |
uint16_t id; |
| 571 |
PCIRegion *rp; |
| 572 |
PCIDevRegions *dev = &pci_dev->real_device; |
| 573 |
|
| 574 |
dev->region_number = 0;
|
| 575 |
|
| 576 |
snprintf(dir, sizeof(dir), "/sys/bus/pci/devices/%04x:%02x:%02x.%x/", |
| 577 |
r_seg, r_bus, r_dev, r_func); |
| 578 |
|
| 579 |
snprintf(name, sizeof(name), "%sconfig", dir); |
| 580 |
|
| 581 |
if (pci_dev->configfd_name && *pci_dev->configfd_name) {
|
| 582 |
dev->config_fd = monitor_handle_fd_param(cur_mon, pci_dev->configfd_name); |
| 583 |
if (dev->config_fd < 0) { |
| 584 |
return 1; |
| 585 |
} |
| 586 |
} else {
|
| 587 |
dev->config_fd = open(name, O_RDWR); |
| 588 |
|
| 589 |
if (dev->config_fd == -1) { |
| 590 |
error_report("%s: %s: %m", __func__, name);
|
| 591 |
return 1; |
| 592 |
} |
| 593 |
} |
| 594 |
again:
|
| 595 |
r = read(dev->config_fd, pci_dev->dev.config, |
| 596 |
pci_config_size(&pci_dev->dev)); |
| 597 |
if (r < 0) { |
| 598 |
if (errno == EINTR || errno == EAGAIN) {
|
| 599 |
goto again;
|
| 600 |
} |
| 601 |
error_report("%s: read failed, errno = %d", __func__, errno);
|
| 602 |
} |
| 603 |
|
| 604 |
/* Restore or clear multifunction, this is always controlled by qemu */
|
| 605 |
if (pci_dev->dev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
|
| 606 |
pci_dev->dev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; |
| 607 |
} else {
|
| 608 |
pci_dev->dev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
| 609 |
} |
| 610 |
|
| 611 |
/* Clear host resource mapping info. If we choose not to register a
|
| 612 |
* BAR, such as might be the case with the option ROM, we can get
|
| 613 |
* confusing, unwritable, residual addresses from the host here. */
|
| 614 |
memset(&pci_dev->dev.config[PCI_BASE_ADDRESS_0], 0, 24); |
| 615 |
memset(&pci_dev->dev.config[PCI_ROM_ADDRESS], 0, 4); |
| 616 |
|
| 617 |
snprintf(name, sizeof(name), "%sresource", dir); |
| 618 |
|
| 619 |
f = fopen(name, "r");
|
| 620 |
if (f == NULL) { |
| 621 |
error_report("%s: %s: %m", __func__, name);
|
| 622 |
return 1; |
| 623 |
} |
| 624 |
|
| 625 |
for (r = 0; r < PCI_ROM_SLOT; r++) { |
| 626 |
if (fscanf(f, "%" SCNi64 " %" SCNi64 " %" SCNi64 "\n", |
| 627 |
&start, &end, &flags) != 3) {
|
| 628 |
break;
|
| 629 |
} |
| 630 |
|
| 631 |
rp = dev->regions + r; |
| 632 |
rp->valid = 0;
|
| 633 |
rp->resource_fd = -1;
|
| 634 |
size = end - start + 1;
|
| 635 |
flags &= IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 636 |
if (size == 0 || (flags & ~IORESOURCE_PREFETCH) == 0) { |
| 637 |
continue;
|
| 638 |
} |
| 639 |
if (flags & IORESOURCE_MEM) {
|
| 640 |
flags &= ~IORESOURCE_IO; |
| 641 |
} else {
|
| 642 |
flags &= ~IORESOURCE_PREFETCH; |
| 643 |
} |
| 644 |
snprintf(name, sizeof(name), "%sresource%d", dir, r); |
| 645 |
fd = open(name, O_RDWR); |
| 646 |
if (fd == -1) { |
| 647 |
continue;
|
| 648 |
} |
| 649 |
rp->resource_fd = fd; |
| 650 |
|
| 651 |
rp->type = flags; |
| 652 |
rp->valid = 1;
|
| 653 |
rp->base_addr = start; |
| 654 |
rp->size = size; |
| 655 |
pci_dev->v_addrs[r].region = rp; |
| 656 |
DEBUG("region %d size %" PRIu64 " start 0x%" PRIx64 |
| 657 |
" type %d resource_fd %d\n",
|
| 658 |
r, rp->size, start, rp->type, rp->resource_fd); |
| 659 |
} |
| 660 |
|
| 661 |
fclose(f); |
| 662 |
|
| 663 |
/* read and fill vendor ID */
|
| 664 |
v = get_real_vendor_id(dir, &id); |
| 665 |
if (v) {
|
| 666 |
return 1; |
| 667 |
} |
| 668 |
pci_dev->dev.config[0] = id & 0xff; |
| 669 |
pci_dev->dev.config[1] = (id & 0xff00) >> 8; |
| 670 |
|
| 671 |
/* read and fill device ID */
|
| 672 |
v = get_real_device_id(dir, &id); |
| 673 |
if (v) {
|
| 674 |
return 1; |
| 675 |
} |
| 676 |
pci_dev->dev.config[2] = id & 0xff; |
| 677 |
pci_dev->dev.config[3] = (id & 0xff00) >> 8; |
| 678 |
|
| 679 |
pci_word_test_and_clear_mask(pci_dev->emulate_config_write + PCI_COMMAND, |
| 680 |
PCI_COMMAND_MASTER | PCI_COMMAND_INTX_DISABLE); |
| 681 |
|
| 682 |
dev->region_number = r; |
| 683 |
return 0; |
| 684 |
} |
| 685 |
|
| 686 |
static void free_msi_virqs(AssignedDevice *dev) |
| 687 |
{
|
| 688 |
int i;
|
| 689 |
|
| 690 |
for (i = 0; i < dev->msi_virq_nr; i++) { |
| 691 |
if (dev->msi_virq[i] >= 0) { |
| 692 |
kvm_irqchip_release_virq(kvm_state, dev->msi_virq[i]); |
| 693 |
dev->msi_virq[i] = -1;
|
| 694 |
} |
| 695 |
} |
| 696 |
g_free(dev->msi_virq); |
| 697 |
dev->msi_virq = NULL;
|
| 698 |
dev->msi_virq_nr = 0;
|
| 699 |
} |
| 700 |
|
| 701 |
static void free_assigned_device(AssignedDevice *dev) |
| 702 |
{
|
| 703 |
int i;
|
| 704 |
|
| 705 |
if (dev->cap.available & ASSIGNED_DEVICE_CAP_MSIX) {
|
| 706 |
assigned_dev_unregister_msix_mmio(dev); |
| 707 |
} |
| 708 |
for (i = 0; i < dev->real_device.region_number; i++) { |
| 709 |
PCIRegion *pci_region = &dev->real_device.regions[i]; |
| 710 |
AssignedDevRegion *region = &dev->v_addrs[i]; |
| 711 |
|
| 712 |
if (!pci_region->valid) {
|
| 713 |
continue;
|
| 714 |
} |
| 715 |
if (pci_region->type & IORESOURCE_IO) {
|
| 716 |
if (region->u.r_baseport) {
|
| 717 |
memory_region_del_subregion(®ion->container, |
| 718 |
®ion->real_iomem); |
| 719 |
memory_region_destroy(®ion->real_iomem); |
| 720 |
memory_region_destroy(®ion->container); |
| 721 |
} |
| 722 |
} else if (pci_region->type & IORESOURCE_MEM) { |
| 723 |
if (region->u.r_virtbase) {
|
| 724 |
memory_region_del_subregion(®ion->container, |
| 725 |
®ion->real_iomem); |
| 726 |
|
| 727 |
/* Remove MSI-X table subregion */
|
| 728 |
if (pci_region->base_addr <= dev->msix_table_addr &&
|
| 729 |
pci_region->base_addr + pci_region->size > |
| 730 |
dev->msix_table_addr) {
|
| 731 |
memory_region_del_subregion(®ion->container, |
| 732 |
&dev->mmio); |
| 733 |
} |
| 734 |
|
| 735 |
memory_region_destroy(®ion->real_iomem); |
| 736 |
memory_region_destroy(®ion->container); |
| 737 |
if (munmap(region->u.r_virtbase,
|
| 738 |
(pci_region->size + 0xFFF) & 0xFFFFF000)) { |
| 739 |
error_report("Failed to unmap assigned device region: %s",
|
| 740 |
strerror(errno)); |
| 741 |
} |
| 742 |
} |
| 743 |
} |
| 744 |
if (pci_region->resource_fd >= 0) { |
| 745 |
close(pci_region->resource_fd); |
| 746 |
} |
| 747 |
} |
| 748 |
|
| 749 |
if (dev->real_device.config_fd >= 0) { |
| 750 |
close(dev->real_device.config_fd); |
| 751 |
} |
| 752 |
|
| 753 |
free_msi_virqs(dev); |
| 754 |
} |
| 755 |
|
| 756 |
static void assign_failed_examine(AssignedDevice *dev) |
| 757 |
{
|
| 758 |
char name[PATH_MAX], dir[PATH_MAX], driver[PATH_MAX] = {}, *ns;
|
| 759 |
uint16_t vendor_id, device_id; |
| 760 |
int r;
|
| 761 |
|
| 762 |
snprintf(dir, sizeof(dir), "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/", |
| 763 |
dev->host.domain, dev->host.bus, dev->host.slot, |
| 764 |
dev->host.function); |
| 765 |
|
| 766 |
snprintf(name, sizeof(name), "%sdriver", dir); |
| 767 |
|
| 768 |
r = readlink(name, driver, sizeof(driver));
|
| 769 |
if ((r <= 0) || r >= sizeof(driver)) { |
| 770 |
goto fail;
|
| 771 |
} |
| 772 |
|
| 773 |
ns = strrchr(driver, '/');
|
| 774 |
if (!ns) {
|
| 775 |
goto fail;
|
| 776 |
} |
| 777 |
|
| 778 |
ns++; |
| 779 |
|
| 780 |
if (get_real_vendor_id(dir, &vendor_id) ||
|
| 781 |
get_real_device_id(dir, &device_id)) {
|
| 782 |
goto fail;
|
| 783 |
} |
| 784 |
|
| 785 |
error_report("*** The driver '%s' is occupying your device "
|
| 786 |
"%04x:%02x:%02x.%x.",
|
| 787 |
ns, dev->host.domain, dev->host.bus, dev->host.slot, |
| 788 |
dev->host.function); |
| 789 |
error_report("***");
|
| 790 |
error_report("*** You can try the following commands to free it:");
|
| 791 |
error_report("***");
|
| 792 |
error_report("*** $ echo \"%04x %04x\" > /sys/bus/pci/drivers/pci-stub/"
|
| 793 |
"new_id", vendor_id, device_id);
|
| 794 |
error_report("*** $ echo \"%04x:%02x:%02x.%x\" > /sys/bus/pci/drivers/"
|
| 795 |
"%s/unbind",
|
| 796 |
dev->host.domain, dev->host.bus, dev->host.slot, |
| 797 |
dev->host.function, ns); |
| 798 |
error_report("*** $ echo \"%04x:%02x:%02x.%x\" > /sys/bus/pci/drivers/"
|
| 799 |
"pci-stub/bind",
|
| 800 |
dev->host.domain, dev->host.bus, dev->host.slot, |
| 801 |
dev->host.function); |
| 802 |
error_report("*** $ echo \"%04x %04x\" > /sys/bus/pci/drivers/pci-stub"
|
| 803 |
"/remove_id", vendor_id, device_id);
|
| 804 |
error_report("***");
|
| 805 |
|
| 806 |
return;
|
| 807 |
|
| 808 |
fail:
|
| 809 |
error_report("Couldn't find out why.");
|
| 810 |
} |
| 811 |
|
| 812 |
static int assign_device(AssignedDevice *dev) |
| 813 |
{
|
| 814 |
uint32_t flags = KVM_DEV_ASSIGN_ENABLE_IOMMU; |
| 815 |
int r;
|
| 816 |
|
| 817 |
/* Only pass non-zero PCI segment to capable module */
|
| 818 |
if (!kvm_check_extension(kvm_state, KVM_CAP_PCI_SEGMENT) &&
|
| 819 |
dev->host.domain) {
|
| 820 |
error_report("Can't assign device inside non-zero PCI segment "
|
| 821 |
"as this KVM module doesn't support it.");
|
| 822 |
return -ENODEV;
|
| 823 |
} |
| 824 |
|
| 825 |
if (!kvm_check_extension(kvm_state, KVM_CAP_IOMMU)) {
|
| 826 |
error_report("No IOMMU found. Unable to assign device \"%s\"",
|
| 827 |
dev->dev.qdev.id); |
| 828 |
return -ENODEV;
|
| 829 |
} |
| 830 |
|
| 831 |
if (dev->features & ASSIGNED_DEVICE_SHARE_INTX_MASK &&
|
| 832 |
kvm_has_intx_set_mask()) {
|
| 833 |
flags |= KVM_DEV_ASSIGN_PCI_2_3; |
| 834 |
} |
| 835 |
|
| 836 |
r = kvm_device_pci_assign(kvm_state, &dev->host, flags, &dev->dev_id); |
| 837 |
if (r < 0) { |
| 838 |
error_report("Failed to assign device \"%s\" : %s",
|
| 839 |
dev->dev.qdev.id, strerror(-r)); |
| 840 |
|
| 841 |
switch (r) {
|
| 842 |
case -EBUSY:
|
| 843 |
assign_failed_examine(dev); |
| 844 |
break;
|
| 845 |
default:
|
| 846 |
break;
|
| 847 |
} |
| 848 |
} |
| 849 |
return r;
|
| 850 |
} |
| 851 |
|
| 852 |
static bool check_irqchip_in_kernel(void) |
| 853 |
{
|
| 854 |
if (kvm_irqchip_in_kernel()) {
|
| 855 |
return true; |
| 856 |
} |
| 857 |
error_report("pci-assign: error: requires KVM with in-kernel irqchip "
|
| 858 |
"enabled");
|
| 859 |
return false; |
| 860 |
} |
| 861 |
|
| 862 |
static int assign_intx(AssignedDevice *dev) |
| 863 |
{
|
| 864 |
AssignedIRQType new_type; |
| 865 |
PCIINTxRoute intx_route; |
| 866 |
bool intx_host_msi;
|
| 867 |
int r;
|
| 868 |
|
| 869 |
/* Interrupt PIN 0 means don't use INTx */
|
| 870 |
if (assigned_dev_pci_read_byte(&dev->dev, PCI_INTERRUPT_PIN) == 0) { |
| 871 |
pci_device_set_intx_routing_notifier(&dev->dev, NULL);
|
| 872 |
return 0; |
| 873 |
} |
| 874 |
|
| 875 |
if (!check_irqchip_in_kernel()) {
|
| 876 |
return -ENOTSUP;
|
| 877 |
} |
| 878 |
|
| 879 |
pci_device_set_intx_routing_notifier(&dev->dev, |
| 880 |
assigned_dev_update_irq_routing); |
| 881 |
|
| 882 |
intx_route = pci_device_route_intx_to_irq(&dev->dev, dev->intpin); |
| 883 |
assert(intx_route.mode != PCI_INTX_INVERTED); |
| 884 |
|
| 885 |
if (dev->intx_route.mode == intx_route.mode &&
|
| 886 |
dev->intx_route.irq == intx_route.irq) {
|
| 887 |
return 0; |
| 888 |
} |
| 889 |
|
| 890 |
switch (dev->assigned_irq_type) {
|
| 891 |
case ASSIGNED_IRQ_INTX_HOST_INTX:
|
| 892 |
case ASSIGNED_IRQ_INTX_HOST_MSI:
|
| 893 |
intx_host_msi = dev->assigned_irq_type == ASSIGNED_IRQ_INTX_HOST_MSI; |
| 894 |
r = kvm_device_intx_deassign(kvm_state, dev->dev_id, intx_host_msi); |
| 895 |
break;
|
| 896 |
case ASSIGNED_IRQ_MSI:
|
| 897 |
r = kvm_device_msi_deassign(kvm_state, dev->dev_id); |
| 898 |
break;
|
| 899 |
case ASSIGNED_IRQ_MSIX:
|
| 900 |
r = kvm_device_msix_deassign(kvm_state, dev->dev_id); |
| 901 |
break;
|
| 902 |
default:
|
| 903 |
r = 0;
|
| 904 |
break;
|
| 905 |
} |
| 906 |
if (r) {
|
| 907 |
perror("assign_intx: deassignment of previous interrupt failed");
|
| 908 |
} |
| 909 |
dev->assigned_irq_type = ASSIGNED_IRQ_NONE; |
| 910 |
|
| 911 |
if (intx_route.mode == PCI_INTX_DISABLED) {
|
| 912 |
dev->intx_route = intx_route; |
| 913 |
return 0; |
| 914 |
} |
| 915 |
|
| 916 |
retry:
|
| 917 |
if (dev->features & ASSIGNED_DEVICE_PREFER_MSI_MASK &&
|
| 918 |
dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) {
|
| 919 |
intx_host_msi = true;
|
| 920 |
new_type = ASSIGNED_IRQ_INTX_HOST_MSI; |
| 921 |
} else {
|
| 922 |
intx_host_msi = false;
|
| 923 |
new_type = ASSIGNED_IRQ_INTX_HOST_INTX; |
| 924 |
} |
| 925 |
|
| 926 |
r = kvm_device_intx_assign(kvm_state, dev->dev_id, intx_host_msi, |
| 927 |
intx_route.irq); |
| 928 |
if (r < 0) { |
| 929 |
if (r == -EIO && !(dev->features & ASSIGNED_DEVICE_PREFER_MSI_MASK) &&
|
| 930 |
dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) {
|
| 931 |
/* Retry with host-side MSI. There might be an IRQ conflict and
|
| 932 |
* either the kernel or the device doesn't support sharing. */
|
| 933 |
error_report("Host-side INTx sharing not supported, "
|
| 934 |
"using MSI instead.\n"
|
| 935 |
"Some devices do not to work properly in this mode.");
|
| 936 |
dev->features |= ASSIGNED_DEVICE_PREFER_MSI_MASK; |
| 937 |
goto retry;
|
| 938 |
} |
| 939 |
error_report("Failed to assign irq for \"%s\": %s",
|
| 940 |
dev->dev.qdev.id, strerror(-r)); |
| 941 |
error_report("Perhaps you are assigning a device "
|
| 942 |
"that shares an IRQ with another device?");
|
| 943 |
return r;
|
| 944 |
} |
| 945 |
|
| 946 |
dev->intx_route = intx_route; |
| 947 |
dev->assigned_irq_type = new_type; |
| 948 |
return r;
|
| 949 |
} |
| 950 |
|
| 951 |
static void deassign_device(AssignedDevice *dev) |
| 952 |
{
|
| 953 |
int r;
|
| 954 |
|
| 955 |
r = kvm_device_pci_deassign(kvm_state, dev->dev_id); |
| 956 |
assert(r == 0);
|
| 957 |
} |
| 958 |
|
| 959 |
/* The pci config space got updated. Check if irq numbers have changed
|
| 960 |
* for our devices
|
| 961 |
*/
|
| 962 |
static void assigned_dev_update_irq_routing(PCIDevice *dev) |
| 963 |
{
|
| 964 |
AssignedDevice *assigned_dev = DO_UPCAST(AssignedDevice, dev, dev); |
| 965 |
Error *err = NULL;
|
| 966 |
int r;
|
| 967 |
|
| 968 |
r = assign_intx(assigned_dev); |
| 969 |
if (r < 0) { |
| 970 |
qdev_unplug(&dev->qdev, &err); |
| 971 |
assert(!err); |
| 972 |
} |
| 973 |
} |
| 974 |
|
| 975 |
static void assigned_dev_update_msi(PCIDevice *pci_dev) |
| 976 |
{
|
| 977 |
AssignedDevice *assigned_dev = DO_UPCAST(AssignedDevice, dev, pci_dev); |
| 978 |
uint8_t ctrl_byte = pci_get_byte(pci_dev->config + pci_dev->msi_cap + |
| 979 |
PCI_MSI_FLAGS); |
| 980 |
int r;
|
| 981 |
|
| 982 |
/* Some guests gratuitously disable MSI even if they're not using it,
|
| 983 |
* try to catch this by only deassigning irqs if the guest is using
|
| 984 |
* MSI or intends to start. */
|
| 985 |
if (assigned_dev->assigned_irq_type == ASSIGNED_IRQ_MSI ||
|
| 986 |
(ctrl_byte & PCI_MSI_FLAGS_ENABLE)) {
|
| 987 |
r = kvm_device_msi_deassign(kvm_state, assigned_dev->dev_id); |
| 988 |
/* -ENXIO means no assigned irq */
|
| 989 |
if (r && r != -ENXIO) {
|
| 990 |
perror("assigned_dev_update_msi: deassign irq");
|
| 991 |
} |
| 992 |
|
| 993 |
free_msi_virqs(assigned_dev); |
| 994 |
|
| 995 |
assigned_dev->assigned_irq_type = ASSIGNED_IRQ_NONE; |
| 996 |
pci_device_set_intx_routing_notifier(pci_dev, NULL);
|
| 997 |
} |
| 998 |
|
| 999 |
if (ctrl_byte & PCI_MSI_FLAGS_ENABLE) {
|
| 1000 |
uint8_t *pos = pci_dev->config + pci_dev->msi_cap; |
| 1001 |
MSIMessage msg; |
| 1002 |
int virq;
|
| 1003 |
|
| 1004 |
msg.address = pci_get_long(pos + PCI_MSI_ADDRESS_LO); |
| 1005 |
msg.data = pci_get_word(pos + PCI_MSI_DATA_32); |
| 1006 |
virq = kvm_irqchip_add_msi_route(kvm_state, msg); |
| 1007 |
if (virq < 0) { |
| 1008 |
perror("assigned_dev_update_msi: kvm_irqchip_add_msi_route");
|
| 1009 |
return;
|
| 1010 |
} |
| 1011 |
|
| 1012 |
assigned_dev->msi_virq = g_malloc(sizeof(*assigned_dev->msi_virq));
|
| 1013 |
assigned_dev->msi_virq_nr = 1;
|
| 1014 |
assigned_dev->msi_virq[0] = virq;
|
| 1015 |
if (kvm_device_msi_assign(kvm_state, assigned_dev->dev_id, virq) < 0) { |
| 1016 |
perror("assigned_dev_update_msi: kvm_device_msi_assign");
|
| 1017 |
} |
| 1018 |
|
| 1019 |
assigned_dev->intx_route.mode = PCI_INTX_DISABLED; |
| 1020 |
assigned_dev->intx_route.irq = -1;
|
| 1021 |
assigned_dev->assigned_irq_type = ASSIGNED_IRQ_MSI; |
| 1022 |
} else {
|
| 1023 |
assign_intx(assigned_dev); |
| 1024 |
} |
| 1025 |
} |
| 1026 |
|
| 1027 |
static bool assigned_dev_msix_masked(MSIXTableEntry *entry) |
| 1028 |
{
|
| 1029 |
return (entry->ctrl & cpu_to_le32(0x1)) != 0; |
| 1030 |
} |
| 1031 |
|
| 1032 |
static int assigned_dev_update_msix_mmio(PCIDevice *pci_dev) |
| 1033 |
{
|
| 1034 |
AssignedDevice *adev = DO_UPCAST(AssignedDevice, dev, pci_dev); |
| 1035 |
uint16_t entries_nr = 0;
|
| 1036 |
int i, r = 0; |
| 1037 |
MSIXTableEntry *entry = adev->msix_table; |
| 1038 |
MSIMessage msg; |
| 1039 |
|
| 1040 |
/* Get the usable entry number for allocating */
|
| 1041 |
for (i = 0; i < adev->msix_max; i++, entry++) { |
| 1042 |
if (assigned_dev_msix_masked(entry)) {
|
| 1043 |
continue;
|
| 1044 |
} |
| 1045 |
entries_nr++; |
| 1046 |
} |
| 1047 |
|
| 1048 |
DEBUG("MSI-X entries: %d\n", entries_nr);
|
| 1049 |
|
| 1050 |
/* It's valid to enable MSI-X with all entries masked */
|
| 1051 |
if (!entries_nr) {
|
| 1052 |
return 0; |
| 1053 |
} |
| 1054 |
|
| 1055 |
r = kvm_device_msix_init_vectors(kvm_state, adev->dev_id, entries_nr); |
| 1056 |
if (r != 0) { |
| 1057 |
error_report("fail to set MSI-X entry number for MSIX! %s",
|
| 1058 |
strerror(-r)); |
| 1059 |
return r;
|
| 1060 |
} |
| 1061 |
|
| 1062 |
free_msi_virqs(adev); |
| 1063 |
|
| 1064 |
adev->msi_virq_nr = adev->msix_max; |
| 1065 |
adev->msi_virq = g_malloc(adev->msix_max * sizeof(*adev->msi_virq));
|
| 1066 |
|
| 1067 |
entry = adev->msix_table; |
| 1068 |
for (i = 0; i < adev->msix_max; i++, entry++) { |
| 1069 |
adev->msi_virq[i] = -1;
|
| 1070 |
|
| 1071 |
if (assigned_dev_msix_masked(entry)) {
|
| 1072 |
continue;
|
| 1073 |
} |
| 1074 |
|
| 1075 |
msg.address = entry->addr_lo | ((uint64_t)entry->addr_hi << 32);
|
| 1076 |
msg.data = entry->data; |
| 1077 |
r = kvm_irqchip_add_msi_route(kvm_state, msg); |
| 1078 |
if (r < 0) { |
| 1079 |
return r;
|
| 1080 |
} |
| 1081 |
adev->msi_virq[i] = r; |
| 1082 |
|
| 1083 |
DEBUG("MSI-X vector %d, gsi %d, addr %08x_%08x, data %08x\n", i,
|
| 1084 |
r, entry->addr_hi, entry->addr_lo, entry->data); |
| 1085 |
|
| 1086 |
r = kvm_device_msix_set_vector(kvm_state, adev->dev_id, i, |
| 1087 |
adev->msi_virq[i]); |
| 1088 |
if (r) {
|
| 1089 |
error_report("fail to set MSI-X entry! %s", strerror(-r));
|
| 1090 |
break;
|
| 1091 |
} |
| 1092 |
} |
| 1093 |
|
| 1094 |
return r;
|
| 1095 |
} |
| 1096 |
|
| 1097 |
static void assigned_dev_update_msix(PCIDevice *pci_dev) |
| 1098 |
{
|
| 1099 |
AssignedDevice *assigned_dev = DO_UPCAST(AssignedDevice, dev, pci_dev); |
| 1100 |
uint16_t ctrl_word = pci_get_word(pci_dev->config + pci_dev->msix_cap + |
| 1101 |
PCI_MSIX_FLAGS); |
| 1102 |
int r;
|
| 1103 |
|
| 1104 |
/* Some guests gratuitously disable MSIX even if they're not using it,
|
| 1105 |
* try to catch this by only deassigning irqs if the guest is using
|
| 1106 |
* MSIX or intends to start. */
|
| 1107 |
if ((assigned_dev->assigned_irq_type == ASSIGNED_IRQ_MSIX) ||
|
| 1108 |
(ctrl_word & PCI_MSIX_FLAGS_ENABLE)) {
|
| 1109 |
r = kvm_device_msix_deassign(kvm_state, assigned_dev->dev_id); |
| 1110 |
/* -ENXIO means no assigned irq */
|
| 1111 |
if (r && r != -ENXIO) {
|
| 1112 |
perror("assigned_dev_update_msix: deassign irq");
|
| 1113 |
} |
| 1114 |
|
| 1115 |
free_msi_virqs(assigned_dev); |
| 1116 |
|
| 1117 |
assigned_dev->assigned_irq_type = ASSIGNED_IRQ_NONE; |
| 1118 |
pci_device_set_intx_routing_notifier(pci_dev, NULL);
|
| 1119 |
} |
| 1120 |
|
| 1121 |
if (ctrl_word & PCI_MSIX_FLAGS_ENABLE) {
|
| 1122 |
if (assigned_dev_update_msix_mmio(pci_dev) < 0) { |
| 1123 |
perror("assigned_dev_update_msix_mmio");
|
| 1124 |
return;
|
| 1125 |
} |
| 1126 |
|
| 1127 |
if (assigned_dev->msi_virq_nr > 0) { |
| 1128 |
if (kvm_device_msix_assign(kvm_state, assigned_dev->dev_id) < 0) { |
| 1129 |
perror("assigned_dev_enable_msix: assign irq");
|
| 1130 |
return;
|
| 1131 |
} |
| 1132 |
} |
| 1133 |
assigned_dev->intx_route.mode = PCI_INTX_DISABLED; |
| 1134 |
assigned_dev->intx_route.irq = -1;
|
| 1135 |
assigned_dev->assigned_irq_type = ASSIGNED_IRQ_MSIX; |
| 1136 |
} else {
|
| 1137 |
assign_intx(assigned_dev); |
| 1138 |
} |
| 1139 |
} |
| 1140 |
|
| 1141 |
static uint32_t assigned_dev_pci_read_config(PCIDevice *pci_dev,
|
| 1142 |
uint32_t address, int len)
|
| 1143 |
{
|
| 1144 |
AssignedDevice *assigned_dev = DO_UPCAST(AssignedDevice, dev, pci_dev); |
| 1145 |
uint32_t virt_val = pci_default_read_config(pci_dev, address, len); |
| 1146 |
uint32_t real_val, emulate_mask, full_emulation_mask; |
| 1147 |
|
| 1148 |
emulate_mask = 0;
|
| 1149 |
memcpy(&emulate_mask, assigned_dev->emulate_config_read + address, len); |
| 1150 |
emulate_mask = le32_to_cpu(emulate_mask); |
| 1151 |
|
| 1152 |
full_emulation_mask = 0xffffffff >> (32 - len * 8); |
| 1153 |
|
| 1154 |
if (emulate_mask != full_emulation_mask) {
|
| 1155 |
real_val = assigned_dev_pci_read(pci_dev, address, len); |
| 1156 |
return (virt_val & emulate_mask) | (real_val & ~emulate_mask);
|
| 1157 |
} else {
|
| 1158 |
return virt_val;
|
| 1159 |
} |
| 1160 |
} |
| 1161 |
|
| 1162 |
static void assigned_dev_pci_write_config(PCIDevice *pci_dev, uint32_t address, |
| 1163 |
uint32_t val, int len)
|
| 1164 |
{
|
| 1165 |
AssignedDevice *assigned_dev = DO_UPCAST(AssignedDevice, dev, pci_dev); |
| 1166 |
uint16_t old_cmd = pci_get_word(pci_dev->config + PCI_COMMAND); |
| 1167 |
uint32_t emulate_mask, full_emulation_mask; |
| 1168 |
int ret;
|
| 1169 |
|
| 1170 |
pci_default_write_config(pci_dev, address, val, len); |
| 1171 |
|
| 1172 |
if (kvm_has_intx_set_mask() &&
|
| 1173 |
range_covers_byte(address, len, PCI_COMMAND + 1)) {
|
| 1174 |
bool intx_masked = (pci_get_word(pci_dev->config + PCI_COMMAND) &
|
| 1175 |
PCI_COMMAND_INTX_DISABLE); |
| 1176 |
|
| 1177 |
if (intx_masked != !!(old_cmd & PCI_COMMAND_INTX_DISABLE)) {
|
| 1178 |
ret = kvm_device_intx_set_mask(kvm_state, assigned_dev->dev_id, |
| 1179 |
intx_masked); |
| 1180 |
if (ret) {
|
| 1181 |
perror("assigned_dev_pci_write_config: set intx mask");
|
| 1182 |
} |
| 1183 |
} |
| 1184 |
} |
| 1185 |
if (assigned_dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) {
|
| 1186 |
if (range_covers_byte(address, len,
|
| 1187 |
pci_dev->msi_cap + PCI_MSI_FLAGS)) {
|
| 1188 |
assigned_dev_update_msi(pci_dev); |
| 1189 |
} |
| 1190 |
} |
| 1191 |
if (assigned_dev->cap.available & ASSIGNED_DEVICE_CAP_MSIX) {
|
| 1192 |
if (range_covers_byte(address, len,
|
| 1193 |
pci_dev->msix_cap + PCI_MSIX_FLAGS + 1)) {
|
| 1194 |
assigned_dev_update_msix(pci_dev); |
| 1195 |
} |
| 1196 |
} |
| 1197 |
|
| 1198 |
emulate_mask = 0;
|
| 1199 |
memcpy(&emulate_mask, assigned_dev->emulate_config_write + address, len); |
| 1200 |
emulate_mask = le32_to_cpu(emulate_mask); |
| 1201 |
|
| 1202 |
full_emulation_mask = 0xffffffff >> (32 - len * 8); |
| 1203 |
|
| 1204 |
if (emulate_mask != full_emulation_mask) {
|
| 1205 |
if (emulate_mask) {
|
| 1206 |
val &= ~emulate_mask; |
| 1207 |
val |= assigned_dev_pci_read(pci_dev, address, len) & emulate_mask; |
| 1208 |
} |
| 1209 |
assigned_dev_pci_write(pci_dev, address, val, len); |
| 1210 |
} |
| 1211 |
} |
| 1212 |
|
| 1213 |
static void assigned_dev_setup_cap_read(AssignedDevice *dev, uint32_t offset, |
| 1214 |
uint32_t len) |
| 1215 |
{
|
| 1216 |
assigned_dev_direct_config_read(dev, offset, len); |
| 1217 |
assigned_dev_emulate_config_read(dev, offset + PCI_CAP_LIST_NEXT, 1);
|
| 1218 |
} |
| 1219 |
|
| 1220 |
static int assigned_device_pci_cap_init(PCIDevice *pci_dev) |
| 1221 |
{
|
| 1222 |
AssignedDevice *dev = DO_UPCAST(AssignedDevice, dev, pci_dev); |
| 1223 |
PCIRegion *pci_region = dev->real_device.regions; |
| 1224 |
int ret, pos;
|
| 1225 |
|
| 1226 |
/* Clear initial capabilities pointer and status copied from hw */
|
| 1227 |
pci_set_byte(pci_dev->config + PCI_CAPABILITY_LIST, 0);
|
| 1228 |
pci_set_word(pci_dev->config + PCI_STATUS, |
| 1229 |
pci_get_word(pci_dev->config + PCI_STATUS) & |
| 1230 |
~PCI_STATUS_CAP_LIST); |
| 1231 |
|
| 1232 |
/* Expose MSI capability
|
| 1233 |
* MSI capability is the 1st capability in capability config */
|
| 1234 |
pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_MSI, 0);
|
| 1235 |
if (pos != 0 && kvm_check_extension(kvm_state, KVM_CAP_ASSIGN_DEV_IRQ)) { |
| 1236 |
if (!check_irqchip_in_kernel()) {
|
| 1237 |
return -ENOTSUP;
|
| 1238 |
} |
| 1239 |
dev->cap.available |= ASSIGNED_DEVICE_CAP_MSI; |
| 1240 |
/* Only 32-bit/no-mask currently supported */
|
| 1241 |
ret = pci_add_capability(pci_dev, PCI_CAP_ID_MSI, pos, 10);
|
| 1242 |
if (ret < 0) { |
| 1243 |
return ret;
|
| 1244 |
} |
| 1245 |
pci_dev->msi_cap = pos; |
| 1246 |
|
| 1247 |
pci_set_word(pci_dev->config + pos + PCI_MSI_FLAGS, |
| 1248 |
pci_get_word(pci_dev->config + pos + PCI_MSI_FLAGS) & |
| 1249 |
PCI_MSI_FLAGS_QMASK); |
| 1250 |
pci_set_long(pci_dev->config + pos + PCI_MSI_ADDRESS_LO, 0);
|
| 1251 |
pci_set_word(pci_dev->config + pos + PCI_MSI_DATA_32, 0);
|
| 1252 |
|
| 1253 |
/* Set writable fields */
|
| 1254 |
pci_set_word(pci_dev->wmask + pos + PCI_MSI_FLAGS, |
| 1255 |
PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE); |
| 1256 |
pci_set_long(pci_dev->wmask + pos + PCI_MSI_ADDRESS_LO, 0xfffffffc);
|
| 1257 |
pci_set_word(pci_dev->wmask + pos + PCI_MSI_DATA_32, 0xffff);
|
| 1258 |
} |
| 1259 |
/* Expose MSI-X capability */
|
| 1260 |
pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_MSIX, 0);
|
| 1261 |
if (pos != 0 && kvm_device_msix_supported(kvm_state)) { |
| 1262 |
int bar_nr;
|
| 1263 |
uint32_t msix_table_entry; |
| 1264 |
|
| 1265 |
if (!check_irqchip_in_kernel()) {
|
| 1266 |
return -ENOTSUP;
|
| 1267 |
} |
| 1268 |
dev->cap.available |= ASSIGNED_DEVICE_CAP_MSIX; |
| 1269 |
ret = pci_add_capability(pci_dev, PCI_CAP_ID_MSIX, pos, 12);
|
| 1270 |
if (ret < 0) { |
| 1271 |
return ret;
|
| 1272 |
} |
| 1273 |
pci_dev->msix_cap = pos; |
| 1274 |
|
| 1275 |
pci_set_word(pci_dev->config + pos + PCI_MSIX_FLAGS, |
| 1276 |
pci_get_word(pci_dev->config + pos + PCI_MSIX_FLAGS) & |
| 1277 |
PCI_MSIX_FLAGS_QSIZE); |
| 1278 |
|
| 1279 |
/* Only enable and function mask bits are writable */
|
| 1280 |
pci_set_word(pci_dev->wmask + pos + PCI_MSIX_FLAGS, |
| 1281 |
PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); |
| 1282 |
|
| 1283 |
msix_table_entry = pci_get_long(pci_dev->config + pos + PCI_MSIX_TABLE); |
| 1284 |
bar_nr = msix_table_entry & PCI_MSIX_FLAGS_BIRMASK; |
| 1285 |
msix_table_entry &= ~PCI_MSIX_FLAGS_BIRMASK; |
| 1286 |
dev->msix_table_addr = pci_region[bar_nr].base_addr + msix_table_entry; |
| 1287 |
dev->msix_max = pci_get_word(pci_dev->config + pos + PCI_MSIX_FLAGS); |
| 1288 |
dev->msix_max &= PCI_MSIX_FLAGS_QSIZE; |
| 1289 |
dev->msix_max += 1;
|
| 1290 |
} |
| 1291 |
|
| 1292 |
/* Minimal PM support, nothing writable, device appears to NAK changes */
|
| 1293 |
pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_PM, 0);
|
| 1294 |
if (pos) {
|
| 1295 |
uint16_t pmc; |
| 1296 |
|
| 1297 |
ret = pci_add_capability(pci_dev, PCI_CAP_ID_PM, pos, PCI_PM_SIZEOF); |
| 1298 |
if (ret < 0) { |
| 1299 |
return ret;
|
| 1300 |
} |
| 1301 |
|
| 1302 |
assigned_dev_setup_cap_read(dev, pos, PCI_PM_SIZEOF); |
| 1303 |
|
| 1304 |
pmc = pci_get_word(pci_dev->config + pos + PCI_CAP_FLAGS); |
| 1305 |
pmc &= (PCI_PM_CAP_VER_MASK | PCI_PM_CAP_DSI); |
| 1306 |
pci_set_word(pci_dev->config + pos + PCI_CAP_FLAGS, pmc); |
| 1307 |
|
| 1308 |
/* assign_device will bring the device up to D0, so we don't need
|
| 1309 |
* to worry about doing that ourselves here. */
|
| 1310 |
pci_set_word(pci_dev->config + pos + PCI_PM_CTRL, |
| 1311 |
PCI_PM_CTRL_NO_SOFT_RESET); |
| 1312 |
|
| 1313 |
pci_set_byte(pci_dev->config + pos + PCI_PM_PPB_EXTENSIONS, 0);
|
| 1314 |
pci_set_byte(pci_dev->config + pos + PCI_PM_DATA_REGISTER, 0);
|
| 1315 |
} |
| 1316 |
|
| 1317 |
pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_EXP, 0);
|
| 1318 |
if (pos) {
|
| 1319 |
uint8_t version, size = 0;
|
| 1320 |
uint16_t type, devctl, lnksta; |
| 1321 |
uint32_t devcap, lnkcap; |
| 1322 |
|
| 1323 |
version = pci_get_byte(pci_dev->config + pos + PCI_EXP_FLAGS); |
| 1324 |
version &= PCI_EXP_FLAGS_VERS; |
| 1325 |
if (version == 1) { |
| 1326 |
size = 0x14;
|
| 1327 |
} else if (version == 2) { |
| 1328 |
/*
|
| 1329 |
* Check for non-std size, accept reduced size to 0x34,
|
| 1330 |
* which is what bcm5761 implemented, violating the
|
| 1331 |
* PCIe v3.0 spec that regs should exist and be read as 0,
|
| 1332 |
* not optionally provided and shorten the struct size.
|
| 1333 |
*/
|
| 1334 |
size = MIN(0x3c, PCI_CONFIG_SPACE_SIZE - pos);
|
| 1335 |
if (size < 0x34) { |
| 1336 |
error_report("%s: Invalid size PCIe cap-id 0x%x",
|
| 1337 |
__func__, PCI_CAP_ID_EXP); |
| 1338 |
return -EINVAL;
|
| 1339 |
} else if (size != 0x3c) { |
| 1340 |
error_report("WARNING, %s: PCIe cap-id 0x%x has "
|
| 1341 |
"non-standard size 0x%x; std size should be 0x3c",
|
| 1342 |
__func__, PCI_CAP_ID_EXP, size); |
| 1343 |
} |
| 1344 |
} else if (version == 0) { |
| 1345 |
uint16_t vid, did; |
| 1346 |
vid = pci_get_word(pci_dev->config + PCI_VENDOR_ID); |
| 1347 |
did = pci_get_word(pci_dev->config + PCI_DEVICE_ID); |
| 1348 |
if (vid == PCI_VENDOR_ID_INTEL && did == 0x10ed) { |
| 1349 |
/*
|
| 1350 |
* quirk for Intel 82599 VF with invalid PCIe capability
|
| 1351 |
* version, should really be version 2 (same as PF)
|
| 1352 |
*/
|
| 1353 |
size = 0x3c;
|
| 1354 |
} |
| 1355 |
} |
| 1356 |
|
| 1357 |
if (size == 0) { |
| 1358 |
error_report("%s: Unsupported PCI express capability version %d",
|
| 1359 |
__func__, version); |
| 1360 |
return -EINVAL;
|
| 1361 |
} |
| 1362 |
|
| 1363 |
ret = pci_add_capability(pci_dev, PCI_CAP_ID_EXP, pos, size); |
| 1364 |
if (ret < 0) { |
| 1365 |
return ret;
|
| 1366 |
} |
| 1367 |
|
| 1368 |
assigned_dev_setup_cap_read(dev, pos, size); |
| 1369 |
|
| 1370 |
type = pci_get_word(pci_dev->config + pos + PCI_EXP_FLAGS); |
| 1371 |
type = (type & PCI_EXP_FLAGS_TYPE) >> 4;
|
| 1372 |
if (type != PCI_EXP_TYPE_ENDPOINT &&
|
| 1373 |
type != PCI_EXP_TYPE_LEG_END && type != PCI_EXP_TYPE_RC_END) {
|
| 1374 |
error_report("Device assignment only supports endpoint assignment,"
|
| 1375 |
" device type %d", type);
|
| 1376 |
return -EINVAL;
|
| 1377 |
} |
| 1378 |
|
| 1379 |
/* capabilities, pass existing read-only copy
|
| 1380 |
* PCI_EXP_FLAGS_IRQ: updated by hardware, should be direct read */
|
| 1381 |
|
| 1382 |
/* device capabilities: hide FLR */
|
| 1383 |
devcap = pci_get_long(pci_dev->config + pos + PCI_EXP_DEVCAP); |
| 1384 |
devcap &= ~PCI_EXP_DEVCAP_FLR; |
| 1385 |
pci_set_long(pci_dev->config + pos + PCI_EXP_DEVCAP, devcap); |
| 1386 |
|
| 1387 |
/* device control: clear all error reporting enable bits, leaving
|
| 1388 |
* only a few host values. Note, these are
|
| 1389 |
* all writable, but not passed to hw.
|
| 1390 |
*/
|
| 1391 |
devctl = pci_get_word(pci_dev->config + pos + PCI_EXP_DEVCTL); |
| 1392 |
devctl = (devctl & (PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_PAYLOAD)) | |
| 1393 |
PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN; |
| 1394 |
pci_set_word(pci_dev->config + pos + PCI_EXP_DEVCTL, devctl); |
| 1395 |
devctl = PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_AUX_PME; |
| 1396 |
pci_set_word(pci_dev->wmask + pos + PCI_EXP_DEVCTL, ~devctl); |
| 1397 |
|
| 1398 |
/* Clear device status */
|
| 1399 |
pci_set_word(pci_dev->config + pos + PCI_EXP_DEVSTA, 0);
|
| 1400 |
|
| 1401 |
/* Link capabilities, expose links and latencues, clear reporting */
|
| 1402 |
lnkcap = pci_get_long(pci_dev->config + pos + PCI_EXP_LNKCAP); |
| 1403 |
lnkcap &= (PCI_EXP_LNKCAP_SLS | PCI_EXP_LNKCAP_MLW | |
| 1404 |
PCI_EXP_LNKCAP_ASPMS | PCI_EXP_LNKCAP_L0SEL | |
| 1405 |
PCI_EXP_LNKCAP_L1EL); |
| 1406 |
pci_set_long(pci_dev->config + pos + PCI_EXP_LNKCAP, lnkcap); |
| 1407 |
|
| 1408 |
/* Link control, pass existing read-only copy. Should be writable? */
|
| 1409 |
|
| 1410 |
/* Link status, only expose current speed and width */
|
| 1411 |
lnksta = pci_get_word(pci_dev->config + pos + PCI_EXP_LNKSTA); |
| 1412 |
lnksta &= (PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW); |
| 1413 |
pci_set_word(pci_dev->config + pos + PCI_EXP_LNKSTA, lnksta); |
| 1414 |
|
| 1415 |
if (version >= 2) { |
| 1416 |
/* Slot capabilities, control, status - not needed for endpoints */
|
| 1417 |
pci_set_long(pci_dev->config + pos + PCI_EXP_SLTCAP, 0);
|
| 1418 |
pci_set_word(pci_dev->config + pos + PCI_EXP_SLTCTL, 0);
|
| 1419 |
pci_set_word(pci_dev->config + pos + PCI_EXP_SLTSTA, 0);
|
| 1420 |
|
| 1421 |
/* Root control, capabilities, status - not needed for endpoints */
|
| 1422 |
pci_set_word(pci_dev->config + pos + PCI_EXP_RTCTL, 0);
|
| 1423 |
pci_set_word(pci_dev->config + pos + PCI_EXP_RTCAP, 0);
|
| 1424 |
pci_set_long(pci_dev->config + pos + PCI_EXP_RTSTA, 0);
|
| 1425 |
|
| 1426 |
/* Device capabilities/control 2, pass existing read-only copy */
|
| 1427 |
/* Link control 2, pass existing read-only copy */
|
| 1428 |
} |
| 1429 |
} |
| 1430 |
|
| 1431 |
pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_PCIX, 0);
|
| 1432 |
if (pos) {
|
| 1433 |
uint16_t cmd; |
| 1434 |
uint32_t status; |
| 1435 |
|
| 1436 |
/* Only expose the minimum, 8 byte capability */
|
| 1437 |
ret = pci_add_capability(pci_dev, PCI_CAP_ID_PCIX, pos, 8);
|
| 1438 |
if (ret < 0) { |
| 1439 |
return ret;
|
| 1440 |
} |
| 1441 |
|
| 1442 |
assigned_dev_setup_cap_read(dev, pos, 8);
|
| 1443 |
|
| 1444 |
/* Command register, clear upper bits, including extended modes */
|
| 1445 |
cmd = pci_get_word(pci_dev->config + pos + PCI_X_CMD); |
| 1446 |
cmd &= (PCI_X_CMD_DPERR_E | PCI_X_CMD_ERO | PCI_X_CMD_MAX_READ | |
| 1447 |
PCI_X_CMD_MAX_SPLIT); |
| 1448 |
pci_set_word(pci_dev->config + pos + PCI_X_CMD, cmd); |
| 1449 |
|
| 1450 |
/* Status register, update with emulated PCI bus location, clear
|
| 1451 |
* error bits, leave the rest. */
|
| 1452 |
status = pci_get_long(pci_dev->config + pos + PCI_X_STATUS); |
| 1453 |
status &= ~(PCI_X_STATUS_BUS | PCI_X_STATUS_DEVFN); |
| 1454 |
status |= (pci_bus_num(pci_dev->bus) << 8) | pci_dev->devfn;
|
| 1455 |
status &= ~(PCI_X_STATUS_SPL_DISC | PCI_X_STATUS_UNX_SPL | |
| 1456 |
PCI_X_STATUS_SPL_ERR); |
| 1457 |
pci_set_long(pci_dev->config + pos + PCI_X_STATUS, status); |
| 1458 |
} |
| 1459 |
|
| 1460 |
pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_VPD, 0);
|
| 1461 |
if (pos) {
|
| 1462 |
/* Direct R/W passthrough */
|
| 1463 |
ret = pci_add_capability(pci_dev, PCI_CAP_ID_VPD, pos, 8);
|
| 1464 |
if (ret < 0) { |
| 1465 |
return ret;
|
| 1466 |
} |
| 1467 |
|
| 1468 |
assigned_dev_setup_cap_read(dev, pos, 8);
|
| 1469 |
|
| 1470 |
/* direct write for cap content */
|
| 1471 |
assigned_dev_direct_config_write(dev, pos + 2, 6); |
| 1472 |
} |
| 1473 |
|
| 1474 |
/* Devices can have multiple vendor capabilities, get them all */
|
| 1475 |
for (pos = 0; (pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_VNDR, pos)); |
| 1476 |
pos += PCI_CAP_LIST_NEXT) {
|
| 1477 |
uint8_t len = pci_get_byte(pci_dev->config + pos + PCI_CAP_FLAGS); |
| 1478 |
/* Direct R/W passthrough */
|
| 1479 |
ret = pci_add_capability(pci_dev, PCI_CAP_ID_VNDR, pos, len); |
| 1480 |
if (ret < 0) { |
| 1481 |
return ret;
|
| 1482 |
} |
| 1483 |
|
| 1484 |
assigned_dev_setup_cap_read(dev, pos, len); |
| 1485 |
|
| 1486 |
/* direct write for cap content */
|
| 1487 |
assigned_dev_direct_config_write(dev, pos + 2, len - 2); |
| 1488 |
} |
| 1489 |
|
| 1490 |
/* If real and virtual capability list status bits differ, virtualize the
|
| 1491 |
* access. */
|
| 1492 |
if ((pci_get_word(pci_dev->config + PCI_STATUS) & PCI_STATUS_CAP_LIST) !=
|
| 1493 |
(assigned_dev_pci_read_byte(pci_dev, PCI_STATUS) & |
| 1494 |
PCI_STATUS_CAP_LIST)) {
|
| 1495 |
dev->emulate_config_read[PCI_STATUS] |= PCI_STATUS_CAP_LIST; |
| 1496 |
} |
| 1497 |
|
| 1498 |
return 0; |
| 1499 |
} |
| 1500 |
|
| 1501 |
static uint64_t
|
| 1502 |
assigned_dev_msix_mmio_read(void *opaque, hwaddr addr,
|
| 1503 |
unsigned size)
|
| 1504 |
{
|
| 1505 |
AssignedDevice *adev = opaque; |
| 1506 |
uint64_t val; |
| 1507 |
|
| 1508 |
memcpy(&val, (void *)((uint8_t *)adev->msix_table + addr), size);
|
| 1509 |
|
| 1510 |
return val;
|
| 1511 |
} |
| 1512 |
|
| 1513 |
static void assigned_dev_msix_mmio_write(void *opaque, hwaddr addr, |
| 1514 |
uint64_t val, unsigned size)
|
| 1515 |
{
|
| 1516 |
AssignedDevice *adev = opaque; |
| 1517 |
PCIDevice *pdev = &adev->dev; |
| 1518 |
uint16_t ctrl; |
| 1519 |
MSIXTableEntry orig; |
| 1520 |
int i = addr >> 4; |
| 1521 |
|
| 1522 |
if (i >= adev->msix_max) {
|
| 1523 |
return; /* Drop write */ |
| 1524 |
} |
| 1525 |
|
| 1526 |
ctrl = pci_get_word(pdev->config + pdev->msix_cap + PCI_MSIX_FLAGS); |
| 1527 |
|
| 1528 |
DEBUG("write to MSI-X table offset 0x%lx, val 0x%lx\n", addr, val);
|
| 1529 |
|
| 1530 |
if (ctrl & PCI_MSIX_FLAGS_ENABLE) {
|
| 1531 |
orig = adev->msix_table[i]; |
| 1532 |
} |
| 1533 |
|
| 1534 |
memcpy((uint8_t *)adev->msix_table + addr, &val, size); |
| 1535 |
|
| 1536 |
if (ctrl & PCI_MSIX_FLAGS_ENABLE) {
|
| 1537 |
MSIXTableEntry *entry = &adev->msix_table[i]; |
| 1538 |
|
| 1539 |
if (!assigned_dev_msix_masked(&orig) &&
|
| 1540 |
assigned_dev_msix_masked(entry)) {
|
| 1541 |
/*
|
| 1542 |
* Vector masked, disable it
|
| 1543 |
*
|
| 1544 |
* XXX It's not clear if we can or should actually attempt
|
| 1545 |
* to mask or disable the interrupt. KVM doesn't have
|
| 1546 |
* support for pending bits and kvm_assign_set_msix_entry
|
| 1547 |
* doesn't modify the device hardware mask. Interrupts
|
| 1548 |
* while masked are simply not injected to the guest, so
|
| 1549 |
* are lost. Can we get away with always injecting an
|
| 1550 |
* interrupt on unmask?
|
| 1551 |
*/
|
| 1552 |
} else if (assigned_dev_msix_masked(&orig) && |
| 1553 |
!assigned_dev_msix_masked(entry)) {
|
| 1554 |
/* Vector unmasked */
|
| 1555 |
if (i >= adev->msi_virq_nr || adev->msi_virq[i] < 0) { |
| 1556 |
/* Previously unassigned vector, start from scratch */
|
| 1557 |
assigned_dev_update_msix(pdev); |
| 1558 |
return;
|
| 1559 |
} else {
|
| 1560 |
/* Update an existing, previously masked vector */
|
| 1561 |
MSIMessage msg; |
| 1562 |
int ret;
|
| 1563 |
|
| 1564 |
msg.address = entry->addr_lo | |
| 1565 |
((uint64_t)entry->addr_hi << 32);
|
| 1566 |
msg.data = entry->data; |
| 1567 |
|
| 1568 |
ret = kvm_irqchip_update_msi_route(kvm_state, |
| 1569 |
adev->msi_virq[i], msg); |
| 1570 |
if (ret) {
|
| 1571 |
error_report("Error updating irq routing entry (%d)", ret);
|
| 1572 |
} |
| 1573 |
} |
| 1574 |
} |
| 1575 |
} |
| 1576 |
} |
| 1577 |
|
| 1578 |
static const MemoryRegionOps assigned_dev_msix_mmio_ops = { |
| 1579 |
.read = assigned_dev_msix_mmio_read, |
| 1580 |
.write = assigned_dev_msix_mmio_write, |
| 1581 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 1582 |
.valid = {
|
| 1583 |
.min_access_size = 4,
|
| 1584 |
.max_access_size = 8,
|
| 1585 |
}, |
| 1586 |
.impl = {
|
| 1587 |
.min_access_size = 4,
|
| 1588 |
.max_access_size = 8,
|
| 1589 |
}, |
| 1590 |
}; |
| 1591 |
|
| 1592 |
static void assigned_dev_msix_reset(AssignedDevice *dev) |
| 1593 |
{
|
| 1594 |
MSIXTableEntry *entry; |
| 1595 |
int i;
|
| 1596 |
|
| 1597 |
if (!dev->msix_table) {
|
| 1598 |
return;
|
| 1599 |
} |
| 1600 |
|
| 1601 |
memset(dev->msix_table, 0, MSIX_PAGE_SIZE);
|
| 1602 |
|
| 1603 |
for (i = 0, entry = dev->msix_table; i < dev->msix_max; i++, entry++) { |
| 1604 |
entry->ctrl = cpu_to_le32(0x1); /* Masked */ |
| 1605 |
} |
| 1606 |
} |
| 1607 |
|
| 1608 |
static int assigned_dev_register_msix_mmio(AssignedDevice *dev) |
| 1609 |
{
|
| 1610 |
dev->msix_table = mmap(NULL, MSIX_PAGE_SIZE, PROT_READ|PROT_WRITE,
|
| 1611 |
MAP_ANONYMOUS|MAP_PRIVATE, 0, 0); |
| 1612 |
if (dev->msix_table == MAP_FAILED) {
|
| 1613 |
error_report("fail allocate msix_table! %s", strerror(errno));
|
| 1614 |
return -EFAULT;
|
| 1615 |
} |
| 1616 |
|
| 1617 |
assigned_dev_msix_reset(dev); |
| 1618 |
|
| 1619 |
memory_region_init_io(&dev->mmio, &assigned_dev_msix_mmio_ops, dev, |
| 1620 |
"assigned-dev-msix", MSIX_PAGE_SIZE);
|
| 1621 |
return 0; |
| 1622 |
} |
| 1623 |
|
| 1624 |
static void assigned_dev_unregister_msix_mmio(AssignedDevice *dev) |
| 1625 |
{
|
| 1626 |
if (!dev->msix_table) {
|
| 1627 |
return;
|
| 1628 |
} |
| 1629 |
|
| 1630 |
memory_region_destroy(&dev->mmio); |
| 1631 |
|
| 1632 |
if (munmap(dev->msix_table, MSIX_PAGE_SIZE) == -1) { |
| 1633 |
error_report("error unmapping msix_table! %s", strerror(errno));
|
| 1634 |
} |
| 1635 |
dev->msix_table = NULL;
|
| 1636 |
} |
| 1637 |
|
| 1638 |
static const VMStateDescription vmstate_assigned_device = { |
| 1639 |
.name = "pci-assign",
|
| 1640 |
.unmigratable = 1,
|
| 1641 |
}; |
| 1642 |
|
| 1643 |
static void reset_assigned_device(DeviceState *dev) |
| 1644 |
{
|
| 1645 |
PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev); |
| 1646 |
AssignedDevice *adev = DO_UPCAST(AssignedDevice, dev, pci_dev); |
| 1647 |
char reset_file[64]; |
| 1648 |
const char reset[] = "1"; |
| 1649 |
int fd, ret;
|
| 1650 |
|
| 1651 |
/*
|
| 1652 |
* If a guest is reset without being shutdown, MSI/MSI-X can still
|
| 1653 |
* be running. We want to return the device to a known state on
|
| 1654 |
* reset, so disable those here. We especially do not want MSI-X
|
| 1655 |
* enabled since it lives in MMIO space, which is about to get
|
| 1656 |
* disabled.
|
| 1657 |
*/
|
| 1658 |
if (adev->assigned_irq_type == ASSIGNED_IRQ_MSIX) {
|
| 1659 |
uint16_t ctrl = pci_get_word(pci_dev->config + |
| 1660 |
pci_dev->msix_cap + PCI_MSIX_FLAGS); |
| 1661 |
|
| 1662 |
pci_set_word(pci_dev->config + pci_dev->msix_cap + PCI_MSIX_FLAGS, |
| 1663 |
ctrl & ~PCI_MSIX_FLAGS_ENABLE); |
| 1664 |
assigned_dev_update_msix(pci_dev); |
| 1665 |
} else if (adev->assigned_irq_type == ASSIGNED_IRQ_MSI) { |
| 1666 |
uint8_t ctrl = pci_get_byte(pci_dev->config + |
| 1667 |
pci_dev->msi_cap + PCI_MSI_FLAGS); |
| 1668 |
|
| 1669 |
pci_set_byte(pci_dev->config + pci_dev->msi_cap + PCI_MSI_FLAGS, |
| 1670 |
ctrl & ~PCI_MSI_FLAGS_ENABLE); |
| 1671 |
assigned_dev_update_msi(pci_dev); |
| 1672 |
} |
| 1673 |
|
| 1674 |
snprintf(reset_file, sizeof(reset_file),
|
| 1675 |
"/sys/bus/pci/devices/%04x:%02x:%02x.%01x/reset",
|
| 1676 |
adev->host.domain, adev->host.bus, adev->host.slot, |
| 1677 |
adev->host.function); |
| 1678 |
|
| 1679 |
/*
|
| 1680 |
* Issue a device reset via pci-sysfs. Note that we use write(2) here
|
| 1681 |
* and ignore the return value because some kernels have a bug that
|
| 1682 |
* returns 0 rather than bytes written on success, sending us into an
|
| 1683 |
* infinite retry loop using other write mechanisms.
|
| 1684 |
*/
|
| 1685 |
fd = open(reset_file, O_WRONLY); |
| 1686 |
if (fd != -1) { |
| 1687 |
ret = write(fd, reset, strlen(reset)); |
| 1688 |
(void)ret;
|
| 1689 |
close(fd); |
| 1690 |
} |
| 1691 |
|
| 1692 |
/*
|
| 1693 |
* When a 0 is written to the bus master register, the device is logically
|
| 1694 |
* disconnected from the PCI bus. This avoids further DMA transfers.
|
| 1695 |
*/
|
| 1696 |
assigned_dev_pci_write_config(pci_dev, PCI_COMMAND, 0, 1); |
| 1697 |
} |
| 1698 |
|
| 1699 |
static int assigned_initfn(struct PCIDevice *pci_dev) |
| 1700 |
{
|
| 1701 |
AssignedDevice *dev = DO_UPCAST(AssignedDevice, dev, pci_dev); |
| 1702 |
uint8_t e_intx; |
| 1703 |
int r;
|
| 1704 |
|
| 1705 |
if (!kvm_enabled()) {
|
| 1706 |
error_report("pci-assign: error: requires KVM support");
|
| 1707 |
return -1; |
| 1708 |
} |
| 1709 |
|
| 1710 |
if (!dev->host.domain && !dev->host.bus && !dev->host.slot &&
|
| 1711 |
!dev->host.function) {
|
| 1712 |
error_report("pci-assign: error: no host device specified");
|
| 1713 |
return -1; |
| 1714 |
} |
| 1715 |
|
| 1716 |
/*
|
| 1717 |
* Set up basic config space access control. Will be further refined during
|
| 1718 |
* device initialization.
|
| 1719 |
*/
|
| 1720 |
assigned_dev_emulate_config_read(dev, 0, PCI_CONFIG_SPACE_SIZE);
|
| 1721 |
assigned_dev_direct_config_read(dev, PCI_STATUS, 2);
|
| 1722 |
assigned_dev_direct_config_read(dev, PCI_REVISION_ID, 1);
|
| 1723 |
assigned_dev_direct_config_read(dev, PCI_CLASS_PROG, 3);
|
| 1724 |
assigned_dev_direct_config_read(dev, PCI_CACHE_LINE_SIZE, 1);
|
| 1725 |
assigned_dev_direct_config_read(dev, PCI_LATENCY_TIMER, 1);
|
| 1726 |
assigned_dev_direct_config_read(dev, PCI_BIST, 1);
|
| 1727 |
assigned_dev_direct_config_read(dev, PCI_CARDBUS_CIS, 4);
|
| 1728 |
assigned_dev_direct_config_read(dev, PCI_SUBSYSTEM_VENDOR_ID, 2);
|
| 1729 |
assigned_dev_direct_config_read(dev, PCI_SUBSYSTEM_ID, 2);
|
| 1730 |
assigned_dev_direct_config_read(dev, PCI_CAPABILITY_LIST + 1, 7); |
| 1731 |
assigned_dev_direct_config_read(dev, PCI_MIN_GNT, 1);
|
| 1732 |
assigned_dev_direct_config_read(dev, PCI_MAX_LAT, 1);
|
| 1733 |
memcpy(dev->emulate_config_write, dev->emulate_config_read, |
| 1734 |
sizeof(dev->emulate_config_read));
|
| 1735 |
|
| 1736 |
if (get_real_device(dev, dev->host.domain, dev->host.bus,
|
| 1737 |
dev->host.slot, dev->host.function)) {
|
| 1738 |
error_report("pci-assign: Error: Couldn't get real device (%s)!",
|
| 1739 |
dev->dev.qdev.id); |
| 1740 |
goto out;
|
| 1741 |
} |
| 1742 |
|
| 1743 |
if (assigned_device_pci_cap_init(pci_dev) < 0) { |
| 1744 |
goto out;
|
| 1745 |
} |
| 1746 |
|
| 1747 |
/* intercept MSI-X entry page in the MMIO */
|
| 1748 |
if (dev->cap.available & ASSIGNED_DEVICE_CAP_MSIX) {
|
| 1749 |
if (assigned_dev_register_msix_mmio(dev)) {
|
| 1750 |
goto out;
|
| 1751 |
} |
| 1752 |
} |
| 1753 |
|
| 1754 |
/* handle real device's MMIO/PIO BARs */
|
| 1755 |
if (assigned_dev_register_regions(dev->real_device.regions,
|
| 1756 |
dev->real_device.region_number, |
| 1757 |
dev)) {
|
| 1758 |
goto out;
|
| 1759 |
} |
| 1760 |
|
| 1761 |
/* handle interrupt routing */
|
| 1762 |
e_intx = dev->dev.config[PCI_INTERRUPT_PIN] - 1;
|
| 1763 |
dev->intpin = e_intx; |
| 1764 |
dev->intx_route.mode = PCI_INTX_DISABLED; |
| 1765 |
dev->intx_route.irq = -1;
|
| 1766 |
|
| 1767 |
/* assign device to guest */
|
| 1768 |
r = assign_device(dev); |
| 1769 |
if (r < 0) { |
| 1770 |
goto out;
|
| 1771 |
} |
| 1772 |
|
| 1773 |
/* assign legacy INTx to the device */
|
| 1774 |
r = assign_intx(dev); |
| 1775 |
if (r < 0) { |
| 1776 |
goto assigned_out;
|
| 1777 |
} |
| 1778 |
|
| 1779 |
assigned_dev_load_option_rom(dev); |
| 1780 |
|
| 1781 |
add_boot_device_path(dev->bootindex, &pci_dev->qdev, NULL);
|
| 1782 |
|
| 1783 |
return 0; |
| 1784 |
|
| 1785 |
assigned_out:
|
| 1786 |
deassign_device(dev); |
| 1787 |
out:
|
| 1788 |
free_assigned_device(dev); |
| 1789 |
return -1; |
| 1790 |
} |
| 1791 |
|
| 1792 |
static void assigned_exitfn(struct PCIDevice *pci_dev) |
| 1793 |
{
|
| 1794 |
AssignedDevice *dev = DO_UPCAST(AssignedDevice, dev, pci_dev); |
| 1795 |
|
| 1796 |
deassign_device(dev); |
| 1797 |
free_assigned_device(dev); |
| 1798 |
} |
| 1799 |
|
| 1800 |
static Property assigned_dev_properties[] = {
|
| 1801 |
DEFINE_PROP_PCI_HOST_DEVADDR("host", AssignedDevice, host),
|
| 1802 |
DEFINE_PROP_BIT("prefer_msi", AssignedDevice, features,
|
| 1803 |
ASSIGNED_DEVICE_PREFER_MSI_BIT, false),
|
| 1804 |
DEFINE_PROP_BIT("share_intx", AssignedDevice, features,
|
| 1805 |
ASSIGNED_DEVICE_SHARE_INTX_BIT, true),
|
| 1806 |
DEFINE_PROP_INT32("bootindex", AssignedDevice, bootindex, -1), |
| 1807 |
DEFINE_PROP_STRING("configfd", AssignedDevice, configfd_name),
|
| 1808 |
DEFINE_PROP_END_OF_LIST(), |
| 1809 |
}; |
| 1810 |
|
| 1811 |
static void assign_class_init(ObjectClass *klass, void *data) |
| 1812 |
{
|
| 1813 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 1814 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 1815 |
|
| 1816 |
k->init = assigned_initfn; |
| 1817 |
k->exit = assigned_exitfn; |
| 1818 |
k->config_read = assigned_dev_pci_read_config; |
| 1819 |
k->config_write = assigned_dev_pci_write_config; |
| 1820 |
dc->props = assigned_dev_properties; |
| 1821 |
dc->vmsd = &vmstate_assigned_device; |
| 1822 |
dc->reset = reset_assigned_device; |
| 1823 |
dc->desc = "KVM-based PCI passthrough";
|
| 1824 |
} |
| 1825 |
|
| 1826 |
static const TypeInfo assign_info = { |
| 1827 |
.name = "kvm-pci-assign",
|
| 1828 |
.parent = TYPE_PCI_DEVICE, |
| 1829 |
.instance_size = sizeof(AssignedDevice),
|
| 1830 |
.class_init = assign_class_init, |
| 1831 |
}; |
| 1832 |
|
| 1833 |
static void assign_register_types(void) |
| 1834 |
{
|
| 1835 |
type_register_static(&assign_info); |
| 1836 |
} |
| 1837 |
|
| 1838 |
type_init(assign_register_types) |
| 1839 |
|
| 1840 |
/*
|
| 1841 |
* Scan the assigned devices for the devices that have an option ROM, and then
|
| 1842 |
* load the corresponding ROM data to RAM. If an error occurs while loading an
|
| 1843 |
* option ROM, we just ignore that option ROM and continue with the next one.
|
| 1844 |
*/
|
| 1845 |
static void assigned_dev_load_option_rom(AssignedDevice *dev) |
| 1846 |
{
|
| 1847 |
char name[32], rom_file[64]; |
| 1848 |
FILE *fp; |
| 1849 |
uint8_t val; |
| 1850 |
struct stat st;
|
| 1851 |
void *ptr;
|
| 1852 |
|
| 1853 |
/* If loading ROM from file, pci handles it */
|
| 1854 |
if (dev->dev.romfile || !dev->dev.rom_bar) {
|
| 1855 |
return;
|
| 1856 |
} |
| 1857 |
|
| 1858 |
snprintf(rom_file, sizeof(rom_file),
|
| 1859 |
"/sys/bus/pci/devices/%04x:%02x:%02x.%01x/rom",
|
| 1860 |
dev->host.domain, dev->host.bus, dev->host.slot, |
| 1861 |
dev->host.function); |
| 1862 |
|
| 1863 |
if (stat(rom_file, &st)) {
|
| 1864 |
return;
|
| 1865 |
} |
| 1866 |
|
| 1867 |
if (access(rom_file, F_OK)) {
|
| 1868 |
error_report("pci-assign: Insufficient privileges for %s", rom_file);
|
| 1869 |
return;
|
| 1870 |
} |
| 1871 |
|
| 1872 |
/* Write "1" to the ROM file to enable it */
|
| 1873 |
fp = fopen(rom_file, "r+");
|
| 1874 |
if (fp == NULL) { |
| 1875 |
return;
|
| 1876 |
} |
| 1877 |
val = 1;
|
| 1878 |
if (fwrite(&val, 1, 1, fp) != 1) { |
| 1879 |
goto close_rom;
|
| 1880 |
} |
| 1881 |
fseek(fp, 0, SEEK_SET);
|
| 1882 |
|
| 1883 |
snprintf(name, sizeof(name), "%s.rom", |
| 1884 |
object_get_typename(OBJECT(dev))); |
| 1885 |
memory_region_init_ram(&dev->dev.rom, name, st.st_size); |
| 1886 |
vmstate_register_ram(&dev->dev.rom, &dev->dev.qdev); |
| 1887 |
ptr = memory_region_get_ram_ptr(&dev->dev.rom); |
| 1888 |
memset(ptr, 0xff, st.st_size);
|
| 1889 |
|
| 1890 |
if (!fread(ptr, 1, st.st_size, fp)) { |
| 1891 |
error_report("pci-assign: Cannot read from host %s\n"
|
| 1892 |
"\tDevice option ROM contents are probably invalid "
|
| 1893 |
"(check dmesg).\n\tSkip option ROM probe with rombar=0, "
|
| 1894 |
"or load from file with romfile=", rom_file);
|
| 1895 |
memory_region_destroy(&dev->dev.rom); |
| 1896 |
goto close_rom;
|
| 1897 |
} |
| 1898 |
|
| 1899 |
pci_register_bar(&dev->dev, PCI_ROM_SLOT, 0, &dev->dev.rom);
|
| 1900 |
dev->dev.has_rom = true;
|
| 1901 |
close_rom:
|
| 1902 |
/* Write "0" to disable ROM */
|
| 1903 |
fseek(fp, 0, SEEK_SET);
|
| 1904 |
val = 0;
|
| 1905 |
if (!fwrite(&val, 1, 1, fp)) { |
| 1906 |
DEBUG("%s\n", "Failed to disable pci-sysfs rom file"); |
| 1907 |
} |
| 1908 |
fclose(fp); |
| 1909 |
} |