root / hw / pc.c @ a8170e5e
History | View | Annotate | Download (30.5 kB)
1 |
/*
|
---|---|
2 |
* QEMU PC System Emulator
|
3 |
*
|
4 |
* Copyright (c) 2003-2004 Fabrice Bellard
|
5 |
*
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 |
* of this software and associated documentation files (the "Software"), to deal
|
8 |
* in the Software without restriction, including without limitation the rights
|
9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 |
* copies of the Software, and to permit persons to whom the Software is
|
11 |
* furnished to do so, subject to the following conditions:
|
12 |
*
|
13 |
* The above copyright notice and this permission notice shall be included in
|
14 |
* all copies or substantial portions of the Software.
|
15 |
*
|
16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 |
* THE SOFTWARE.
|
23 |
*/
|
24 |
#include "hw.h" |
25 |
#include "pc.h" |
26 |
#include "serial.h" |
27 |
#include "apic.h" |
28 |
#include "fdc.h" |
29 |
#include "ide.h" |
30 |
#include "pci.h" |
31 |
#include "monitor.h" |
32 |
#include "fw_cfg.h" |
33 |
#include "hpet_emul.h" |
34 |
#include "smbios.h" |
35 |
#include "loader.h" |
36 |
#include "elf.h" |
37 |
#include "multiboot.h" |
38 |
#include "mc146818rtc.h" |
39 |
#include "i8254.h" |
40 |
#include "pcspk.h" |
41 |
#include "msi.h" |
42 |
#include "sysbus.h" |
43 |
#include "sysemu.h" |
44 |
#include "kvm.h" |
45 |
#include "kvm_i386.h" |
46 |
#include "xen.h" |
47 |
#include "blockdev.h" |
48 |
#include "hw/block-common.h" |
49 |
#include "ui/qemu-spice.h" |
50 |
#include "memory.h" |
51 |
#include "exec-memory.h" |
52 |
#include "arch_init.h" |
53 |
#include "bitmap.h" |
54 |
|
55 |
/* debug PC/ISA interrupts */
|
56 |
//#define DEBUG_IRQ
|
57 |
|
58 |
#ifdef DEBUG_IRQ
|
59 |
#define DPRINTF(fmt, ...) \
|
60 |
do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
61 |
#else
|
62 |
#define DPRINTF(fmt, ...)
|
63 |
#endif
|
64 |
|
65 |
/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
|
66 |
#define ACPI_DATA_SIZE 0x10000 |
67 |
#define BIOS_CFG_IOPORT 0x510 |
68 |
#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
69 |
#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
70 |
#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
71 |
#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
72 |
#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
73 |
|
74 |
#define MSI_ADDR_BASE 0xfee00000 |
75 |
|
76 |
#define E820_NR_ENTRIES 16 |
77 |
|
78 |
struct e820_entry {
|
79 |
uint64_t address; |
80 |
uint64_t length; |
81 |
uint32_t type; |
82 |
} QEMU_PACKED __attribute((__aligned__(4)));
|
83 |
|
84 |
struct e820_table {
|
85 |
uint32_t count; |
86 |
struct e820_entry entry[E820_NR_ENTRIES];
|
87 |
} QEMU_PACKED __attribute((__aligned__(4)));
|
88 |
|
89 |
static struct e820_table e820_table; |
90 |
struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
|
91 |
|
92 |
void gsi_handler(void *opaque, int n, int level) |
93 |
{ |
94 |
GSIState *s = opaque; |
95 |
|
96 |
DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
97 |
if (n < ISA_NUM_IRQS) {
|
98 |
qemu_set_irq(s->i8259_irq[n], level); |
99 |
} |
100 |
qemu_set_irq(s->ioapic_irq[n], level); |
101 |
} |
102 |
|
103 |
static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
104 |
{ |
105 |
} |
106 |
|
107 |
/* MSDOS compatibility mode FPU exception support */
|
108 |
static qemu_irq ferr_irq;
|
109 |
|
110 |
void pc_register_ferr_irq(qemu_irq irq)
|
111 |
{ |
112 |
ferr_irq = irq; |
113 |
} |
114 |
|
115 |
/* XXX: add IGNNE support */
|
116 |
void cpu_set_ferr(CPUX86State *s)
|
117 |
{ |
118 |
qemu_irq_raise(ferr_irq); |
119 |
} |
120 |
|
121 |
static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) |
122 |
{ |
123 |
qemu_irq_lower(ferr_irq); |
124 |
} |
125 |
|
126 |
/* TSC handling */
|
127 |
uint64_t cpu_get_tsc(CPUX86State *env) |
128 |
{ |
129 |
return cpu_get_ticks();
|
130 |
} |
131 |
|
132 |
/* SMM support */
|
133 |
|
134 |
static cpu_set_smm_t smm_set;
|
135 |
static void *smm_arg; |
136 |
|
137 |
void cpu_smm_register(cpu_set_smm_t callback, void *arg) |
138 |
{ |
139 |
assert(smm_set == NULL);
|
140 |
assert(smm_arg == NULL);
|
141 |
smm_set = callback; |
142 |
smm_arg = arg; |
143 |
} |
144 |
|
145 |
void cpu_smm_update(CPUX86State *env)
|
146 |
{ |
147 |
if (smm_set && smm_arg && env == first_cpu)
|
148 |
smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); |
149 |
} |
150 |
|
151 |
|
152 |
/* IRQ handling */
|
153 |
int cpu_get_pic_interrupt(CPUX86State *env)
|
154 |
{ |
155 |
int intno;
|
156 |
|
157 |
intno = apic_get_interrupt(env->apic_state); |
158 |
if (intno >= 0) { |
159 |
return intno;
|
160 |
} |
161 |
/* read the irq from the PIC */
|
162 |
if (!apic_accept_pic_intr(env->apic_state)) {
|
163 |
return -1; |
164 |
} |
165 |
|
166 |
intno = pic_read_irq(isa_pic); |
167 |
return intno;
|
168 |
} |
169 |
|
170 |
static void pic_irq_request(void *opaque, int irq, int level) |
171 |
{ |
172 |
CPUX86State *env = first_cpu; |
173 |
|
174 |
DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
175 |
if (env->apic_state) {
|
176 |
while (env) {
|
177 |
if (apic_accept_pic_intr(env->apic_state)) {
|
178 |
apic_deliver_pic_intr(env->apic_state, level); |
179 |
} |
180 |
env = env->next_cpu; |
181 |
} |
182 |
} else {
|
183 |
if (level)
|
184 |
cpu_interrupt(env, CPU_INTERRUPT_HARD); |
185 |
else
|
186 |
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
187 |
} |
188 |
} |
189 |
|
190 |
/* PC cmos mappings */
|
191 |
|
192 |
#define REG_EQUIPMENT_BYTE 0x14 |
193 |
|
194 |
static int cmos_get_fd_drive_type(FDriveType fd0) |
195 |
{ |
196 |
int val;
|
197 |
|
198 |
switch (fd0) {
|
199 |
case FDRIVE_DRV_144:
|
200 |
/* 1.44 Mb 3"5 drive */
|
201 |
val = 4;
|
202 |
break;
|
203 |
case FDRIVE_DRV_288:
|
204 |
/* 2.88 Mb 3"5 drive */
|
205 |
val = 5;
|
206 |
break;
|
207 |
case FDRIVE_DRV_120:
|
208 |
/* 1.2 Mb 5"5 drive */
|
209 |
val = 2;
|
210 |
break;
|
211 |
case FDRIVE_DRV_NONE:
|
212 |
default:
|
213 |
val = 0;
|
214 |
break;
|
215 |
} |
216 |
return val;
|
217 |
} |
218 |
|
219 |
static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
220 |
int16_t cylinders, int8_t heads, int8_t sectors) |
221 |
{ |
222 |
rtc_set_memory(s, type_ofs, 47);
|
223 |
rtc_set_memory(s, info_ofs, cylinders); |
224 |
rtc_set_memory(s, info_ofs + 1, cylinders >> 8); |
225 |
rtc_set_memory(s, info_ofs + 2, heads);
|
226 |
rtc_set_memory(s, info_ofs + 3, 0xff); |
227 |
rtc_set_memory(s, info_ofs + 4, 0xff); |
228 |
rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); |
229 |
rtc_set_memory(s, info_ofs + 6, cylinders);
|
230 |
rtc_set_memory(s, info_ofs + 7, cylinders >> 8); |
231 |
rtc_set_memory(s, info_ofs + 8, sectors);
|
232 |
} |
233 |
|
234 |
/* convert boot_device letter to something recognizable by the bios */
|
235 |
static int boot_device2nibble(char boot_device) |
236 |
{ |
237 |
switch(boot_device) {
|
238 |
case 'a': |
239 |
case 'b': |
240 |
return 0x01; /* floppy boot */ |
241 |
case 'c': |
242 |
return 0x02; /* hard drive boot */ |
243 |
case 'd': |
244 |
return 0x03; /* CD-ROM boot */ |
245 |
case 'n': |
246 |
return 0x04; /* Network boot */ |
247 |
} |
248 |
return 0; |
249 |
} |
250 |
|
251 |
static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk) |
252 |
{ |
253 |
#define PC_MAX_BOOT_DEVICES 3 |
254 |
int nbds, bds[3] = { 0, }; |
255 |
int i;
|
256 |
|
257 |
nbds = strlen(boot_device); |
258 |
if (nbds > PC_MAX_BOOT_DEVICES) {
|
259 |
error_report("Too many boot devices for PC");
|
260 |
return(1); |
261 |
} |
262 |
for (i = 0; i < nbds; i++) { |
263 |
bds[i] = boot_device2nibble(boot_device[i]); |
264 |
if (bds[i] == 0) { |
265 |
error_report("Invalid boot device for PC: '%c'",
|
266 |
boot_device[i]); |
267 |
return(1); |
268 |
} |
269 |
} |
270 |
rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
271 |
rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
272 |
return(0); |
273 |
} |
274 |
|
275 |
static int pc_boot_set(void *opaque, const char *boot_device) |
276 |
{ |
277 |
return set_boot_dev(opaque, boot_device, 0); |
278 |
} |
279 |
|
280 |
typedef struct pc_cmos_init_late_arg { |
281 |
ISADevice *rtc_state; |
282 |
BusState *idebus[2];
|
283 |
} pc_cmos_init_late_arg; |
284 |
|
285 |
static void pc_cmos_init_late(void *opaque) |
286 |
{ |
287 |
pc_cmos_init_late_arg *arg = opaque; |
288 |
ISADevice *s = arg->rtc_state; |
289 |
int16_t cylinders; |
290 |
int8_t heads, sectors; |
291 |
int val;
|
292 |
int i, trans;
|
293 |
|
294 |
val = 0;
|
295 |
if (ide_get_geometry(arg->idebus[0], 0, |
296 |
&cylinders, &heads, §ors) >= 0) {
|
297 |
cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); |
298 |
val |= 0xf0;
|
299 |
} |
300 |
if (ide_get_geometry(arg->idebus[0], 1, |
301 |
&cylinders, &heads, §ors) >= 0) {
|
302 |
cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); |
303 |
val |= 0x0f;
|
304 |
} |
305 |
rtc_set_memory(s, 0x12, val);
|
306 |
|
307 |
val = 0;
|
308 |
for (i = 0; i < 4; i++) { |
309 |
/* NOTE: ide_get_geometry() returns the physical
|
310 |
geometry. It is always such that: 1 <= sects <= 63, 1
|
311 |
<= heads <= 16, 1 <= cylinders <= 16383. The BIOS
|
312 |
geometry can be different if a translation is done. */
|
313 |
if (ide_get_geometry(arg->idebus[i / 2], i % 2, |
314 |
&cylinders, &heads, §ors) >= 0) {
|
315 |
trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
316 |
assert((trans & ~3) == 0); |
317 |
val |= trans << (i * 2);
|
318 |
} |
319 |
} |
320 |
rtc_set_memory(s, 0x39, val);
|
321 |
|
322 |
qemu_unregister_reset(pc_cmos_init_late, opaque); |
323 |
} |
324 |
|
325 |
void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
|
326 |
const char *boot_device, |
327 |
ISADevice *floppy, BusState *idebus0, BusState *idebus1, |
328 |
ISADevice *s) |
329 |
{ |
330 |
int val, nb, i;
|
331 |
FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
|
332 |
static pc_cmos_init_late_arg arg;
|
333 |
|
334 |
/* various important CMOS locations needed by PC/Bochs bios */
|
335 |
|
336 |
/* memory size */
|
337 |
/* base memory (first MiB) */
|
338 |
val = MIN(ram_size / 1024, 640); |
339 |
rtc_set_memory(s, 0x15, val);
|
340 |
rtc_set_memory(s, 0x16, val >> 8); |
341 |
/* extended memory (next 64MiB) */
|
342 |
if (ram_size > 1024 * 1024) { |
343 |
val = (ram_size - 1024 * 1024) / 1024; |
344 |
} else {
|
345 |
val = 0;
|
346 |
} |
347 |
if (val > 65535) |
348 |
val = 65535;
|
349 |
rtc_set_memory(s, 0x17, val);
|
350 |
rtc_set_memory(s, 0x18, val >> 8); |
351 |
rtc_set_memory(s, 0x30, val);
|
352 |
rtc_set_memory(s, 0x31, val >> 8); |
353 |
/* memory between 16MiB and 4GiB */
|
354 |
if (ram_size > 16 * 1024 * 1024) { |
355 |
val = (ram_size - 16 * 1024 * 1024) / 65536; |
356 |
} else {
|
357 |
val = 0;
|
358 |
} |
359 |
if (val > 65535) |
360 |
val = 65535;
|
361 |
rtc_set_memory(s, 0x34, val);
|
362 |
rtc_set_memory(s, 0x35, val >> 8); |
363 |
/* memory above 4GiB */
|
364 |
val = above_4g_mem_size / 65536;
|
365 |
rtc_set_memory(s, 0x5b, val);
|
366 |
rtc_set_memory(s, 0x5c, val >> 8); |
367 |
rtc_set_memory(s, 0x5d, val >> 16); |
368 |
|
369 |
/* set the number of CPU */
|
370 |
rtc_set_memory(s, 0x5f, smp_cpus - 1); |
371 |
|
372 |
/* set boot devices, and disable floppy signature check if requested */
|
373 |
if (set_boot_dev(s, boot_device, fd_bootchk)) {
|
374 |
exit(1);
|
375 |
} |
376 |
|
377 |
/* floppy type */
|
378 |
if (floppy) {
|
379 |
for (i = 0; i < 2; i++) { |
380 |
fd_type[i] = isa_fdc_get_drive_type(floppy, i); |
381 |
} |
382 |
} |
383 |
val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | |
384 |
cmos_get_fd_drive_type(fd_type[1]);
|
385 |
rtc_set_memory(s, 0x10, val);
|
386 |
|
387 |
val = 0;
|
388 |
nb = 0;
|
389 |
if (fd_type[0] < FDRIVE_DRV_NONE) { |
390 |
nb++; |
391 |
} |
392 |
if (fd_type[1] < FDRIVE_DRV_NONE) { |
393 |
nb++; |
394 |
} |
395 |
switch (nb) {
|
396 |
case 0: |
397 |
break;
|
398 |
case 1: |
399 |
val |= 0x01; /* 1 drive, ready for boot */ |
400 |
break;
|
401 |
case 2: |
402 |
val |= 0x41; /* 2 drives, ready for boot */ |
403 |
break;
|
404 |
} |
405 |
val |= 0x02; /* FPU is there */ |
406 |
val |= 0x04; /* PS/2 mouse installed */ |
407 |
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); |
408 |
|
409 |
/* hard drives */
|
410 |
arg.rtc_state = s; |
411 |
arg.idebus[0] = idebus0;
|
412 |
arg.idebus[1] = idebus1;
|
413 |
qemu_register_reset(pc_cmos_init_late, &arg); |
414 |
} |
415 |
|
416 |
/* port 92 stuff: could be split off */
|
417 |
typedef struct Port92State { |
418 |
ISADevice dev; |
419 |
MemoryRegion io; |
420 |
uint8_t outport; |
421 |
qemu_irq *a20_out; |
422 |
} Port92State; |
423 |
|
424 |
static void port92_write(void *opaque, uint32_t addr, uint32_t val) |
425 |
{ |
426 |
Port92State *s = opaque; |
427 |
|
428 |
DPRINTF("port92: write 0x%02x\n", val);
|
429 |
s->outport = val; |
430 |
qemu_set_irq(*s->a20_out, (val >> 1) & 1); |
431 |
if (val & 1) { |
432 |
qemu_system_reset_request(); |
433 |
} |
434 |
} |
435 |
|
436 |
static uint32_t port92_read(void *opaque, uint32_t addr) |
437 |
{ |
438 |
Port92State *s = opaque; |
439 |
uint32_t ret; |
440 |
|
441 |
ret = s->outport; |
442 |
DPRINTF("port92: read 0x%02x\n", ret);
|
443 |
return ret;
|
444 |
} |
445 |
|
446 |
static void port92_init(ISADevice *dev, qemu_irq *a20_out) |
447 |
{ |
448 |
Port92State *s = DO_UPCAST(Port92State, dev, dev); |
449 |
|
450 |
s->a20_out = a20_out; |
451 |
} |
452 |
|
453 |
static const VMStateDescription vmstate_port92_isa = { |
454 |
.name = "port92",
|
455 |
.version_id = 1,
|
456 |
.minimum_version_id = 1,
|
457 |
.minimum_version_id_old = 1,
|
458 |
.fields = (VMStateField []) { |
459 |
VMSTATE_UINT8(outport, Port92State), |
460 |
VMSTATE_END_OF_LIST() |
461 |
} |
462 |
}; |
463 |
|
464 |
static void port92_reset(DeviceState *d) |
465 |
{ |
466 |
Port92State *s = container_of(d, Port92State, dev.qdev); |
467 |
|
468 |
s->outport &= ~1;
|
469 |
} |
470 |
|
471 |
static const MemoryRegionPortio port92_portio[] = { |
472 |
{ 0, 1, 1, .read = port92_read, .write = port92_write }, |
473 |
PORTIO_END_OF_LIST(), |
474 |
}; |
475 |
|
476 |
static const MemoryRegionOps port92_ops = { |
477 |
.old_portio = port92_portio |
478 |
}; |
479 |
|
480 |
static int port92_initfn(ISADevice *dev) |
481 |
{ |
482 |
Port92State *s = DO_UPCAST(Port92State, dev, dev); |
483 |
|
484 |
memory_region_init_io(&s->io, &port92_ops, s, "port92", 1); |
485 |
isa_register_ioport(dev, &s->io, 0x92);
|
486 |
|
487 |
s->outport = 0;
|
488 |
return 0; |
489 |
} |
490 |
|
491 |
static void port92_class_initfn(ObjectClass *klass, void *data) |
492 |
{ |
493 |
DeviceClass *dc = DEVICE_CLASS(klass); |
494 |
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
495 |
ic->init = port92_initfn; |
496 |
dc->no_user = 1;
|
497 |
dc->reset = port92_reset; |
498 |
dc->vmsd = &vmstate_port92_isa; |
499 |
} |
500 |
|
501 |
static TypeInfo port92_info = {
|
502 |
.name = "port92",
|
503 |
.parent = TYPE_ISA_DEVICE, |
504 |
.instance_size = sizeof(Port92State),
|
505 |
.class_init = port92_class_initfn, |
506 |
}; |
507 |
|
508 |
static void port92_register_types(void) |
509 |
{ |
510 |
type_register_static(&port92_info); |
511 |
} |
512 |
|
513 |
type_init(port92_register_types) |
514 |
|
515 |
static void handle_a20_line_change(void *opaque, int irq, int level) |
516 |
{ |
517 |
CPUX86State *cpu = opaque; |
518 |
|
519 |
/* XXX: send to all CPUs ? */
|
520 |
/* XXX: add logic to handle multiple A20 line sources */
|
521 |
cpu_x86_set_a20(cpu, level); |
522 |
} |
523 |
|
524 |
/***********************************************************/
|
525 |
/* Bochs BIOS debug ports */
|
526 |
|
527 |
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
528 |
{ |
529 |
static const char shutdown_str[8] = "Shutdown"; |
530 |
static int shutdown_index = 0; |
531 |
|
532 |
switch(addr) {
|
533 |
case 0x8900: |
534 |
/* same as Bochs power off */
|
535 |
if (val == shutdown_str[shutdown_index]) {
|
536 |
shutdown_index++; |
537 |
if (shutdown_index == 8) { |
538 |
shutdown_index = 0;
|
539 |
qemu_system_shutdown_request(); |
540 |
} |
541 |
} else {
|
542 |
shutdown_index = 0;
|
543 |
} |
544 |
break;
|
545 |
|
546 |
case 0x501: |
547 |
case 0x502: |
548 |
exit((val << 1) | 1); |
549 |
} |
550 |
} |
551 |
|
552 |
int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
|
553 |
{ |
554 |
int index = le32_to_cpu(e820_table.count);
|
555 |
struct e820_entry *entry;
|
556 |
|
557 |
if (index >= E820_NR_ENTRIES)
|
558 |
return -EBUSY;
|
559 |
entry = &e820_table.entry[index++]; |
560 |
|
561 |
entry->address = cpu_to_le64(address); |
562 |
entry->length = cpu_to_le64(length); |
563 |
entry->type = cpu_to_le32(type); |
564 |
|
565 |
e820_table.count = cpu_to_le32(index); |
566 |
return index;
|
567 |
} |
568 |
|
569 |
static void *bochs_bios_init(void) |
570 |
{ |
571 |
void *fw_cfg;
|
572 |
uint8_t *smbios_table; |
573 |
size_t smbios_len; |
574 |
uint64_t *numa_fw_cfg; |
575 |
int i, j;
|
576 |
|
577 |
register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
578 |
|
579 |
register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL); |
580 |
register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
581 |
register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); |
582 |
|
583 |
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
584 |
|
585 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
586 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
587 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
588 |
acpi_tables_len); |
589 |
fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); |
590 |
|
591 |
smbios_table = smbios_get_table(&smbios_len); |
592 |
if (smbios_table)
|
593 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
594 |
smbios_table, smbios_len); |
595 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table, |
596 |
sizeof(struct e820_table)); |
597 |
|
598 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg, |
599 |
sizeof(struct hpet_fw_config)); |
600 |
/* allocate memory for the NUMA channel: one (64bit) word for the number
|
601 |
* of nodes, one word for each VCPU->node and one word for each node to
|
602 |
* hold the amount of memory.
|
603 |
*/
|
604 |
numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8); |
605 |
numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
|
606 |
for (i = 0; i < max_cpus; i++) { |
607 |
for (j = 0; j < nb_numa_nodes; j++) { |
608 |
if (test_bit(i, node_cpumask[j])) {
|
609 |
numa_fw_cfg[i + 1] = cpu_to_le64(j);
|
610 |
break;
|
611 |
} |
612 |
} |
613 |
} |
614 |
for (i = 0; i < nb_numa_nodes; i++) { |
615 |
numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
|
616 |
} |
617 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, |
618 |
(1 + max_cpus + nb_numa_nodes) * 8); |
619 |
|
620 |
return fw_cfg;
|
621 |
} |
622 |
|
623 |
static long get_file_size(FILE *f) |
624 |
{ |
625 |
long where, size;
|
626 |
|
627 |
/* XXX: on Unix systems, using fstat() probably makes more sense */
|
628 |
|
629 |
where = ftell(f); |
630 |
fseek(f, 0, SEEK_END);
|
631 |
size = ftell(f); |
632 |
fseek(f, where, SEEK_SET); |
633 |
|
634 |
return size;
|
635 |
} |
636 |
|
637 |
static void load_linux(void *fw_cfg, |
638 |
const char *kernel_filename, |
639 |
const char *initrd_filename, |
640 |
const char *kernel_cmdline, |
641 |
hwaddr max_ram_size) |
642 |
{ |
643 |
uint16_t protocol; |
644 |
int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
645 |
uint32_t initrd_max; |
646 |
uint8_t header[8192], *setup, *kernel, *initrd_data;
|
647 |
hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
|
648 |
FILE *f; |
649 |
char *vmode;
|
650 |
|
651 |
/* Align to 16 bytes as a paranoia measure */
|
652 |
cmdline_size = (strlen(kernel_cmdline)+16) & ~15; |
653 |
|
654 |
/* load the kernel header */
|
655 |
f = fopen(kernel_filename, "rb");
|
656 |
if (!f || !(kernel_size = get_file_size(f)) ||
|
657 |
fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
|
658 |
MIN(ARRAY_SIZE(header), kernel_size)) { |
659 |
fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
|
660 |
kernel_filename, strerror(errno)); |
661 |
exit(1);
|
662 |
} |
663 |
|
664 |
/* kernel protocol version */
|
665 |
#if 0
|
666 |
fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
|
667 |
#endif
|
668 |
if (ldl_p(header+0x202) == 0x53726448) |
669 |
protocol = lduw_p(header+0x206);
|
670 |
else {
|
671 |
/* This looks like a multiboot kernel. If it is, let's stop
|
672 |
treating it like a Linux kernel. */
|
673 |
if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
|
674 |
kernel_cmdline, kernel_size, header)) |
675 |
return;
|
676 |
protocol = 0;
|
677 |
} |
678 |
|
679 |
if (protocol < 0x200 || !(header[0x211] & 0x01)) { |
680 |
/* Low kernel */
|
681 |
real_addr = 0x90000;
|
682 |
cmdline_addr = 0x9a000 - cmdline_size;
|
683 |
prot_addr = 0x10000;
|
684 |
} else if (protocol < 0x202) { |
685 |
/* High but ancient kernel */
|
686 |
real_addr = 0x90000;
|
687 |
cmdline_addr = 0x9a000 - cmdline_size;
|
688 |
prot_addr = 0x100000;
|
689 |
} else {
|
690 |
/* High and recent kernel */
|
691 |
real_addr = 0x10000;
|
692 |
cmdline_addr = 0x20000;
|
693 |
prot_addr = 0x100000;
|
694 |
} |
695 |
|
696 |
#if 0
|
697 |
fprintf(stderr,
|
698 |
"qemu: real_addr = 0x" TARGET_FMT_plx "\n"
|
699 |
"qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
|
700 |
"qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
|
701 |
real_addr,
|
702 |
cmdline_addr,
|
703 |
prot_addr);
|
704 |
#endif
|
705 |
|
706 |
/* highest address for loading the initrd */
|
707 |
if (protocol >= 0x203) |
708 |
initrd_max = ldl_p(header+0x22c);
|
709 |
else
|
710 |
initrd_max = 0x37ffffff;
|
711 |
|
712 |
if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
|
713 |
initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
|
714 |
|
715 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
716 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
|
717 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
718 |
(uint8_t*)strdup(kernel_cmdline), |
719 |
strlen(kernel_cmdline)+1);
|
720 |
|
721 |
if (protocol >= 0x202) { |
722 |
stl_p(header+0x228, cmdline_addr);
|
723 |
} else {
|
724 |
stw_p(header+0x20, 0xA33F); |
725 |
stw_p(header+0x22, cmdline_addr-real_addr);
|
726 |
} |
727 |
|
728 |
/* handle vga= parameter */
|
729 |
vmode = strstr(kernel_cmdline, "vga=");
|
730 |
if (vmode) {
|
731 |
unsigned int video_mode; |
732 |
/* skip "vga=" */
|
733 |
vmode += 4;
|
734 |
if (!strncmp(vmode, "normal", 6)) { |
735 |
video_mode = 0xffff;
|
736 |
} else if (!strncmp(vmode, "ext", 3)) { |
737 |
video_mode = 0xfffe;
|
738 |
} else if (!strncmp(vmode, "ask", 3)) { |
739 |
video_mode = 0xfffd;
|
740 |
} else {
|
741 |
video_mode = strtol(vmode, NULL, 0); |
742 |
} |
743 |
stw_p(header+0x1fa, video_mode);
|
744 |
} |
745 |
|
746 |
/* loader type */
|
747 |
/* High nybble = B reserved for QEMU; low nybble is revision number.
|
748 |
If this code is substantially changed, you may want to consider
|
749 |
incrementing the revision. */
|
750 |
if (protocol >= 0x200) |
751 |
header[0x210] = 0xB0; |
752 |
|
753 |
/* heap */
|
754 |
if (protocol >= 0x201) { |
755 |
header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
756 |
stw_p(header+0x224, cmdline_addr-real_addr-0x200); |
757 |
} |
758 |
|
759 |
/* load initrd */
|
760 |
if (initrd_filename) {
|
761 |
if (protocol < 0x200) { |
762 |
fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
|
763 |
exit(1);
|
764 |
} |
765 |
|
766 |
initrd_size = get_image_size(initrd_filename); |
767 |
if (initrd_size < 0) { |
768 |
fprintf(stderr, "qemu: error reading initrd %s\n",
|
769 |
initrd_filename); |
770 |
exit(1);
|
771 |
} |
772 |
|
773 |
initrd_addr = (initrd_max-initrd_size) & ~4095;
|
774 |
|
775 |
initrd_data = g_malloc(initrd_size); |
776 |
load_image(initrd_filename, initrd_data); |
777 |
|
778 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
779 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
780 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); |
781 |
|
782 |
stl_p(header+0x218, initrd_addr);
|
783 |
stl_p(header+0x21c, initrd_size);
|
784 |
} |
785 |
|
786 |
/* load kernel and setup */
|
787 |
setup_size = header[0x1f1];
|
788 |
if (setup_size == 0) |
789 |
setup_size = 4;
|
790 |
setup_size = (setup_size+1)*512; |
791 |
kernel_size -= setup_size; |
792 |
|
793 |
setup = g_malloc(setup_size); |
794 |
kernel = g_malloc(kernel_size); |
795 |
fseek(f, 0, SEEK_SET);
|
796 |
if (fread(setup, 1, setup_size, f) != setup_size) { |
797 |
fprintf(stderr, "fread() failed\n");
|
798 |
exit(1);
|
799 |
} |
800 |
if (fread(kernel, 1, kernel_size, f) != kernel_size) { |
801 |
fprintf(stderr, "fread() failed\n");
|
802 |
exit(1);
|
803 |
} |
804 |
fclose(f); |
805 |
memcpy(setup, header, MIN(sizeof(header), setup_size));
|
806 |
|
807 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); |
808 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
809 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); |
810 |
|
811 |
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); |
812 |
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); |
813 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); |
814 |
|
815 |
option_rom[nb_option_roms].name = "linuxboot.bin";
|
816 |
option_rom[nb_option_roms].bootindex = 0;
|
817 |
nb_option_roms++; |
818 |
} |
819 |
|
820 |
#define NE2000_NB_MAX 6 |
821 |
|
822 |
static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
823 |
0x280, 0x380 }; |
824 |
static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
825 |
|
826 |
static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
827 |
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
828 |
|
829 |
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
|
830 |
{ |
831 |
static int nb_ne2k = 0; |
832 |
|
833 |
if (nb_ne2k == NE2000_NB_MAX)
|
834 |
return;
|
835 |
isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
836 |
ne2000_irq[nb_ne2k], nd); |
837 |
nb_ne2k++; |
838 |
} |
839 |
|
840 |
DeviceState *cpu_get_current_apic(void)
|
841 |
{ |
842 |
if (cpu_single_env) {
|
843 |
return cpu_single_env->apic_state;
|
844 |
} else {
|
845 |
return NULL; |
846 |
} |
847 |
} |
848 |
|
849 |
static DeviceState *apic_init(void *env, uint8_t apic_id) |
850 |
{ |
851 |
DeviceState *dev; |
852 |
static int apic_mapped; |
853 |
|
854 |
if (kvm_irqchip_in_kernel()) {
|
855 |
dev = qdev_create(NULL, "kvm-apic"); |
856 |
} else if (xen_enabled()) { |
857 |
dev = qdev_create(NULL, "xen-apic"); |
858 |
} else {
|
859 |
dev = qdev_create(NULL, "apic"); |
860 |
} |
861 |
|
862 |
qdev_prop_set_uint8(dev, "id", apic_id);
|
863 |
qdev_prop_set_ptr(dev, "cpu_env", env);
|
864 |
qdev_init_nofail(dev); |
865 |
|
866 |
/* XXX: mapping more APICs at the same memory location */
|
867 |
if (apic_mapped == 0) { |
868 |
/* NOTE: the APIC is directly connected to the CPU - it is not
|
869 |
on the global memory bus. */
|
870 |
/* XXX: what if the base changes? */
|
871 |
sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE);
|
872 |
apic_mapped = 1;
|
873 |
} |
874 |
|
875 |
return dev;
|
876 |
} |
877 |
|
878 |
void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
879 |
{ |
880 |
CPUX86State *s = opaque; |
881 |
|
882 |
if (level) {
|
883 |
cpu_interrupt(s, CPU_INTERRUPT_SMI); |
884 |
} |
885 |
} |
886 |
|
887 |
static X86CPU *pc_new_cpu(const char *cpu_model) |
888 |
{ |
889 |
X86CPU *cpu; |
890 |
CPUX86State *env; |
891 |
|
892 |
cpu = cpu_x86_init(cpu_model); |
893 |
if (cpu == NULL) { |
894 |
fprintf(stderr, "Unable to find x86 CPU definition\n");
|
895 |
exit(1);
|
896 |
} |
897 |
env = &cpu->env; |
898 |
if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { |
899 |
env->apic_state = apic_init(env, env->cpuid_apic_id); |
900 |
} |
901 |
cpu_reset(CPU(cpu)); |
902 |
return cpu;
|
903 |
} |
904 |
|
905 |
void pc_cpus_init(const char *cpu_model) |
906 |
{ |
907 |
int i;
|
908 |
|
909 |
/* init CPUs */
|
910 |
if (cpu_model == NULL) { |
911 |
#ifdef TARGET_X86_64
|
912 |
cpu_model = "qemu64";
|
913 |
#else
|
914 |
cpu_model = "qemu32";
|
915 |
#endif
|
916 |
} |
917 |
|
918 |
for(i = 0; i < smp_cpus; i++) { |
919 |
pc_new_cpu(cpu_model); |
920 |
} |
921 |
} |
922 |
|
923 |
void *pc_memory_init(MemoryRegion *system_memory,
|
924 |
const char *kernel_filename, |
925 |
const char *kernel_cmdline, |
926 |
const char *initrd_filename, |
927 |
ram_addr_t below_4g_mem_size, |
928 |
ram_addr_t above_4g_mem_size, |
929 |
MemoryRegion *rom_memory, |
930 |
MemoryRegion **ram_memory) |
931 |
{ |
932 |
int linux_boot, i;
|
933 |
MemoryRegion *ram, *option_rom_mr; |
934 |
MemoryRegion *ram_below_4g, *ram_above_4g; |
935 |
void *fw_cfg;
|
936 |
|
937 |
linux_boot = (kernel_filename != NULL);
|
938 |
|
939 |
/* Allocate RAM. We allocate it as a single memory region and use
|
940 |
* aliases to address portions of it, mostly for backwards compatibility
|
941 |
* with older qemus that used qemu_ram_alloc().
|
942 |
*/
|
943 |
ram = g_malloc(sizeof(*ram));
|
944 |
memory_region_init_ram(ram, "pc.ram",
|
945 |
below_4g_mem_size + above_4g_mem_size); |
946 |
vmstate_register_ram_global(ram); |
947 |
*ram_memory = ram; |
948 |
ram_below_4g = g_malloc(sizeof(*ram_below_4g));
|
949 |
memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
|
950 |
0, below_4g_mem_size);
|
951 |
memory_region_add_subregion(system_memory, 0, ram_below_4g);
|
952 |
if (above_4g_mem_size > 0) { |
953 |
ram_above_4g = g_malloc(sizeof(*ram_above_4g));
|
954 |
memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
|
955 |
below_4g_mem_size, above_4g_mem_size); |
956 |
memory_region_add_subregion(system_memory, 0x100000000ULL,
|
957 |
ram_above_4g); |
958 |
} |
959 |
|
960 |
|
961 |
/* Initialize PC system firmware */
|
962 |
pc_system_firmware_init(rom_memory); |
963 |
|
964 |
option_rom_mr = g_malloc(sizeof(*option_rom_mr));
|
965 |
memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
|
966 |
vmstate_register_ram_global(option_rom_mr); |
967 |
memory_region_add_subregion_overlap(rom_memory, |
968 |
PC_ROM_MIN_VGA, |
969 |
option_rom_mr, |
970 |
1);
|
971 |
|
972 |
fw_cfg = bochs_bios_init(); |
973 |
rom_set_fw(fw_cfg); |
974 |
|
975 |
if (linux_boot) {
|
976 |
load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
977 |
} |
978 |
|
979 |
for (i = 0; i < nb_option_roms; i++) { |
980 |
rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
981 |
} |
982 |
return fw_cfg;
|
983 |
} |
984 |
|
985 |
qemu_irq *pc_allocate_cpu_irq(void)
|
986 |
{ |
987 |
return qemu_allocate_irqs(pic_irq_request, NULL, 1); |
988 |
} |
989 |
|
990 |
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
991 |
{ |
992 |
DeviceState *dev = NULL;
|
993 |
|
994 |
if (pci_bus) {
|
995 |
PCIDevice *pcidev = pci_vga_init(pci_bus); |
996 |
dev = pcidev ? &pcidev->qdev : NULL;
|
997 |
} else if (isa_bus) { |
998 |
ISADevice *isadev = isa_vga_init(isa_bus); |
999 |
dev = isadev ? &isadev->qdev : NULL;
|
1000 |
} |
1001 |
return dev;
|
1002 |
} |
1003 |
|
1004 |
static void cpu_request_exit(void *opaque, int irq, int level) |
1005 |
{ |
1006 |
CPUX86State *env = cpu_single_env; |
1007 |
|
1008 |
if (env && level) {
|
1009 |
cpu_exit(env); |
1010 |
} |
1011 |
} |
1012 |
|
1013 |
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
|
1014 |
ISADevice **rtc_state, |
1015 |
ISADevice **floppy, |
1016 |
bool no_vmport)
|
1017 |
{ |
1018 |
int i;
|
1019 |
DriveInfo *fd[MAX_FD]; |
1020 |
DeviceState *hpet = NULL;
|
1021 |
int pit_isa_irq = 0; |
1022 |
qemu_irq pit_alt_irq = NULL;
|
1023 |
qemu_irq rtc_irq = NULL;
|
1024 |
qemu_irq *a20_line; |
1025 |
ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
|
1026 |
qemu_irq *cpu_exit_irq; |
1027 |
|
1028 |
register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
1029 |
|
1030 |
register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
1031 |
|
1032 |
/*
|
1033 |
* Check if an HPET shall be created.
|
1034 |
*
|
1035 |
* Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
|
1036 |
* when the HPET wants to take over. Thus we have to disable the latter.
|
1037 |
*/
|
1038 |
if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
|
1039 |
hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); |
1040 |
|
1041 |
if (hpet) {
|
1042 |
for (i = 0; i < GSI_NUM_PINS; i++) { |
1043 |
sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]); |
1044 |
} |
1045 |
pit_isa_irq = -1;
|
1046 |
pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); |
1047 |
rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); |
1048 |
} |
1049 |
} |
1050 |
*rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
|
1051 |
|
1052 |
qemu_register_boot_set(pc_boot_set, *rtc_state); |
1053 |
|
1054 |
if (!xen_enabled()) {
|
1055 |
if (kvm_irqchip_in_kernel()) {
|
1056 |
pit = kvm_pit_init(isa_bus, 0x40);
|
1057 |
} else {
|
1058 |
pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
|
1059 |
} |
1060 |
if (hpet) {
|
1061 |
/* connect PIT to output control line of the HPET */
|
1062 |
qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0)); |
1063 |
} |
1064 |
pcspk_init(isa_bus, pit); |
1065 |
} |
1066 |
|
1067 |
for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
1068 |
if (serial_hds[i]) {
|
1069 |
serial_isa_init(isa_bus, i, serial_hds[i]); |
1070 |
} |
1071 |
} |
1072 |
|
1073 |
for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
1074 |
if (parallel_hds[i]) {
|
1075 |
parallel_init(isa_bus, i, parallel_hds[i]); |
1076 |
} |
1077 |
} |
1078 |
|
1079 |
a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
|
1080 |
i8042 = isa_create_simple(isa_bus, "i8042");
|
1081 |
i8042_setup_a20_line(i8042, &a20_line[0]);
|
1082 |
if (!no_vmport) {
|
1083 |
vmport_init(isa_bus); |
1084 |
vmmouse = isa_try_create(isa_bus, "vmmouse");
|
1085 |
} else {
|
1086 |
vmmouse = NULL;
|
1087 |
} |
1088 |
if (vmmouse) {
|
1089 |
qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
|
1090 |
qdev_init_nofail(&vmmouse->qdev); |
1091 |
} |
1092 |
port92 = isa_create_simple(isa_bus, "port92");
|
1093 |
port92_init(port92, &a20_line[1]);
|
1094 |
|
1095 |
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
1096 |
DMA_init(0, cpu_exit_irq);
|
1097 |
|
1098 |
for(i = 0; i < MAX_FD; i++) { |
1099 |
fd[i] = drive_get(IF_FLOPPY, 0, i);
|
1100 |
} |
1101 |
*floppy = fdctrl_init_isa(isa_bus, fd); |
1102 |
} |
1103 |
|
1104 |
void pc_pci_device_init(PCIBus *pci_bus)
|
1105 |
{ |
1106 |
int max_bus;
|
1107 |
int bus;
|
1108 |
|
1109 |
max_bus = drive_get_max_bus(IF_SCSI); |
1110 |
for (bus = 0; bus <= max_bus; bus++) { |
1111 |
pci_create_simple(pci_bus, -1, "lsi53c895a"); |
1112 |
} |
1113 |
} |