root / hw / pxa2xx.c @ a8170e5e
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/*
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* Intel XScale PXA255/270 processor support.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GPL.
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*/
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|
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#include "sysbus.h" |
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#include "pxa.h" |
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#include "sysemu.h" |
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#include "serial.h" |
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#include "i2c.h" |
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#include "ssi.h" |
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#include "qemu-char.h" |
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#include "blockdev.h" |
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|
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static struct { |
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hwaddr io_base; |
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int irqn;
|
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} pxa255_serial[] = { |
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{ 0x40100000, PXA2XX_PIC_FFUART },
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{ 0x40200000, PXA2XX_PIC_BTUART },
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{ 0x40700000, PXA2XX_PIC_STUART },
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{ 0x41600000, PXA25X_PIC_HWUART },
|
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{ 0, 0 } |
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}, pxa270_serial[] = { |
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{ 0x40100000, PXA2XX_PIC_FFUART },
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{ 0x40200000, PXA2XX_PIC_BTUART },
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{ 0x40700000, PXA2XX_PIC_STUART },
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{ 0, 0 } |
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}; |
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typedef struct PXASSPDef { |
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hwaddr io_base; |
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int irqn;
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} PXASSPDef; |
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|
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#if 0
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static PXASSPDef pxa250_ssp[] = {
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{ 0x41000000, PXA2XX_PIC_SSP },
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{ 0, 0 }
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};
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#endif
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|
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static PXASSPDef pxa255_ssp[] = {
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{ 0x41000000, PXA2XX_PIC_SSP },
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{ 0x41400000, PXA25X_PIC_NSSP },
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{ 0, 0 } |
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}; |
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|
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#if 0
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static PXASSPDef pxa26x_ssp[] = {
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{ 0x41000000, PXA2XX_PIC_SSP },
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{ 0x41400000, PXA25X_PIC_NSSP },
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{ 0x41500000, PXA26X_PIC_ASSP },
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{ 0, 0 }
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};
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#endif
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|
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static PXASSPDef pxa27x_ssp[] = {
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{ 0x41000000, PXA2XX_PIC_SSP },
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{ 0x41700000, PXA27X_PIC_SSP2 },
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{ 0x41900000, PXA2XX_PIC_SSP3 },
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{ 0, 0 } |
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}; |
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|
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#define PMCR 0x00 /* Power Manager Control register */ |
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#define PSSR 0x04 /* Power Manager Sleep Status register */ |
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#define PSPR 0x08 /* Power Manager Scratch-Pad register */ |
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#define PWER 0x0c /* Power Manager Wake-Up Enable register */ |
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#define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ |
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#define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ |
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#define PEDR 0x18 /* Power Manager Edge-Detect Status register */ |
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#define PCFR 0x1c /* Power Manager General Configuration register */ |
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#define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ |
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#define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ |
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#define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ |
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#define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ |
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#define RCSR 0x30 /* Reset Controller Status register */ |
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#define PSLR 0x34 /* Power Manager Sleep Configuration register */ |
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#define PTSR 0x38 /* Power Manager Standby Configuration register */ |
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#define PVCR 0x40 /* Power Manager Voltage Change Control register */ |
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#define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ |
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#define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ |
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#define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ |
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#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ |
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#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ |
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|
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static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, |
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unsigned size)
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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switch (addr) {
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case PMCR ... PCMD31:
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if (addr & 3) |
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goto fail;
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return s->pm_regs[addr >> 2]; |
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default:
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fail:
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
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break;
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} |
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return 0; |
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} |
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|
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static void pxa2xx_pm_write(void *opaque, hwaddr addr, |
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uint64_t value, unsigned size)
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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switch (addr) {
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case PMCR:
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/* Clear the write-one-to-clear bits... */
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s->pm_regs[addr >> 2] &= ~(value & 0x2a); |
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/* ...and set the plain r/w bits */
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s->pm_regs[addr >> 2] &= ~0x15; |
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s->pm_regs[addr >> 2] |= value & 0x15; |
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break;
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|
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case PSSR: /* Read-clean registers */ |
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case RCSR:
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case PKSR:
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s->pm_regs[addr >> 2] &= ~value;
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break;
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|
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default: /* Read-write registers */ |
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if (!(addr & 3)) { |
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s->pm_regs[addr >> 2] = value;
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break;
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} |
135 |
|
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
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break;
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} |
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} |
140 |
|
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static const MemoryRegionOps pxa2xx_pm_ops = { |
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.read = pxa2xx_pm_read, |
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.write = pxa2xx_pm_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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|
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static const VMStateDescription vmstate_pxa2xx_pm = { |
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.name = "pxa2xx_pm",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField[]) { |
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VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define CCCR 0x00 /* Core Clock Configuration register */ |
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#define CKEN 0x04 /* Clock Enable register */ |
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#define OSCC 0x08 /* Oscillator Configuration register */ |
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#define CCSR 0x0c /* Core Clock Status register */ |
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|
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static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, |
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unsigned size)
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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switch (addr) {
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case CCCR:
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case CKEN:
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case OSCC:
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return s->cm_regs[addr >> 2]; |
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case CCSR:
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return s->cm_regs[CCCR >> 2] | (3 << 28); |
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default:
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
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break;
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} |
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return 0; |
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} |
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|
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static void pxa2xx_cm_write(void *opaque, hwaddr addr, |
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uint64_t value, unsigned size)
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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switch (addr) {
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case CCCR:
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case CKEN:
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s->cm_regs[addr >> 2] = value;
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break;
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case OSCC:
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s->cm_regs[addr >> 2] &= ~0x6c; |
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s->cm_regs[addr >> 2] |= value & 0x6e; |
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if ((value >> 1) & 1) /* OON */ |
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s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ |
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break;
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default:
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
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break;
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} |
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} |
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static const MemoryRegionOps pxa2xx_cm_ops = { |
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.read = pxa2xx_cm_read, |
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.write = pxa2xx_cm_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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static const VMStateDescription vmstate_pxa2xx_cm = { |
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.name = "pxa2xx_cm",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField[]) { |
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VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
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VMSTATE_UINT32(clkcfg, PXA2xxState), |
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VMSTATE_UINT32(pmnc, PXA2xxState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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static int pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t *value) |
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{ |
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PXA2xxState *s = (PXA2xxState *)ri->opaque; |
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*value = s->clkcfg; |
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return 0; |
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} |
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static int pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
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{ |
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PXA2xxState *s = (PXA2xxState *)ri->opaque; |
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s->clkcfg = value & 0xf;
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if (value & 2) { |
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printf("%s: CPU frequency change attempt\n", __func__);
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} |
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return 0; |
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} |
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static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
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{ |
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PXA2xxState *s = (PXA2xxState *)ri->opaque; |
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static const char *pwrmode[8] = { |
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"Normal", "Idle", "Deep-idle", "Standby", |
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"Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", |
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}; |
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if (value & 8) { |
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printf("%s: CPU voltage change attempt\n", __func__);
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} |
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switch (value & 7) { |
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case 0: |
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/* Do nothing */
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break;
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case 1: |
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/* Idle */
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if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */ |
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cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT); |
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break;
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} |
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/* Fall through. */
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case 2: |
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/* Deep-Idle */
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cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT); |
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s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ |
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goto message;
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|
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case 3: |
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s->cpu->env.uncached_cpsr = |
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ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
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s->cpu->env.cp15.c1_sys = 0;
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s->cpu->env.cp15.c1_coproc = 0;
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s->cpu->env.cp15.c2_base0 = 0;
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s->cpu->env.cp15.c3 = 0;
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s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ |
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s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ |
286 |
|
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/*
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* The scratch-pad register is almost universally used
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* for storing the return address on suspend. For the
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* lack of a resuming bootloader, perform a jump
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* directly to that address.
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*/
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memset(s->cpu->env.regs, 0, 4 * 15); |
294 |
s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; |
295 |
|
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#if 0
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buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
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cpu_physical_memory_write(0, &buffer, 4);
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buffer = s->pm_regs[PSPR >> 2];
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cpu_physical_memory_write(8, &buffer, 4);
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#endif
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|
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/* Suspend */
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
305 |
|
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goto message;
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|
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default:
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message:
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310 |
printf("%s: machine entered %s mode\n", __func__,
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pwrmode[value & 7]);
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} |
313 |
|
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return 0; |
315 |
} |
316 |
|
317 |
static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri, |
318 |
uint64_t *value) |
319 |
{ |
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PXA2xxState *s = (PXA2xxState *)ri->opaque; |
321 |
*value = s->pmnc; |
322 |
return 0; |
323 |
} |
324 |
|
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static int pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
326 |
uint64_t value) |
327 |
{ |
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PXA2xxState *s = (PXA2xxState *)ri->opaque; |
329 |
s->pmnc = value; |
330 |
return 0; |
331 |
} |
332 |
|
333 |
static int pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri, |
334 |
uint64_t *value) |
335 |
{ |
336 |
PXA2xxState *s = (PXA2xxState *)ri->opaque; |
337 |
if (s->pmnc & 1) { |
338 |
*value = qemu_get_clock_ns(vm_clock); |
339 |
} else {
|
340 |
*value = 0;
|
341 |
} |
342 |
return 0; |
343 |
} |
344 |
|
345 |
static const ARMCPRegInfo pxa_cp_reginfo[] = { |
346 |
/* cp14 crn==1: perf registers */
|
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{ .name = "CPPMNC", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, |
348 |
.access = PL1_RW, |
349 |
.readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, |
350 |
{ .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, |
351 |
.access = PL1_RW, |
352 |
.readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, |
353 |
{ .name = "CPINTEN", .cp = 14, .crn = 1, .crm = 4, .opc1 = 0, .opc2 = 0, |
354 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
355 |
{ .name = "CPFLAG", .cp = 14, .crn = 1, .crm = 5, .opc1 = 0, .opc2 = 0, |
356 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
357 |
{ .name = "CPEVTSEL", .cp = 14, .crn = 1, .crm = 8, .opc1 = 0, .opc2 = 0, |
358 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
359 |
/* cp14 crn==2: performance count registers */
|
360 |
{ .name = "CPPMN0", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
361 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
362 |
{ .name = "CPPMN1", .cp = 14, .crn = 2, .crm = 1, .opc1 = 0, .opc2 = 0, |
363 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
364 |
{ .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, |
365 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
366 |
{ .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, |
367 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
368 |
/* cp14 crn==6: CLKCFG */
|
369 |
{ .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, |
370 |
.access = PL1_RW, |
371 |
.readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, |
372 |
/* cp14 crn==7: PWRMODE */
|
373 |
{ .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, |
374 |
.access = PL1_RW, |
375 |
.readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, |
376 |
REGINFO_SENTINEL |
377 |
}; |
378 |
|
379 |
static void pxa2xx_setup_cp14(PXA2xxState *s) |
380 |
{ |
381 |
define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); |
382 |
} |
383 |
|
384 |
#define MDCNFG 0x00 /* SDRAM Configuration register */ |
385 |
#define MDREFR 0x04 /* SDRAM Refresh Control register */ |
386 |
#define MSC0 0x08 /* Static Memory Control register 0 */ |
387 |
#define MSC1 0x0c /* Static Memory Control register 1 */ |
388 |
#define MSC2 0x10 /* Static Memory Control register 2 */ |
389 |
#define MECR 0x14 /* Expansion Memory Bus Config register */ |
390 |
#define SXCNFG 0x1c /* Synchronous Static Memory Config register */ |
391 |
#define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ |
392 |
#define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ |
393 |
#define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ |
394 |
#define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ |
395 |
#define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ |
396 |
#define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ |
397 |
#define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ |
398 |
#define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ |
399 |
#define ARB_CNTL 0x48 /* Arbiter Control register */ |
400 |
#define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ |
401 |
#define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ |
402 |
#define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ |
403 |
#define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ |
404 |
#define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ |
405 |
#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ |
406 |
#define SA1110 0x64 /* SA-1110 Memory Compatibility register */ |
407 |
|
408 |
static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, |
409 |
unsigned size)
|
410 |
{ |
411 |
PXA2xxState *s = (PXA2xxState *) opaque; |
412 |
|
413 |
switch (addr) {
|
414 |
case MDCNFG ... SA1110:
|
415 |
if ((addr & 3) == 0) |
416 |
return s->mm_regs[addr >> 2]; |
417 |
|
418 |
default:
|
419 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
420 |
break;
|
421 |
} |
422 |
return 0; |
423 |
} |
424 |
|
425 |
static void pxa2xx_mm_write(void *opaque, hwaddr addr, |
426 |
uint64_t value, unsigned size)
|
427 |
{ |
428 |
PXA2xxState *s = (PXA2xxState *) opaque; |
429 |
|
430 |
switch (addr) {
|
431 |
case MDCNFG ... SA1110:
|
432 |
if ((addr & 3) == 0) { |
433 |
s->mm_regs[addr >> 2] = value;
|
434 |
break;
|
435 |
} |
436 |
|
437 |
default:
|
438 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
439 |
break;
|
440 |
} |
441 |
} |
442 |
|
443 |
static const MemoryRegionOps pxa2xx_mm_ops = { |
444 |
.read = pxa2xx_mm_read, |
445 |
.write = pxa2xx_mm_write, |
446 |
.endianness = DEVICE_NATIVE_ENDIAN, |
447 |
}; |
448 |
|
449 |
static const VMStateDescription vmstate_pxa2xx_mm = { |
450 |
.name = "pxa2xx_mm",
|
451 |
.version_id = 0,
|
452 |
.minimum_version_id = 0,
|
453 |
.minimum_version_id_old = 0,
|
454 |
.fields = (VMStateField[]) { |
455 |
VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
|
456 |
VMSTATE_END_OF_LIST() |
457 |
} |
458 |
}; |
459 |
|
460 |
/* Synchronous Serial Ports */
|
461 |
typedef struct { |
462 |
SysBusDevice busdev; |
463 |
MemoryRegion iomem; |
464 |
qemu_irq irq; |
465 |
int enable;
|
466 |
SSIBus *bus; |
467 |
|
468 |
uint32_t sscr[2];
|
469 |
uint32_t sspsp; |
470 |
uint32_t ssto; |
471 |
uint32_t ssitr; |
472 |
uint32_t sssr; |
473 |
uint8_t sstsa; |
474 |
uint8_t ssrsa; |
475 |
uint8_t ssacd; |
476 |
|
477 |
uint32_t rx_fifo[16];
|
478 |
int rx_level;
|
479 |
int rx_start;
|
480 |
} PXA2xxSSPState; |
481 |
|
482 |
#define SSCR0 0x00 /* SSP Control register 0 */ |
483 |
#define SSCR1 0x04 /* SSP Control register 1 */ |
484 |
#define SSSR 0x08 /* SSP Status register */ |
485 |
#define SSITR 0x0c /* SSP Interrupt Test register */ |
486 |
#define SSDR 0x10 /* SSP Data register */ |
487 |
#define SSTO 0x28 /* SSP Time-Out register */ |
488 |
#define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ |
489 |
#define SSTSA 0x30 /* SSP TX Time Slot Active register */ |
490 |
#define SSRSA 0x34 /* SSP RX Time Slot Active register */ |
491 |
#define SSTSS 0x38 /* SSP Time Slot Status register */ |
492 |
#define SSACD 0x3c /* SSP Audio Clock Divider register */ |
493 |
|
494 |
/* Bitfields for above registers */
|
495 |
#define SSCR0_SPI(x) (((x) & 0x30) == 0x00) |
496 |
#define SSCR0_SSP(x) (((x) & 0x30) == 0x10) |
497 |
#define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) |
498 |
#define SSCR0_PSP(x) (((x) & 0x30) == 0x30) |
499 |
#define SSCR0_SSE (1 << 7) |
500 |
#define SSCR0_RIM (1 << 22) |
501 |
#define SSCR0_TIM (1 << 23) |
502 |
#define SSCR0_MOD (1 << 31) |
503 |
#define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) |
504 |
#define SSCR1_RIE (1 << 0) |
505 |
#define SSCR1_TIE (1 << 1) |
506 |
#define SSCR1_LBM (1 << 2) |
507 |
#define SSCR1_MWDS (1 << 5) |
508 |
#define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) |
509 |
#define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) |
510 |
#define SSCR1_EFWR (1 << 14) |
511 |
#define SSCR1_PINTE (1 << 18) |
512 |
#define SSCR1_TINTE (1 << 19) |
513 |
#define SSCR1_RSRE (1 << 20) |
514 |
#define SSCR1_TSRE (1 << 21) |
515 |
#define SSCR1_EBCEI (1 << 29) |
516 |
#define SSITR_INT (7 << 5) |
517 |
#define SSSR_TNF (1 << 2) |
518 |
#define SSSR_RNE (1 << 3) |
519 |
#define SSSR_TFS (1 << 5) |
520 |
#define SSSR_RFS (1 << 6) |
521 |
#define SSSR_ROR (1 << 7) |
522 |
#define SSSR_PINT (1 << 18) |
523 |
#define SSSR_TINT (1 << 19) |
524 |
#define SSSR_EOC (1 << 20) |
525 |
#define SSSR_TUR (1 << 21) |
526 |
#define SSSR_BCE (1 << 23) |
527 |
#define SSSR_RW 0x00bc0080 |
528 |
|
529 |
static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) |
530 |
{ |
531 |
int level = 0; |
532 |
|
533 |
level |= s->ssitr & SSITR_INT; |
534 |
level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
|
535 |
level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
|
536 |
level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); |
537 |
level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
|
538 |
level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
|
539 |
level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
|
540 |
level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
|
541 |
level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
|
542 |
qemu_set_irq(s->irq, !!level); |
543 |
} |
544 |
|
545 |
static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) |
546 |
{ |
547 |
s->sssr &= ~(0xf << 12); /* Clear RFL */ |
548 |
s->sssr &= ~(0xf << 8); /* Clear TFL */ |
549 |
s->sssr &= ~SSSR_TFS; |
550 |
s->sssr &= ~SSSR_TNF; |
551 |
if (s->enable) {
|
552 |
s->sssr |= ((s->rx_level - 1) & 0xf) << 12; |
553 |
if (s->rx_level >= SSCR1_RFT(s->sscr[1])) |
554 |
s->sssr |= SSSR_RFS; |
555 |
else
|
556 |
s->sssr &= ~SSSR_RFS; |
557 |
if (s->rx_level)
|
558 |
s->sssr |= SSSR_RNE; |
559 |
else
|
560 |
s->sssr &= ~SSSR_RNE; |
561 |
/* TX FIFO is never filled, so it is always in underrun
|
562 |
condition if SSP is enabled */
|
563 |
s->sssr |= SSSR_TFS; |
564 |
s->sssr |= SSSR_TNF; |
565 |
} |
566 |
|
567 |
pxa2xx_ssp_int_update(s); |
568 |
} |
569 |
|
570 |
static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, |
571 |
unsigned size)
|
572 |
{ |
573 |
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
574 |
uint32_t retval; |
575 |
|
576 |
switch (addr) {
|
577 |
case SSCR0:
|
578 |
return s->sscr[0]; |
579 |
case SSCR1:
|
580 |
return s->sscr[1]; |
581 |
case SSPSP:
|
582 |
return s->sspsp;
|
583 |
case SSTO:
|
584 |
return s->ssto;
|
585 |
case SSITR:
|
586 |
return s->ssitr;
|
587 |
case SSSR:
|
588 |
return s->sssr | s->ssitr;
|
589 |
case SSDR:
|
590 |
if (!s->enable)
|
591 |
return 0xffffffff; |
592 |
if (s->rx_level < 1) { |
593 |
printf("%s: SSP Rx Underrun\n", __FUNCTION__);
|
594 |
return 0xffffffff; |
595 |
} |
596 |
s->rx_level --; |
597 |
retval = s->rx_fifo[s->rx_start ++]; |
598 |
s->rx_start &= 0xf;
|
599 |
pxa2xx_ssp_fifo_update(s); |
600 |
return retval;
|
601 |
case SSTSA:
|
602 |
return s->sstsa;
|
603 |
case SSRSA:
|
604 |
return s->ssrsa;
|
605 |
case SSTSS:
|
606 |
return 0; |
607 |
case SSACD:
|
608 |
return s->ssacd;
|
609 |
default:
|
610 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
611 |
break;
|
612 |
} |
613 |
return 0; |
614 |
} |
615 |
|
616 |
static void pxa2xx_ssp_write(void *opaque, hwaddr addr, |
617 |
uint64_t value64, unsigned size)
|
618 |
{ |
619 |
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
620 |
uint32_t value = value64; |
621 |
|
622 |
switch (addr) {
|
623 |
case SSCR0:
|
624 |
s->sscr[0] = value & 0xc7ffffff; |
625 |
s->enable = value & SSCR0_SSE; |
626 |
if (value & SSCR0_MOD)
|
627 |
printf("%s: Attempt to use network mode\n", __FUNCTION__);
|
628 |
if (s->enable && SSCR0_DSS(value) < 4) |
629 |
printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
|
630 |
SSCR0_DSS(value)); |
631 |
if (!(value & SSCR0_SSE)) {
|
632 |
s->sssr = 0;
|
633 |
s->ssitr = 0;
|
634 |
s->rx_level = 0;
|
635 |
} |
636 |
pxa2xx_ssp_fifo_update(s); |
637 |
break;
|
638 |
|
639 |
case SSCR1:
|
640 |
s->sscr[1] = value;
|
641 |
if (value & (SSCR1_LBM | SSCR1_EFWR))
|
642 |
printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
|
643 |
pxa2xx_ssp_fifo_update(s); |
644 |
break;
|
645 |
|
646 |
case SSPSP:
|
647 |
s->sspsp = value; |
648 |
break;
|
649 |
|
650 |
case SSTO:
|
651 |
s->ssto = value; |
652 |
break;
|
653 |
|
654 |
case SSITR:
|
655 |
s->ssitr = value & SSITR_INT; |
656 |
pxa2xx_ssp_int_update(s); |
657 |
break;
|
658 |
|
659 |
case SSSR:
|
660 |
s->sssr &= ~(value & SSSR_RW); |
661 |
pxa2xx_ssp_int_update(s); |
662 |
break;
|
663 |
|
664 |
case SSDR:
|
665 |
if (SSCR0_UWIRE(s->sscr[0])) { |
666 |
if (s->sscr[1] & SSCR1_MWDS) |
667 |
value &= 0xffff;
|
668 |
else
|
669 |
value &= 0xff;
|
670 |
} else
|
671 |
/* Note how 32bits overflow does no harm here */
|
672 |
value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; |
673 |
|
674 |
/* Data goes from here to the Tx FIFO and is shifted out from
|
675 |
* there directly to the slave, no need to buffer it.
|
676 |
*/
|
677 |
if (s->enable) {
|
678 |
uint32_t readval; |
679 |
readval = ssi_transfer(s->bus, value); |
680 |
if (s->rx_level < 0x10) { |
681 |
s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
|
682 |
} else {
|
683 |
s->sssr |= SSSR_ROR; |
684 |
} |
685 |
} |
686 |
pxa2xx_ssp_fifo_update(s); |
687 |
break;
|
688 |
|
689 |
case SSTSA:
|
690 |
s->sstsa = value; |
691 |
break;
|
692 |
|
693 |
case SSRSA:
|
694 |
s->ssrsa = value; |
695 |
break;
|
696 |
|
697 |
case SSACD:
|
698 |
s->ssacd = value; |
699 |
break;
|
700 |
|
701 |
default:
|
702 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
703 |
break;
|
704 |
} |
705 |
} |
706 |
|
707 |
static const MemoryRegionOps pxa2xx_ssp_ops = { |
708 |
.read = pxa2xx_ssp_read, |
709 |
.write = pxa2xx_ssp_write, |
710 |
.endianness = DEVICE_NATIVE_ENDIAN, |
711 |
}; |
712 |
|
713 |
static void pxa2xx_ssp_save(QEMUFile *f, void *opaque) |
714 |
{ |
715 |
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
716 |
int i;
|
717 |
|
718 |
qemu_put_be32(f, s->enable); |
719 |
|
720 |
qemu_put_be32s(f, &s->sscr[0]);
|
721 |
qemu_put_be32s(f, &s->sscr[1]);
|
722 |
qemu_put_be32s(f, &s->sspsp); |
723 |
qemu_put_be32s(f, &s->ssto); |
724 |
qemu_put_be32s(f, &s->ssitr); |
725 |
qemu_put_be32s(f, &s->sssr); |
726 |
qemu_put_8s(f, &s->sstsa); |
727 |
qemu_put_8s(f, &s->ssrsa); |
728 |
qemu_put_8s(f, &s->ssacd); |
729 |
|
730 |
qemu_put_byte(f, s->rx_level); |
731 |
for (i = 0; i < s->rx_level; i ++) |
732 |
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
|
733 |
} |
734 |
|
735 |
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id) |
736 |
{ |
737 |
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
738 |
int i;
|
739 |
|
740 |
s->enable = qemu_get_be32(f); |
741 |
|
742 |
qemu_get_be32s(f, &s->sscr[0]);
|
743 |
qemu_get_be32s(f, &s->sscr[1]);
|
744 |
qemu_get_be32s(f, &s->sspsp); |
745 |
qemu_get_be32s(f, &s->ssto); |
746 |
qemu_get_be32s(f, &s->ssitr); |
747 |
qemu_get_be32s(f, &s->sssr); |
748 |
qemu_get_8s(f, &s->sstsa); |
749 |
qemu_get_8s(f, &s->ssrsa); |
750 |
qemu_get_8s(f, &s->ssacd); |
751 |
|
752 |
s->rx_level = qemu_get_byte(f); |
753 |
s->rx_start = 0;
|
754 |
for (i = 0; i < s->rx_level; i ++) |
755 |
s->rx_fifo[i] = qemu_get_byte(f); |
756 |
|
757 |
return 0; |
758 |
} |
759 |
|
760 |
static int pxa2xx_ssp_init(SysBusDevice *dev) |
761 |
{ |
762 |
PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev); |
763 |
|
764 |
sysbus_init_irq(dev, &s->irq); |
765 |
|
766 |
memory_region_init_io(&s->iomem, &pxa2xx_ssp_ops, s, "pxa2xx-ssp", 0x1000); |
767 |
sysbus_init_mmio(dev, &s->iomem); |
768 |
register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0, |
769 |
pxa2xx_ssp_save, pxa2xx_ssp_load, s); |
770 |
|
771 |
s->bus = ssi_create_bus(&dev->qdev, "ssi");
|
772 |
return 0; |
773 |
} |
774 |
|
775 |
/* Real-Time Clock */
|
776 |
#define RCNR 0x00 /* RTC Counter register */ |
777 |
#define RTAR 0x04 /* RTC Alarm register */ |
778 |
#define RTSR 0x08 /* RTC Status register */ |
779 |
#define RTTR 0x0c /* RTC Timer Trim register */ |
780 |
#define RDCR 0x10 /* RTC Day Counter register */ |
781 |
#define RYCR 0x14 /* RTC Year Counter register */ |
782 |
#define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ |
783 |
#define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ |
784 |
#define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ |
785 |
#define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ |
786 |
#define SWCR 0x28 /* RTC Stopwatch Counter register */ |
787 |
#define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ |
788 |
#define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ |
789 |
#define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ |
790 |
#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ |
791 |
|
792 |
typedef struct { |
793 |
SysBusDevice busdev; |
794 |
MemoryRegion iomem; |
795 |
uint32_t rttr; |
796 |
uint32_t rtsr; |
797 |
uint32_t rtar; |
798 |
uint32_t rdar1; |
799 |
uint32_t rdar2; |
800 |
uint32_t ryar1; |
801 |
uint32_t ryar2; |
802 |
uint32_t swar1; |
803 |
uint32_t swar2; |
804 |
uint32_t piar; |
805 |
uint32_t last_rcnr; |
806 |
uint32_t last_rdcr; |
807 |
uint32_t last_rycr; |
808 |
uint32_t last_swcr; |
809 |
uint32_t last_rtcpicr; |
810 |
int64_t last_hz; |
811 |
int64_t last_sw; |
812 |
int64_t last_pi; |
813 |
QEMUTimer *rtc_hz; |
814 |
QEMUTimer *rtc_rdal1; |
815 |
QEMUTimer *rtc_rdal2; |
816 |
QEMUTimer *rtc_swal1; |
817 |
QEMUTimer *rtc_swal2; |
818 |
QEMUTimer *rtc_pi; |
819 |
qemu_irq rtc_irq; |
820 |
} PXA2xxRTCState; |
821 |
|
822 |
static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) |
823 |
{ |
824 |
qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
|
825 |
} |
826 |
|
827 |
static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) |
828 |
{ |
829 |
int64_t rt = qemu_get_clock_ms(rtc_clock); |
830 |
s->last_rcnr += ((rt - s->last_hz) << 15) /
|
831 |
(1000 * ((s->rttr & 0xffff) + 1)); |
832 |
s->last_rdcr += ((rt - s->last_hz) << 15) /
|
833 |
(1000 * ((s->rttr & 0xffff) + 1)); |
834 |
s->last_hz = rt; |
835 |
} |
836 |
|
837 |
static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) |
838 |
{ |
839 |
int64_t rt = qemu_get_clock_ms(rtc_clock); |
840 |
if (s->rtsr & (1 << 12)) |
841 |
s->last_swcr += (rt - s->last_sw) / 10;
|
842 |
s->last_sw = rt; |
843 |
} |
844 |
|
845 |
static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) |
846 |
{ |
847 |
int64_t rt = qemu_get_clock_ms(rtc_clock); |
848 |
if (s->rtsr & (1 << 15)) |
849 |
s->last_swcr += rt - s->last_pi; |
850 |
s->last_pi = rt; |
851 |
} |
852 |
|
853 |
static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, |
854 |
uint32_t rtsr) |
855 |
{ |
856 |
if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) |
857 |
qemu_mod_timer(s->rtc_hz, s->last_hz + |
858 |
(((s->rtar - s->last_rcnr) * 1000 *
|
859 |
((s->rttr & 0xffff) + 1)) >> 15)); |
860 |
else
|
861 |
qemu_del_timer(s->rtc_hz); |
862 |
|
863 |
if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) |
864 |
qemu_mod_timer(s->rtc_rdal1, s->last_hz + |
865 |
(((s->rdar1 - s->last_rdcr) * 1000 *
|
866 |
((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ |
867 |
else
|
868 |
qemu_del_timer(s->rtc_rdal1); |
869 |
|
870 |
if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) |
871 |
qemu_mod_timer(s->rtc_rdal2, s->last_hz + |
872 |
(((s->rdar2 - s->last_rdcr) * 1000 *
|
873 |
((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ |
874 |
else
|
875 |
qemu_del_timer(s->rtc_rdal2); |
876 |
|
877 |
if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) |
878 |
qemu_mod_timer(s->rtc_swal1, s->last_sw + |
879 |
(s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ |
880 |
else
|
881 |
qemu_del_timer(s->rtc_swal1); |
882 |
|
883 |
if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) |
884 |
qemu_mod_timer(s->rtc_swal2, s->last_sw + |
885 |
(s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ |
886 |
else
|
887 |
qemu_del_timer(s->rtc_swal2); |
888 |
|
889 |
if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) |
890 |
qemu_mod_timer(s->rtc_pi, s->last_pi + |
891 |
(s->piar & 0xffff) - s->last_rtcpicr);
|
892 |
else
|
893 |
qemu_del_timer(s->rtc_pi); |
894 |
} |
895 |
|
896 |
static inline void pxa2xx_rtc_hz_tick(void *opaque) |
897 |
{ |
898 |
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
899 |
s->rtsr |= (1 << 0); |
900 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
901 |
pxa2xx_rtc_int_update(s); |
902 |
} |
903 |
|
904 |
static inline void pxa2xx_rtc_rdal1_tick(void *opaque) |
905 |
{ |
906 |
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
907 |
s->rtsr |= (1 << 4); |
908 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
909 |
pxa2xx_rtc_int_update(s); |
910 |
} |
911 |
|
912 |
static inline void pxa2xx_rtc_rdal2_tick(void *opaque) |
913 |
{ |
914 |
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
915 |
s->rtsr |= (1 << 6); |
916 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
917 |
pxa2xx_rtc_int_update(s); |
918 |
} |
919 |
|
920 |
static inline void pxa2xx_rtc_swal1_tick(void *opaque) |
921 |
{ |
922 |
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
923 |
s->rtsr |= (1 << 8); |
924 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
925 |
pxa2xx_rtc_int_update(s); |
926 |
} |
927 |
|
928 |
static inline void pxa2xx_rtc_swal2_tick(void *opaque) |
929 |
{ |
930 |
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
931 |
s->rtsr |= (1 << 10); |
932 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
933 |
pxa2xx_rtc_int_update(s); |
934 |
} |
935 |
|
936 |
static inline void pxa2xx_rtc_pi_tick(void *opaque) |
937 |
{ |
938 |
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
939 |
s->rtsr |= (1 << 13); |
940 |
pxa2xx_rtc_piupdate(s); |
941 |
s->last_rtcpicr = 0;
|
942 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
943 |
pxa2xx_rtc_int_update(s); |
944 |
} |
945 |
|
946 |
static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, |
947 |
unsigned size)
|
948 |
{ |
949 |
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
950 |
|
951 |
switch (addr) {
|
952 |
case RTTR:
|
953 |
return s->rttr;
|
954 |
case RTSR:
|
955 |
return s->rtsr;
|
956 |
case RTAR:
|
957 |
return s->rtar;
|
958 |
case RDAR1:
|
959 |
return s->rdar1;
|
960 |
case RDAR2:
|
961 |
return s->rdar2;
|
962 |
case RYAR1:
|
963 |
return s->ryar1;
|
964 |
case RYAR2:
|
965 |
return s->ryar2;
|
966 |
case SWAR1:
|
967 |
return s->swar1;
|
968 |
case SWAR2:
|
969 |
return s->swar2;
|
970 |
case PIAR:
|
971 |
return s->piar;
|
972 |
case RCNR:
|
973 |
return s->last_rcnr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / |
974 |
(1000 * ((s->rttr & 0xffff) + 1)); |
975 |
case RDCR:
|
976 |
return s->last_rdcr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / |
977 |
(1000 * ((s->rttr & 0xffff) + 1)); |
978 |
case RYCR:
|
979 |
return s->last_rycr;
|
980 |
case SWCR:
|
981 |
if (s->rtsr & (1 << 12)) |
982 |
return s->last_swcr + (qemu_get_clock_ms(rtc_clock) - s->last_sw) / 10; |
983 |
else
|
984 |
return s->last_swcr;
|
985 |
default:
|
986 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
987 |
break;
|
988 |
} |
989 |
return 0; |
990 |
} |
991 |
|
992 |
static void pxa2xx_rtc_write(void *opaque, hwaddr addr, |
993 |
uint64_t value64, unsigned size)
|
994 |
{ |
995 |
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
996 |
uint32_t value = value64; |
997 |
|
998 |
switch (addr) {
|
999 |
case RTTR:
|
1000 |
if (!(s->rttr & (1 << 31))) { |
1001 |
pxa2xx_rtc_hzupdate(s); |
1002 |
s->rttr = value; |
1003 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1004 |
} |
1005 |
break;
|
1006 |
|
1007 |
case RTSR:
|
1008 |
if ((s->rtsr ^ value) & (1 << 15)) |
1009 |
pxa2xx_rtc_piupdate(s); |
1010 |
|
1011 |
if ((s->rtsr ^ value) & (1 << 12)) |
1012 |
pxa2xx_rtc_swupdate(s); |
1013 |
|
1014 |
if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) |
1015 |
pxa2xx_rtc_alarm_update(s, value); |
1016 |
|
1017 |
s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); |
1018 |
pxa2xx_rtc_int_update(s); |
1019 |
break;
|
1020 |
|
1021 |
case RTAR:
|
1022 |
s->rtar = value; |
1023 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1024 |
break;
|
1025 |
|
1026 |
case RDAR1:
|
1027 |
s->rdar1 = value; |
1028 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1029 |
break;
|
1030 |
|
1031 |
case RDAR2:
|
1032 |
s->rdar2 = value; |
1033 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1034 |
break;
|
1035 |
|
1036 |
case RYAR1:
|
1037 |
s->ryar1 = value; |
1038 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1039 |
break;
|
1040 |
|
1041 |
case RYAR2:
|
1042 |
s->ryar2 = value; |
1043 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1044 |
break;
|
1045 |
|
1046 |
case SWAR1:
|
1047 |
pxa2xx_rtc_swupdate(s); |
1048 |
s->swar1 = value; |
1049 |
s->last_swcr = 0;
|
1050 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1051 |
break;
|
1052 |
|
1053 |
case SWAR2:
|
1054 |
s->swar2 = value; |
1055 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1056 |
break;
|
1057 |
|
1058 |
case PIAR:
|
1059 |
s->piar = value; |
1060 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1061 |
break;
|
1062 |
|
1063 |
case RCNR:
|
1064 |
pxa2xx_rtc_hzupdate(s); |
1065 |
s->last_rcnr = value; |
1066 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1067 |
break;
|
1068 |
|
1069 |
case RDCR:
|
1070 |
pxa2xx_rtc_hzupdate(s); |
1071 |
s->last_rdcr = value; |
1072 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1073 |
break;
|
1074 |
|
1075 |
case RYCR:
|
1076 |
s->last_rycr = value; |
1077 |
break;
|
1078 |
|
1079 |
case SWCR:
|
1080 |
pxa2xx_rtc_swupdate(s); |
1081 |
s->last_swcr = value; |
1082 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1083 |
break;
|
1084 |
|
1085 |
case RTCPICR:
|
1086 |
pxa2xx_rtc_piupdate(s); |
1087 |
s->last_rtcpicr = value & 0xffff;
|
1088 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1089 |
break;
|
1090 |
|
1091 |
default:
|
1092 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1093 |
} |
1094 |
} |
1095 |
|
1096 |
static const MemoryRegionOps pxa2xx_rtc_ops = { |
1097 |
.read = pxa2xx_rtc_read, |
1098 |
.write = pxa2xx_rtc_write, |
1099 |
.endianness = DEVICE_NATIVE_ENDIAN, |
1100 |
}; |
1101 |
|
1102 |
static int pxa2xx_rtc_init(SysBusDevice *dev) |
1103 |
{ |
1104 |
PXA2xxRTCState *s = FROM_SYSBUS(PXA2xxRTCState, dev); |
1105 |
struct tm tm;
|
1106 |
int wom;
|
1107 |
|
1108 |
s->rttr = 0x7fff;
|
1109 |
s->rtsr = 0;
|
1110 |
|
1111 |
qemu_get_timedate(&tm, 0);
|
1112 |
wom = ((tm.tm_mday - 1) / 7) + 1; |
1113 |
|
1114 |
s->last_rcnr = (uint32_t) mktimegm(&tm); |
1115 |
s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | |
1116 |
(tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; |
1117 |
s->last_rycr = ((tm.tm_year + 1900) << 9) | |
1118 |
((tm.tm_mon + 1) << 5) | tm.tm_mday; |
1119 |
s->last_swcr = (tm.tm_hour << 19) |
|
1120 |
(tm.tm_min << 13) | (tm.tm_sec << 7); |
1121 |
s->last_rtcpicr = 0;
|
1122 |
s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rtc_clock); |
1123 |
|
1124 |
s->rtc_hz = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); |
1125 |
s->rtc_rdal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); |
1126 |
s->rtc_rdal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); |
1127 |
s->rtc_swal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); |
1128 |
s->rtc_swal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); |
1129 |
s->rtc_pi = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); |
1130 |
|
1131 |
sysbus_init_irq(dev, &s->rtc_irq); |
1132 |
|
1133 |
memory_region_init_io(&s->iomem, &pxa2xx_rtc_ops, s, "pxa2xx-rtc", 0x10000); |
1134 |
sysbus_init_mmio(dev, &s->iomem); |
1135 |
|
1136 |
return 0; |
1137 |
} |
1138 |
|
1139 |
static void pxa2xx_rtc_pre_save(void *opaque) |
1140 |
{ |
1141 |
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
1142 |
|
1143 |
pxa2xx_rtc_hzupdate(s); |
1144 |
pxa2xx_rtc_piupdate(s); |
1145 |
pxa2xx_rtc_swupdate(s); |
1146 |
} |
1147 |
|
1148 |
static int pxa2xx_rtc_post_load(void *opaque, int version_id) |
1149 |
{ |
1150 |
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
1151 |
|
1152 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1153 |
|
1154 |
return 0; |
1155 |
} |
1156 |
|
1157 |
static const VMStateDescription vmstate_pxa2xx_rtc_regs = { |
1158 |
.name = "pxa2xx_rtc",
|
1159 |
.version_id = 0,
|
1160 |
.minimum_version_id = 0,
|
1161 |
.minimum_version_id_old = 0,
|
1162 |
.pre_save = pxa2xx_rtc_pre_save, |
1163 |
.post_load = pxa2xx_rtc_post_load, |
1164 |
.fields = (VMStateField[]) { |
1165 |
VMSTATE_UINT32(rttr, PXA2xxRTCState), |
1166 |
VMSTATE_UINT32(rtsr, PXA2xxRTCState), |
1167 |
VMSTATE_UINT32(rtar, PXA2xxRTCState), |
1168 |
VMSTATE_UINT32(rdar1, PXA2xxRTCState), |
1169 |
VMSTATE_UINT32(rdar2, PXA2xxRTCState), |
1170 |
VMSTATE_UINT32(ryar1, PXA2xxRTCState), |
1171 |
VMSTATE_UINT32(ryar2, PXA2xxRTCState), |
1172 |
VMSTATE_UINT32(swar1, PXA2xxRTCState), |
1173 |
VMSTATE_UINT32(swar2, PXA2xxRTCState), |
1174 |
VMSTATE_UINT32(piar, PXA2xxRTCState), |
1175 |
VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), |
1176 |
VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), |
1177 |
VMSTATE_UINT32(last_rycr, PXA2xxRTCState), |
1178 |
VMSTATE_UINT32(last_swcr, PXA2xxRTCState), |
1179 |
VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), |
1180 |
VMSTATE_INT64(last_hz, PXA2xxRTCState), |
1181 |
VMSTATE_INT64(last_sw, PXA2xxRTCState), |
1182 |
VMSTATE_INT64(last_pi, PXA2xxRTCState), |
1183 |
VMSTATE_END_OF_LIST(), |
1184 |
}, |
1185 |
}; |
1186 |
|
1187 |
static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) |
1188 |
{ |
1189 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1190 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
1191 |
|
1192 |
k->init = pxa2xx_rtc_init; |
1193 |
dc->desc = "PXA2xx RTC Controller";
|
1194 |
dc->vmsd = &vmstate_pxa2xx_rtc_regs; |
1195 |
} |
1196 |
|
1197 |
static TypeInfo pxa2xx_rtc_sysbus_info = {
|
1198 |
.name = "pxa2xx_rtc",
|
1199 |
.parent = TYPE_SYS_BUS_DEVICE, |
1200 |
.instance_size = sizeof(PXA2xxRTCState),
|
1201 |
.class_init = pxa2xx_rtc_sysbus_class_init, |
1202 |
}; |
1203 |
|
1204 |
/* I2C Interface */
|
1205 |
typedef struct { |
1206 |
I2CSlave i2c; |
1207 |
PXA2xxI2CState *host; |
1208 |
} PXA2xxI2CSlaveState; |
1209 |
|
1210 |
struct PXA2xxI2CState {
|
1211 |
SysBusDevice busdev; |
1212 |
MemoryRegion iomem; |
1213 |
PXA2xxI2CSlaveState *slave; |
1214 |
i2c_bus *bus; |
1215 |
qemu_irq irq; |
1216 |
uint32_t offset; |
1217 |
uint32_t region_size; |
1218 |
|
1219 |
uint16_t control; |
1220 |
uint16_t status; |
1221 |
uint8_t ibmr; |
1222 |
uint8_t data; |
1223 |
}; |
1224 |
|
1225 |
#define IBMR 0x80 /* I2C Bus Monitor register */ |
1226 |
#define IDBR 0x88 /* I2C Data Buffer register */ |
1227 |
#define ICR 0x90 /* I2C Control register */ |
1228 |
#define ISR 0x98 /* I2C Status register */ |
1229 |
#define ISAR 0xa0 /* I2C Slave Address register */ |
1230 |
|
1231 |
static void pxa2xx_i2c_update(PXA2xxI2CState *s) |
1232 |
{ |
1233 |
uint16_t level = 0;
|
1234 |
level |= s->status & s->control & (1 << 10); /* BED */ |
1235 |
level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ |
1236 |
level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ |
1237 |
level |= s->status & (1 << 9); /* SAD */ |
1238 |
qemu_set_irq(s->irq, !!level); |
1239 |
} |
1240 |
|
1241 |
/* These are only stubs now. */
|
1242 |
static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) |
1243 |
{ |
1244 |
PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); |
1245 |
PXA2xxI2CState *s = slave->host; |
1246 |
|
1247 |
switch (event) {
|
1248 |
case I2C_START_SEND:
|
1249 |
s->status |= (1 << 9); /* set SAD */ |
1250 |
s->status &= ~(1 << 0); /* clear RWM */ |
1251 |
break;
|
1252 |
case I2C_START_RECV:
|
1253 |
s->status |= (1 << 9); /* set SAD */ |
1254 |
s->status |= 1 << 0; /* set RWM */ |
1255 |
break;
|
1256 |
case I2C_FINISH:
|
1257 |
s->status |= (1 << 4); /* set SSD */ |
1258 |
break;
|
1259 |
case I2C_NACK:
|
1260 |
s->status |= 1 << 1; /* set ACKNAK */ |
1261 |
break;
|
1262 |
} |
1263 |
pxa2xx_i2c_update(s); |
1264 |
} |
1265 |
|
1266 |
static int pxa2xx_i2c_rx(I2CSlave *i2c) |
1267 |
{ |
1268 |
PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); |
1269 |
PXA2xxI2CState *s = slave->host; |
1270 |
if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) |
1271 |
return 0; |
1272 |
|
1273 |
if (s->status & (1 << 0)) { /* RWM */ |
1274 |
s->status |= 1 << 6; /* set ITE */ |
1275 |
} |
1276 |
pxa2xx_i2c_update(s); |
1277 |
|
1278 |
return s->data;
|
1279 |
} |
1280 |
|
1281 |
static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) |
1282 |
{ |
1283 |
PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); |
1284 |
PXA2xxI2CState *s = slave->host; |
1285 |
if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) |
1286 |
return 1; |
1287 |
|
1288 |
if (!(s->status & (1 << 0))) { /* RWM */ |
1289 |
s->status |= 1 << 7; /* set IRF */ |
1290 |
s->data = data; |
1291 |
} |
1292 |
pxa2xx_i2c_update(s); |
1293 |
|
1294 |
return 1; |
1295 |
} |
1296 |
|
1297 |
static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, |
1298 |
unsigned size)
|
1299 |
{ |
1300 |
PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; |
1301 |
|
1302 |
addr -= s->offset; |
1303 |
switch (addr) {
|
1304 |
case ICR:
|
1305 |
return s->control;
|
1306 |
case ISR:
|
1307 |
return s->status | (i2c_bus_busy(s->bus) << 2); |
1308 |
case ISAR:
|
1309 |
return s->slave->i2c.address;
|
1310 |
case IDBR:
|
1311 |
return s->data;
|
1312 |
case IBMR:
|
1313 |
if (s->status & (1 << 2)) |
1314 |
s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ |
1315 |
else
|
1316 |
s->ibmr = 0;
|
1317 |
return s->ibmr;
|
1318 |
default:
|
1319 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1320 |
break;
|
1321 |
} |
1322 |
return 0; |
1323 |
} |
1324 |
|
1325 |
static void pxa2xx_i2c_write(void *opaque, hwaddr addr, |
1326 |
uint64_t value64, unsigned size)
|
1327 |
{ |
1328 |
PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; |
1329 |
uint32_t value = value64; |
1330 |
int ack;
|
1331 |
|
1332 |
addr -= s->offset; |
1333 |
switch (addr) {
|
1334 |
case ICR:
|
1335 |
s->control = value & 0xfff7;
|
1336 |
if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ |
1337 |
/* TODO: slave mode */
|
1338 |
if (value & (1 << 0)) { /* START condition */ |
1339 |
if (s->data & 1) |
1340 |
s->status |= 1 << 0; /* set RWM */ |
1341 |
else
|
1342 |
s->status &= ~(1 << 0); /* clear RWM */ |
1343 |
ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); |
1344 |
} else {
|
1345 |
if (s->status & (1 << 0)) { /* RWM */ |
1346 |
s->data = i2c_recv(s->bus); |
1347 |
if (value & (1 << 2)) /* ACKNAK */ |
1348 |
i2c_nack(s->bus); |
1349 |
ack = 1;
|
1350 |
} else
|
1351 |
ack = !i2c_send(s->bus, s->data); |
1352 |
} |
1353 |
|
1354 |
if (value & (1 << 1)) /* STOP condition */ |
1355 |
i2c_end_transfer(s->bus); |
1356 |
|
1357 |
if (ack) {
|
1358 |
if (value & (1 << 0)) /* START condition */ |
1359 |
s->status |= 1 << 6; /* set ITE */ |
1360 |
else
|
1361 |
if (s->status & (1 << 0)) /* RWM */ |
1362 |
s->status |= 1 << 7; /* set IRF */ |
1363 |
else
|
1364 |
s->status |= 1 << 6; /* set ITE */ |
1365 |
s->status &= ~(1 << 1); /* clear ACKNAK */ |
1366 |
} else {
|
1367 |
s->status |= 1 << 6; /* set ITE */ |
1368 |
s->status |= 1 << 10; /* set BED */ |
1369 |
s->status |= 1 << 1; /* set ACKNAK */ |
1370 |
} |
1371 |
} |
1372 |
if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ |
1373 |
if (value & (1 << 4)) /* MA */ |
1374 |
i2c_end_transfer(s->bus); |
1375 |
pxa2xx_i2c_update(s); |
1376 |
break;
|
1377 |
|
1378 |
case ISR:
|
1379 |
s->status &= ~(value & 0x07f0);
|
1380 |
pxa2xx_i2c_update(s); |
1381 |
break;
|
1382 |
|
1383 |
case ISAR:
|
1384 |
i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
|
1385 |
break;
|
1386 |
|
1387 |
case IDBR:
|
1388 |
s->data = value & 0xff;
|
1389 |
break;
|
1390 |
|
1391 |
default:
|
1392 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1393 |
} |
1394 |
} |
1395 |
|
1396 |
static const MemoryRegionOps pxa2xx_i2c_ops = { |
1397 |
.read = pxa2xx_i2c_read, |
1398 |
.write = pxa2xx_i2c_write, |
1399 |
.endianness = DEVICE_NATIVE_ENDIAN, |
1400 |
}; |
1401 |
|
1402 |
static const VMStateDescription vmstate_pxa2xx_i2c_slave = { |
1403 |
.name = "pxa2xx_i2c_slave",
|
1404 |
.version_id = 1,
|
1405 |
.minimum_version_id = 1,
|
1406 |
.minimum_version_id_old = 1,
|
1407 |
.fields = (VMStateField []) { |
1408 |
VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState), |
1409 |
VMSTATE_END_OF_LIST() |
1410 |
} |
1411 |
}; |
1412 |
|
1413 |
static const VMStateDescription vmstate_pxa2xx_i2c = { |
1414 |
.name = "pxa2xx_i2c",
|
1415 |
.version_id = 1,
|
1416 |
.minimum_version_id = 1,
|
1417 |
.minimum_version_id_old = 1,
|
1418 |
.fields = (VMStateField []) { |
1419 |
VMSTATE_UINT16(control, PXA2xxI2CState), |
1420 |
VMSTATE_UINT16(status, PXA2xxI2CState), |
1421 |
VMSTATE_UINT8(ibmr, PXA2xxI2CState), |
1422 |
VMSTATE_UINT8(data, PXA2xxI2CState), |
1423 |
VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, |
1424 |
vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *), |
1425 |
VMSTATE_END_OF_LIST() |
1426 |
} |
1427 |
}; |
1428 |
|
1429 |
static int pxa2xx_i2c_slave_init(I2CSlave *i2c) |
1430 |
{ |
1431 |
/* Nothing to do. */
|
1432 |
return 0; |
1433 |
} |
1434 |
|
1435 |
static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) |
1436 |
{ |
1437 |
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); |
1438 |
|
1439 |
k->init = pxa2xx_i2c_slave_init; |
1440 |
k->event = pxa2xx_i2c_event; |
1441 |
k->recv = pxa2xx_i2c_rx; |
1442 |
k->send = pxa2xx_i2c_tx; |
1443 |
} |
1444 |
|
1445 |
static TypeInfo pxa2xx_i2c_slave_info = {
|
1446 |
.name = "pxa2xx-i2c-slave",
|
1447 |
.parent = TYPE_I2C_SLAVE, |
1448 |
.instance_size = sizeof(PXA2xxI2CSlaveState),
|
1449 |
.class_init = pxa2xx_i2c_slave_class_init, |
1450 |
}; |
1451 |
|
1452 |
PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, |
1453 |
qemu_irq irq, uint32_t region_size) |
1454 |
{ |
1455 |
DeviceState *dev; |
1456 |
SysBusDevice *i2c_dev; |
1457 |
PXA2xxI2CState *s; |
1458 |
|
1459 |
i2c_dev = sysbus_from_qdev(qdev_create(NULL, "pxa2xx_i2c")); |
1460 |
qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1); |
1461 |
qdev_prop_set_uint32(&i2c_dev->qdev, "offset", base & region_size);
|
1462 |
|
1463 |
qdev_init_nofail(&i2c_dev->qdev); |
1464 |
|
1465 |
sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
|
1466 |
sysbus_connect_irq(i2c_dev, 0, irq);
|
1467 |
|
1468 |
s = FROM_SYSBUS(PXA2xxI2CState, i2c_dev); |
1469 |
/* FIXME: Should the slave device really be on a separate bus? */
|
1470 |
dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0); |
1471 |
s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev)); |
1472 |
s->slave->host = s; |
1473 |
|
1474 |
return s;
|
1475 |
} |
1476 |
|
1477 |
static int pxa2xx_i2c_initfn(SysBusDevice *dev) |
1478 |
{ |
1479 |
PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev); |
1480 |
|
1481 |
s->bus = i2c_init_bus(&dev->qdev, "i2c");
|
1482 |
|
1483 |
memory_region_init_io(&s->iomem, &pxa2xx_i2c_ops, s, |
1484 |
"pxa2xx-i2x", s->region_size);
|
1485 |
sysbus_init_mmio(dev, &s->iomem); |
1486 |
sysbus_init_irq(dev, &s->irq); |
1487 |
|
1488 |
return 0; |
1489 |
} |
1490 |
|
1491 |
i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s) |
1492 |
{ |
1493 |
return s->bus;
|
1494 |
} |
1495 |
|
1496 |
static Property pxa2xx_i2c_properties[] = {
|
1497 |
DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), |
1498 |
DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), |
1499 |
DEFINE_PROP_END_OF_LIST(), |
1500 |
}; |
1501 |
|
1502 |
static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) |
1503 |
{ |
1504 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1505 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
1506 |
|
1507 |
k->init = pxa2xx_i2c_initfn; |
1508 |
dc->desc = "PXA2xx I2C Bus Controller";
|
1509 |
dc->vmsd = &vmstate_pxa2xx_i2c; |
1510 |
dc->props = pxa2xx_i2c_properties; |
1511 |
} |
1512 |
|
1513 |
static TypeInfo pxa2xx_i2c_info = {
|
1514 |
.name = "pxa2xx_i2c",
|
1515 |
.parent = TYPE_SYS_BUS_DEVICE, |
1516 |
.instance_size = sizeof(PXA2xxI2CState),
|
1517 |
.class_init = pxa2xx_i2c_class_init, |
1518 |
}; |
1519 |
|
1520 |
/* PXA Inter-IC Sound Controller */
|
1521 |
static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) |
1522 |
{ |
1523 |
i2s->rx_len = 0;
|
1524 |
i2s->tx_len = 0;
|
1525 |
i2s->fifo_len = 0;
|
1526 |
i2s->clk = 0x1a;
|
1527 |
i2s->control[0] = 0x00; |
1528 |
i2s->control[1] = 0x00; |
1529 |
i2s->status = 0x00;
|
1530 |
i2s->mask = 0x00;
|
1531 |
} |
1532 |
|
1533 |
#define SACR_TFTH(val) ((val >> 8) & 0xf) |
1534 |
#define SACR_RFTH(val) ((val >> 12) & 0xf) |
1535 |
#define SACR_DREC(val) (val & (1 << 3)) |
1536 |
#define SACR_DPRL(val) (val & (1 << 4)) |
1537 |
|
1538 |
static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) |
1539 |
{ |
1540 |
int rfs, tfs;
|
1541 |
rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
|
1542 |
!SACR_DREC(i2s->control[1]);
|
1543 |
tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
|
1544 |
i2s->enable && !SACR_DPRL(i2s->control[1]);
|
1545 |
|
1546 |
qemu_set_irq(i2s->rx_dma, rfs); |
1547 |
qemu_set_irq(i2s->tx_dma, tfs); |
1548 |
|
1549 |
i2s->status &= 0xe0;
|
1550 |
if (i2s->fifo_len < 16 || !i2s->enable) |
1551 |
i2s->status |= 1 << 0; /* TNF */ |
1552 |
if (i2s->rx_len)
|
1553 |
i2s->status |= 1 << 1; /* RNE */ |
1554 |
if (i2s->enable)
|
1555 |
i2s->status |= 1 << 2; /* BSY */ |
1556 |
if (tfs)
|
1557 |
i2s->status |= 1 << 3; /* TFS */ |
1558 |
if (rfs)
|
1559 |
i2s->status |= 1 << 4; /* RFS */ |
1560 |
if (!(i2s->tx_len && i2s->enable))
|
1561 |
i2s->status |= i2s->fifo_len << 8; /* TFL */ |
1562 |
i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ |
1563 |
|
1564 |
qemu_set_irq(i2s->irq, i2s->status & i2s->mask); |
1565 |
} |
1566 |
|
1567 |
#define SACR0 0x00 /* Serial Audio Global Control register */ |
1568 |
#define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ |
1569 |
#define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ |
1570 |
#define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ |
1571 |
#define SAICR 0x18 /* Serial Audio Interrupt Clear register */ |
1572 |
#define SADIV 0x60 /* Serial Audio Clock Divider register */ |
1573 |
#define SADR 0x80 /* Serial Audio Data register */ |
1574 |
|
1575 |
static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, |
1576 |
unsigned size)
|
1577 |
{ |
1578 |
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
1579 |
|
1580 |
switch (addr) {
|
1581 |
case SACR0:
|
1582 |
return s->control[0]; |
1583 |
case SACR1:
|
1584 |
return s->control[1]; |
1585 |
case SASR0:
|
1586 |
return s->status;
|
1587 |
case SAIMR:
|
1588 |
return s->mask;
|
1589 |
case SAICR:
|
1590 |
return 0; |
1591 |
case SADIV:
|
1592 |
return s->clk;
|
1593 |
case SADR:
|
1594 |
if (s->rx_len > 0) { |
1595 |
s->rx_len --; |
1596 |
pxa2xx_i2s_update(s); |
1597 |
return s->codec_in(s->opaque);
|
1598 |
} |
1599 |
return 0; |
1600 |
default:
|
1601 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1602 |
break;
|
1603 |
} |
1604 |
return 0; |
1605 |
} |
1606 |
|
1607 |
static void pxa2xx_i2s_write(void *opaque, hwaddr addr, |
1608 |
uint64_t value, unsigned size)
|
1609 |
{ |
1610 |
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
1611 |
uint32_t *sample; |
1612 |
|
1613 |
switch (addr) {
|
1614 |
case SACR0:
|
1615 |
if (value & (1 << 3)) /* RST */ |
1616 |
pxa2xx_i2s_reset(s); |
1617 |
s->control[0] = value & 0xff3d; |
1618 |
if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ |
1619 |
for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) |
1620 |
s->codec_out(s->opaque, *sample); |
1621 |
s->status &= ~(1 << 7); /* I2SOFF */ |
1622 |
} |
1623 |
if (value & (1 << 4)) /* EFWR */ |
1624 |
printf("%s: Attempt to use special function\n", __FUNCTION__);
|
1625 |
s->enable = (value & 9) == 1; /* ENB && !RST*/ |
1626 |
pxa2xx_i2s_update(s); |
1627 |
break;
|
1628 |
case SACR1:
|
1629 |
s->control[1] = value & 0x0039; |
1630 |
if (value & (1 << 5)) /* ENLBF */ |
1631 |
printf("%s: Attempt to use loopback function\n", __FUNCTION__);
|
1632 |
if (value & (1 << 4)) /* DPRL */ |
1633 |
s->fifo_len = 0;
|
1634 |
pxa2xx_i2s_update(s); |
1635 |
break;
|
1636 |
case SAIMR:
|
1637 |
s->mask = value & 0x0078;
|
1638 |
pxa2xx_i2s_update(s); |
1639 |
break;
|
1640 |
case SAICR:
|
1641 |
s->status &= ~(value & (3 << 5)); |
1642 |
pxa2xx_i2s_update(s); |
1643 |
break;
|
1644 |
case SADIV:
|
1645 |
s->clk = value & 0x007f;
|
1646 |
break;
|
1647 |
case SADR:
|
1648 |
if (s->tx_len && s->enable) {
|
1649 |
s->tx_len --; |
1650 |
pxa2xx_i2s_update(s); |
1651 |
s->codec_out(s->opaque, value); |
1652 |
} else if (s->fifo_len < 16) { |
1653 |
s->fifo[s->fifo_len ++] = value; |
1654 |
pxa2xx_i2s_update(s); |
1655 |
} |
1656 |
break;
|
1657 |
default:
|
1658 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1659 |
} |
1660 |
} |
1661 |
|
1662 |
static const MemoryRegionOps pxa2xx_i2s_ops = { |
1663 |
.read = pxa2xx_i2s_read, |
1664 |
.write = pxa2xx_i2s_write, |
1665 |
.endianness = DEVICE_NATIVE_ENDIAN, |
1666 |
}; |
1667 |
|
1668 |
static const VMStateDescription vmstate_pxa2xx_i2s = { |
1669 |
.name = "pxa2xx_i2s",
|
1670 |
.version_id = 0,
|
1671 |
.minimum_version_id = 0,
|
1672 |
.minimum_version_id_old = 0,
|
1673 |
.fields = (VMStateField[]) { |
1674 |
VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
|
1675 |
VMSTATE_UINT32(status, PXA2xxI2SState), |
1676 |
VMSTATE_UINT32(mask, PXA2xxI2SState), |
1677 |
VMSTATE_UINT32(clk, PXA2xxI2SState), |
1678 |
VMSTATE_INT32(enable, PXA2xxI2SState), |
1679 |
VMSTATE_INT32(rx_len, PXA2xxI2SState), |
1680 |
VMSTATE_INT32(tx_len, PXA2xxI2SState), |
1681 |
VMSTATE_INT32(fifo_len, PXA2xxI2SState), |
1682 |
VMSTATE_END_OF_LIST() |
1683 |
} |
1684 |
}; |
1685 |
|
1686 |
static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) |
1687 |
{ |
1688 |
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
1689 |
uint32_t *sample; |
1690 |
|
1691 |
/* Signal FIFO errors */
|
1692 |
if (s->enable && s->tx_len)
|
1693 |
s->status |= 1 << 5; /* TUR */ |
1694 |
if (s->enable && s->rx_len)
|
1695 |
s->status |= 1 << 6; /* ROR */ |
1696 |
|
1697 |
/* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
|
1698 |
* handle the cases where it makes a difference. */
|
1699 |
s->tx_len = tx - s->fifo_len; |
1700 |
s->rx_len = rx; |
1701 |
/* Note that is s->codec_out wasn't set, we wouldn't get called. */
|
1702 |
if (s->enable)
|
1703 |
for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
|
1704 |
s->codec_out(s->opaque, *sample); |
1705 |
pxa2xx_i2s_update(s); |
1706 |
} |
1707 |
|
1708 |
static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
|
1709 |
hwaddr base, |
1710 |
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) |
1711 |
{ |
1712 |
PXA2xxI2SState *s = (PXA2xxI2SState *) |
1713 |
g_malloc0(sizeof(PXA2xxI2SState));
|
1714 |
|
1715 |
s->irq = irq; |
1716 |
s->rx_dma = rx_dma; |
1717 |
s->tx_dma = tx_dma; |
1718 |
s->data_req = pxa2xx_i2s_data_req; |
1719 |
|
1720 |
pxa2xx_i2s_reset(s); |
1721 |
|
1722 |
memory_region_init_io(&s->iomem, &pxa2xx_i2s_ops, s, |
1723 |
"pxa2xx-i2s", 0x100000); |
1724 |
memory_region_add_subregion(sysmem, base, &s->iomem); |
1725 |
|
1726 |
vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
|
1727 |
|
1728 |
return s;
|
1729 |
} |
1730 |
|
1731 |
/* PXA Fast Infra-red Communications Port */
|
1732 |
struct PXA2xxFIrState {
|
1733 |
MemoryRegion iomem; |
1734 |
qemu_irq irq; |
1735 |
qemu_irq rx_dma; |
1736 |
qemu_irq tx_dma; |
1737 |
int enable;
|
1738 |
CharDriverState *chr; |
1739 |
|
1740 |
uint8_t control[3];
|
1741 |
uint8_t status[2];
|
1742 |
|
1743 |
int rx_len;
|
1744 |
int rx_start;
|
1745 |
uint8_t rx_fifo[64];
|
1746 |
}; |
1747 |
|
1748 |
static void pxa2xx_fir_reset(PXA2xxFIrState *s) |
1749 |
{ |
1750 |
s->control[0] = 0x00; |
1751 |
s->control[1] = 0x00; |
1752 |
s->control[2] = 0x00; |
1753 |
s->status[0] = 0x00; |
1754 |
s->status[1] = 0x00; |
1755 |
s->enable = 0;
|
1756 |
} |
1757 |
|
1758 |
static inline void pxa2xx_fir_update(PXA2xxFIrState *s) |
1759 |
{ |
1760 |
static const int tresh[4] = { 8, 16, 32, 0 }; |
1761 |
int intr = 0; |
1762 |
if ((s->control[0] & (1 << 4)) && /* RXE */ |
1763 |
s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ |
1764 |
s->status[0] |= 1 << 4; /* RFS */ |
1765 |
else
|
1766 |
s->status[0] &= ~(1 << 4); /* RFS */ |
1767 |
if (s->control[0] & (1 << 3)) /* TXE */ |
1768 |
s->status[0] |= 1 << 3; /* TFS */ |
1769 |
else
|
1770 |
s->status[0] &= ~(1 << 3); /* TFS */ |
1771 |
if (s->rx_len)
|
1772 |
s->status[1] |= 1 << 2; /* RNE */ |
1773 |
else
|
1774 |
s->status[1] &= ~(1 << 2); /* RNE */ |
1775 |
if (s->control[0] & (1 << 4)) /* RXE */ |
1776 |
s->status[1] |= 1 << 0; /* RSY */ |
1777 |
else
|
1778 |
s->status[1] &= ~(1 << 0); /* RSY */ |
1779 |
|
1780 |
intr |= (s->control[0] & (1 << 5)) && /* RIE */ |
1781 |
(s->status[0] & (1 << 4)); /* RFS */ |
1782 |
intr |= (s->control[0] & (1 << 6)) && /* TIE */ |
1783 |
(s->status[0] & (1 << 3)); /* TFS */ |
1784 |
intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ |
1785 |
(s->status[0] & (1 << 6)); /* EOC */ |
1786 |
intr |= (s->control[0] & (1 << 2)) && /* TUS */ |
1787 |
(s->status[0] & (1 << 1)); /* TUR */ |
1788 |
intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ |
1789 |
|
1790 |
qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); |
1791 |
qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); |
1792 |
|
1793 |
qemu_set_irq(s->irq, intr && s->enable); |
1794 |
} |
1795 |
|
1796 |
#define ICCR0 0x00 /* FICP Control register 0 */ |
1797 |
#define ICCR1 0x04 /* FICP Control register 1 */ |
1798 |
#define ICCR2 0x08 /* FICP Control register 2 */ |
1799 |
#define ICDR 0x0c /* FICP Data register */ |
1800 |
#define ICSR0 0x14 /* FICP Status register 0 */ |
1801 |
#define ICSR1 0x18 /* FICP Status register 1 */ |
1802 |
#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ |
1803 |
|
1804 |
static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, |
1805 |
unsigned size)
|
1806 |
{ |
1807 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
1808 |
uint8_t ret; |
1809 |
|
1810 |
switch (addr) {
|
1811 |
case ICCR0:
|
1812 |
return s->control[0]; |
1813 |
case ICCR1:
|
1814 |
return s->control[1]; |
1815 |
case ICCR2:
|
1816 |
return s->control[2]; |
1817 |
case ICDR:
|
1818 |
s->status[0] &= ~0x01; |
1819 |
s->status[1] &= ~0x72; |
1820 |
if (s->rx_len) {
|
1821 |
s->rx_len --; |
1822 |
ret = s->rx_fifo[s->rx_start ++]; |
1823 |
s->rx_start &= 63;
|
1824 |
pxa2xx_fir_update(s); |
1825 |
return ret;
|
1826 |
} |
1827 |
printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
|
1828 |
break;
|
1829 |
case ICSR0:
|
1830 |
return s->status[0]; |
1831 |
case ICSR1:
|
1832 |
return s->status[1] | (1 << 3); /* TNF */ |
1833 |
case ICFOR:
|
1834 |
return s->rx_len;
|
1835 |
default:
|
1836 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1837 |
break;
|
1838 |
} |
1839 |
return 0; |
1840 |
} |
1841 |
|
1842 |
static void pxa2xx_fir_write(void *opaque, hwaddr addr, |
1843 |
uint64_t value64, unsigned size)
|
1844 |
{ |
1845 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
1846 |
uint32_t value = value64; |
1847 |
uint8_t ch; |
1848 |
|
1849 |
switch (addr) {
|
1850 |
case ICCR0:
|
1851 |
s->control[0] = value;
|
1852 |
if (!(value & (1 << 4))) /* RXE */ |
1853 |
s->rx_len = s->rx_start = 0;
|
1854 |
if (!(value & (1 << 3))) { /* TXE */ |
1855 |
/* Nop */
|
1856 |
} |
1857 |
s->enable = value & 1; /* ITR */ |
1858 |
if (!s->enable)
|
1859 |
s->status[0] = 0; |
1860 |
pxa2xx_fir_update(s); |
1861 |
break;
|
1862 |
case ICCR1:
|
1863 |
s->control[1] = value;
|
1864 |
break;
|
1865 |
case ICCR2:
|
1866 |
s->control[2] = value & 0x3f; |
1867 |
pxa2xx_fir_update(s); |
1868 |
break;
|
1869 |
case ICDR:
|
1870 |
if (s->control[2] & (1 << 2)) /* TXP */ |
1871 |
ch = value; |
1872 |
else
|
1873 |
ch = ~value; |
1874 |
if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */ |
1875 |
qemu_chr_fe_write(s->chr, &ch, 1);
|
1876 |
break;
|
1877 |
case ICSR0:
|
1878 |
s->status[0] &= ~(value & 0x66); |
1879 |
pxa2xx_fir_update(s); |
1880 |
break;
|
1881 |
case ICFOR:
|
1882 |
break;
|
1883 |
default:
|
1884 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1885 |
} |
1886 |
} |
1887 |
|
1888 |
static const MemoryRegionOps pxa2xx_fir_ops = { |
1889 |
.read = pxa2xx_fir_read, |
1890 |
.write = pxa2xx_fir_write, |
1891 |
.endianness = DEVICE_NATIVE_ENDIAN, |
1892 |
}; |
1893 |
|
1894 |
static int pxa2xx_fir_is_empty(void *opaque) |
1895 |
{ |
1896 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
1897 |
return (s->rx_len < 64); |
1898 |
} |
1899 |
|
1900 |
static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) |
1901 |
{ |
1902 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
1903 |
if (!(s->control[0] & (1 << 4))) /* RXE */ |
1904 |
return;
|
1905 |
|
1906 |
while (size --) {
|
1907 |
s->status[1] |= 1 << 4; /* EOF */ |
1908 |
if (s->rx_len >= 64) { |
1909 |
s->status[1] |= 1 << 6; /* ROR */ |
1910 |
break;
|
1911 |
} |
1912 |
|
1913 |
if (s->control[2] & (1 << 3)) /* RXP */ |
1914 |
s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
|
1915 |
else
|
1916 |
s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
|
1917 |
} |
1918 |
|
1919 |
pxa2xx_fir_update(s); |
1920 |
} |
1921 |
|
1922 |
static void pxa2xx_fir_event(void *opaque, int event) |
1923 |
{ |
1924 |
} |
1925 |
|
1926 |
static void pxa2xx_fir_save(QEMUFile *f, void *opaque) |
1927 |
{ |
1928 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
1929 |
int i;
|
1930 |
|
1931 |
qemu_put_be32(f, s->enable); |
1932 |
|
1933 |
qemu_put_8s(f, &s->control[0]);
|
1934 |
qemu_put_8s(f, &s->control[1]);
|
1935 |
qemu_put_8s(f, &s->control[2]);
|
1936 |
qemu_put_8s(f, &s->status[0]);
|
1937 |
qemu_put_8s(f, &s->status[1]);
|
1938 |
|
1939 |
qemu_put_byte(f, s->rx_len); |
1940 |
for (i = 0; i < s->rx_len; i ++) |
1941 |
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
|
1942 |
} |
1943 |
|
1944 |
static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) |
1945 |
{ |
1946 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
1947 |
int i;
|
1948 |
|
1949 |
s->enable = qemu_get_be32(f); |
1950 |
|
1951 |
qemu_get_8s(f, &s->control[0]);
|
1952 |
qemu_get_8s(f, &s->control[1]);
|
1953 |
qemu_get_8s(f, &s->control[2]);
|
1954 |
qemu_get_8s(f, &s->status[0]);
|
1955 |
qemu_get_8s(f, &s->status[1]);
|
1956 |
|
1957 |
s->rx_len = qemu_get_byte(f); |
1958 |
s->rx_start = 0;
|
1959 |
for (i = 0; i < s->rx_len; i ++) |
1960 |
s->rx_fifo[i] = qemu_get_byte(f); |
1961 |
|
1962 |
return 0; |
1963 |
} |
1964 |
|
1965 |
static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
|
1966 |
hwaddr base, |
1967 |
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma, |
1968 |
CharDriverState *chr) |
1969 |
{ |
1970 |
PXA2xxFIrState *s = (PXA2xxFIrState *) |
1971 |
g_malloc0(sizeof(PXA2xxFIrState));
|
1972 |
|
1973 |
s->irq = irq; |
1974 |
s->rx_dma = rx_dma; |
1975 |
s->tx_dma = tx_dma; |
1976 |
s->chr = chr; |
1977 |
|
1978 |
pxa2xx_fir_reset(s); |
1979 |
|
1980 |
memory_region_init_io(&s->iomem, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000); |
1981 |
memory_region_add_subregion(sysmem, base, &s->iomem); |
1982 |
|
1983 |
if (chr)
|
1984 |
qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, |
1985 |
pxa2xx_fir_rx, pxa2xx_fir_event, s); |
1986 |
|
1987 |
register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save, |
1988 |
pxa2xx_fir_load, s); |
1989 |
|
1990 |
return s;
|
1991 |
} |
1992 |
|
1993 |
static void pxa2xx_reset(void *opaque, int line, int level) |
1994 |
{ |
1995 |
PXA2xxState *s = (PXA2xxState *) opaque; |
1996 |
|
1997 |
if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ |
1998 |
cpu_reset(CPU(s->cpu)); |
1999 |
/* TODO: reset peripherals */
|
2000 |
} |
2001 |
} |
2002 |
|
2003 |
/* Initialise a PXA270 integrated chip (ARM based core). */
|
2004 |
PXA2xxState *pxa270_init(MemoryRegion *address_space, |
2005 |
unsigned int sdram_size, const char *revision) |
2006 |
{ |
2007 |
PXA2xxState *s; |
2008 |
int i;
|
2009 |
DriveInfo *dinfo; |
2010 |
s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
|
2011 |
|
2012 |
if (revision && strncmp(revision, "pxa27", 5)) { |
2013 |
fprintf(stderr, "Machine requires a PXA27x processor.\n");
|
2014 |
exit(1);
|
2015 |
} |
2016 |
if (!revision)
|
2017 |
revision = "pxa270";
|
2018 |
|
2019 |
s->cpu = cpu_arm_init(revision); |
2020 |
if (s->cpu == NULL) { |
2021 |
fprintf(stderr, "Unable to find CPU definition\n");
|
2022 |
exit(1);
|
2023 |
} |
2024 |
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; |
2025 |
|
2026 |
/* SDRAM & Internal Memory Storage */
|
2027 |
memory_region_init_ram(&s->sdram, "pxa270.sdram", sdram_size);
|
2028 |
vmstate_register_ram_global(&s->sdram); |
2029 |
memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); |
2030 |
memory_region_init_ram(&s->internal, "pxa270.internal", 0x40000); |
2031 |
vmstate_register_ram_global(&s->internal); |
2032 |
memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, |
2033 |
&s->internal); |
2034 |
|
2035 |
s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
|
2036 |
|
2037 |
s->dma = pxa27x_dma_init(0x40000000,
|
2038 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); |
2039 |
|
2040 |
sysbus_create_varargs("pxa27x-timer", 0x40a00000, |
2041 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
|
2042 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
|
2043 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
|
2044 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
|
2045 |
qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), |
2046 |
NULL);
|
2047 |
|
2048 |
s->gpio = pxa2xx_gpio_init(0x40e00000, &s->cpu->env, s->pic, 121); |
2049 |
|
2050 |
dinfo = drive_get(IF_SD, 0, 0); |
2051 |
if (!dinfo) {
|
2052 |
fprintf(stderr, "qemu: missing SecureDigital device\n");
|
2053 |
exit(1);
|
2054 |
} |
2055 |
s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv,
|
2056 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), |
2057 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), |
2058 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); |
2059 |
|
2060 |
for (i = 0; pxa270_serial[i].io_base; i++) { |
2061 |
if (serial_hds[i]) {
|
2062 |
serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
|
2063 |
qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), |
2064 |
14857000 / 16, serial_hds[i], |
2065 |
DEVICE_NATIVE_ENDIAN); |
2066 |
} else {
|
2067 |
break;
|
2068 |
} |
2069 |
} |
2070 |
if (serial_hds[i])
|
2071 |
s->fir = pxa2xx_fir_init(address_space, 0x40800000,
|
2072 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), |
2073 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), |
2074 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), |
2075 |
serial_hds[i]); |
2076 |
|
2077 |
s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
|
2078 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
2079 |
|
2080 |
s->cm_base = 0x41300000;
|
2081 |
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ |
2082 |
s->clkcfg = 0x00000009; /* Turbo mode active */ |
2083 |
memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); |
2084 |
memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); |
2085 |
vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); |
2086 |
|
2087 |
pxa2xx_setup_cp14(s); |
2088 |
|
2089 |
s->mm_base = 0x48000000;
|
2090 |
s->mm_regs[MDMRS >> 2] = 0x00020002; |
2091 |
s->mm_regs[MDREFR >> 2] = 0x03ca4000; |
2092 |
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ |
2093 |
memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); |
2094 |
memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); |
2095 |
vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); |
2096 |
|
2097 |
s->pm_base = 0x40f00000;
|
2098 |
memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); |
2099 |
memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); |
2100 |
vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); |
2101 |
|
2102 |
for (i = 0; pxa27x_ssp[i].io_base; i ++); |
2103 |
s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
|
2104 |
for (i = 0; pxa27x_ssp[i].io_base; i ++) { |
2105 |
DeviceState *dev; |
2106 |
dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
|
2107 |
qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); |
2108 |
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
|
2109 |
} |
2110 |
|
2111 |
if (usb_enabled) {
|
2112 |
sysbus_create_simple("sysbus-ohci", 0x4c000000, |
2113 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); |
2114 |
} |
2115 |
|
2116 |
s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); |
2117 |
s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); |
2118 |
|
2119 |
sysbus_create_simple("pxa2xx_rtc", 0x40900000, |
2120 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); |
2121 |
|
2122 |
s->i2c[0] = pxa2xx_i2c_init(0x40301600, |
2123 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
|
2124 |
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, |
2125 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
|
2126 |
|
2127 |
s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
|
2128 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), |
2129 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), |
2130 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); |
2131 |
|
2132 |
s->kp = pxa27x_keypad_init(address_space, 0x41500000,
|
2133 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); |
2134 |
|
2135 |
/* GPIO1 resets the processor */
|
2136 |
/* The handler can be overridden by board-specific code */
|
2137 |
qdev_connect_gpio_out(s->gpio, 1, s->reset);
|
2138 |
return s;
|
2139 |
} |
2140 |
|
2141 |
/* Initialise a PXA255 integrated chip (ARM based core). */
|
2142 |
PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) |
2143 |
{ |
2144 |
PXA2xxState *s; |
2145 |
int i;
|
2146 |
DriveInfo *dinfo; |
2147 |
|
2148 |
s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
|
2149 |
|
2150 |
s->cpu = cpu_arm_init("pxa255");
|
2151 |
if (s->cpu == NULL) { |
2152 |
fprintf(stderr, "Unable to find CPU definition\n");
|
2153 |
exit(1);
|
2154 |
} |
2155 |
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; |
2156 |
|
2157 |
/* SDRAM & Internal Memory Storage */
|
2158 |
memory_region_init_ram(&s->sdram, "pxa255.sdram", sdram_size);
|
2159 |
vmstate_register_ram_global(&s->sdram); |
2160 |
memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); |
2161 |
memory_region_init_ram(&s->internal, "pxa255.internal",
|
2162 |
PXA2XX_INTERNAL_SIZE); |
2163 |
vmstate_register_ram_global(&s->internal); |
2164 |
memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, |
2165 |
&s->internal); |
2166 |
|
2167 |
s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
|
2168 |
|
2169 |
s->dma = pxa255_dma_init(0x40000000,
|
2170 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); |
2171 |
|
2172 |
sysbus_create_varargs("pxa25x-timer", 0x40a00000, |
2173 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
|
2174 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
|
2175 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
|
2176 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
|
2177 |
NULL);
|
2178 |
|
2179 |
s->gpio = pxa2xx_gpio_init(0x40e00000, &s->cpu->env, s->pic, 85); |
2180 |
|
2181 |
dinfo = drive_get(IF_SD, 0, 0); |
2182 |
if (!dinfo) {
|
2183 |
fprintf(stderr, "qemu: missing SecureDigital device\n");
|
2184 |
exit(1);
|
2185 |
} |
2186 |
s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv,
|
2187 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), |
2188 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), |
2189 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); |
2190 |
|
2191 |
for (i = 0; pxa255_serial[i].io_base; i++) { |
2192 |
if (serial_hds[i]) {
|
2193 |
serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
|
2194 |
qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), |
2195 |
14745600 / 16, serial_hds[i], |
2196 |
DEVICE_NATIVE_ENDIAN); |
2197 |
} else {
|
2198 |
break;
|
2199 |
} |
2200 |
} |
2201 |
if (serial_hds[i])
|
2202 |
s->fir = pxa2xx_fir_init(address_space, 0x40800000,
|
2203 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), |
2204 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), |
2205 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), |
2206 |
serial_hds[i]); |
2207 |
|
2208 |
s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
|
2209 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
2210 |
|
2211 |
s->cm_base = 0x41300000;
|
2212 |
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ |
2213 |
s->clkcfg = 0x00000009; /* Turbo mode active */ |
2214 |
memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); |
2215 |
memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); |
2216 |
vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); |
2217 |
|
2218 |
pxa2xx_setup_cp14(s); |
2219 |
|
2220 |
s->mm_base = 0x48000000;
|
2221 |
s->mm_regs[MDMRS >> 2] = 0x00020002; |
2222 |
s->mm_regs[MDREFR >> 2] = 0x03ca4000; |
2223 |
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ |
2224 |
memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); |
2225 |
memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); |
2226 |
vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); |
2227 |
|
2228 |
s->pm_base = 0x40f00000;
|
2229 |
memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); |
2230 |
memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); |
2231 |
vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); |
2232 |
|
2233 |
for (i = 0; pxa255_ssp[i].io_base; i ++); |
2234 |
s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
|
2235 |
for (i = 0; pxa255_ssp[i].io_base; i ++) { |
2236 |
DeviceState *dev; |
2237 |
dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
|
2238 |
qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); |
2239 |
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
|
2240 |
} |
2241 |
|
2242 |
if (usb_enabled) {
|
2243 |
sysbus_create_simple("sysbus-ohci", 0x4c000000, |
2244 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); |
2245 |
} |
2246 |
|
2247 |
s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); |
2248 |
s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); |
2249 |
|
2250 |
sysbus_create_simple("pxa2xx_rtc", 0x40900000, |
2251 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); |
2252 |
|
2253 |
s->i2c[0] = pxa2xx_i2c_init(0x40301600, |
2254 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
|
2255 |
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, |
2256 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
|
2257 |
|
2258 |
s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
|
2259 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), |
2260 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), |
2261 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); |
2262 |
|
2263 |
/* GPIO1 resets the processor */
|
2264 |
/* The handler can be overridden by board-specific code */
|
2265 |
qdev_connect_gpio_out(s->gpio, 1, s->reset);
|
2266 |
return s;
|
2267 |
} |
2268 |
|
2269 |
static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) |
2270 |
{ |
2271 |
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
2272 |
|
2273 |
sdc->init = pxa2xx_ssp_init; |
2274 |
} |
2275 |
|
2276 |
static TypeInfo pxa2xx_ssp_info = {
|
2277 |
.name = "pxa2xx-ssp",
|
2278 |
.parent = TYPE_SYS_BUS_DEVICE, |
2279 |
.instance_size = sizeof(PXA2xxSSPState),
|
2280 |
.class_init = pxa2xx_ssp_class_init, |
2281 |
}; |
2282 |
|
2283 |
static void pxa2xx_register_types(void) |
2284 |
{ |
2285 |
type_register_static(&pxa2xx_i2c_slave_info); |
2286 |
type_register_static(&pxa2xx_ssp_info); |
2287 |
type_register_static(&pxa2xx_i2c_info); |
2288 |
type_register_static(&pxa2xx_rtc_sysbus_info); |
2289 |
} |
2290 |
|
2291 |
type_init(pxa2xx_register_types) |